JPH10283256A - Memory bus connection system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the connection control of a memory bus without designing or manufacturing a circuit board again by providing a memory bus connection conversion means between a main memory means and a memory access control means. SOLUTION: When address signals, data signals and control signals are inputted from a central processing unit 1, in a memory access control part 2, the respective signals are converted to the signals corresponding to the input condition of a memory cell inside a main memory unit 4, outputted and inputted to the input terminal 3a of a memory bus connection conversion part 3. The respective signals inputted to the memory bus connection conversion part 3 are outputted from an output terminal connected to the input terminal among the output terminals 3b and inputted to the memory cells 4a-4d. Then, by the main memory unit 4, the write or read operation of data is performed. The kind of the memory cells 4a-4d is changed there, and in the case that a memory address signal line number is increased, it is made possible by changing the connection data of the internal signal line 3c of the memory bus connection conversion part 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory bus connection system between a central processing unit and a main storage device, and more particularly to a memory bus connection system capable of arbitrarily changing the connection of a memory bus.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing one configuration example of a conventional memory bus connection system.

In this conventional example, as shown in FIG. 4, a main memory (MEM) 4 including a plurality of memory elements 4a to 4d,
A central processing unit (C) for outputting a signal to the main storage device 4
PU) 1 and a memory access control unit (MA) that converts a signal output from the central processing unit 1 into a signal according to input conditions of the memory elements 4a to 4d in the main storage device 4 and outputs the signal.
C) 2, and the central processing unit 1 and the memory access control unit 2 are connected by a bus, and the memory access control unit 2 and the main storage device 4 are connected by a bus.

In the memory bus connection system configured as described above, when an address signal, a data signal, and a control signal are output from the central processing unit 1, the memory access control unit 2 converts the signals into a main storage device. The signals are converted into signals according to the input conditions of the memory elements 4 a to 4 d in the memory 4 and output to the main storage device 4. Thereafter, data writing or reading operation is performed in the main storage device 4.

In the above-described memory bus connection method, the memory access control unit 2 and the main storage device 4 correspond to the types of the memory elements in the main storage device 4 (the number of data signals, the number of address signals, etc.). Is predetermined, and the connection is fixed.

[0006]

In recent years, the development of memory elements has been rapidly progressing, and the memory capacity has been increased, the number of data signals has been increased, and control signals have been changed frequently. In order to make the connection of the memory bus compatible with the latest memory element in the market, it is necessary to change the connection between the memory access control unit and the memory element, but in the conventional memory bus connection method as described above, The connection between the memory access control unit and the memory element is predetermined according to the type of the memory element used, and the memory access control unit and the memory element are physically and fixedly connected. Therefore, when the connection between the memory access control unit and the memory element is changed, it is necessary to redesign the board on which the components are mounted, and there is a problem that economic efficiency and responsiveness are lacking.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has been developed in consideration of the design and circuit board design even when the type of memory element in the main storage device is changed. It is an object of the present invention to provide a memory bus connection method capable of connecting a memory bus without performing manufacturing again.

[0008]

In order to achieve the above object, the present invention provides a main memory comprising a plurality of memory elements;
Central processing means for outputting a signal to the main storage means;
Memory access control means for converting a signal output from the central processing means into a signal in accordance with an input condition of the memory element and outputting the signal, and wherein the central processing means, the memory access control means, and the memory access control Means and the main storage means are connected by a bus, respectively.
In a memory bus connection system in which a data write or read operation is performed in the main storage unit in accordance with a signal output from the central processing unit, the memory element and the memory access control unit are provided between the main storage unit and the memory access control unit. It is characterized by having a memory bus connection conversion means for controlling connection with the memory access control means.

Further, the memory bus connection conversion means is constituted by a logic circuit element capable of changing data programmably.

Further, the memory bus connection conversion means is a physical switch.

(Operation) In the present invention configured as described above, the connection between the memory element and the memory access control means is controlled by the memory bus connection conversion means.
Even when the type of the memory element is changed, the connection between the memory element and the memory access control means is changed only by changing the connection data or the connection setting of the memory bus connection conversion means.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a memory bus connection system according to the present invention.

In this embodiment, as shown in FIG. 1, a main memory (MEM) 4 comprising a plurality of memory elements 4a to 4d, and a central processing unit (CP) for outputting a signal to the main memory 4
U) 1 and a memory access control unit (MAC) that converts a signal output from the central processing unit 1 into a signal according to input conditions of the memory elements 4 a to 4 d in the main storage device 4 and outputs the signal.
2 and a memory bus connection conversion unit (CNV) 3 which is composed of a logic circuit element capable of changing data programmably and controls connection between the memory elements 4a to 4d and the memory access control unit 2. The central processing unit 1 is connected to the memory access control unit 2, the memory access control unit 2 is connected to the memory bus connection conversion unit 3, and the memory bus connection conversion unit 3 is connected to the main storage device 4 via a bus.

The connection operation in the memory bus connection system configured as described above will be described below.

FIG. 2 is a diagram for explaining a connection operation in the memory bus connection system shown in FIG.

First, an address signal from the central processing unit 1
When the data signal and the control signal are output, the memory access control unit 2 converts the signals into signals according to the input conditions of the memory elements in the main storage device 4 and outputs the signals.

The address signal, data signal and control signal converted by the memory access control unit 2 are input to an input terminal 3a of the memory bus connection conversion unit 3.

Here, in the memory bus connection converter 3, the input terminal 3a and the output terminal 3d are arbitrarily connected in advance, and the address signal, data signal and control signal input to the input terminal 3a are output. The output from the output terminal to which the input terminal is connected among the terminals 3b is output to the memory element 4
a to 4d.

Thereafter, in the main storage device 4, data write or read operation is performed according to the input address signal, data signal and control signal.

Here, when the type of the memory elements 4a to 4d is changed and the number of memory address signal lines is increased, the memory access control unit 2 and the memory elements 4a to 4d
Must be changed, but can be changed by changing the connection data of the internal signal line 3c of the memory bus connection conversion unit 3. When the signal accommodation of the memory elements 4a to 4d is changed, the memory bus connection conversion unit 3
Can be changed by changing the internal connection data.

In the above-described embodiment, the memory bus connection conversion unit 3 has been described as being constituted by a logic circuit element capable of programmably changing data, but instead of the logic circuit element, It is also possible to provide a physical switch and control the connection between the memory access control unit 2 and the memory elements 4a to 4d by the switch.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 3A and 3B are views showing one embodiment of the memory bus connection system shown in FIGS. 1 and 2, wherein FIG. 3A is a board mounting diagram, and FIG. FIG. 3 is a circuit diagram of a programmable logic array 13 for use in the present invention.

In this embodiment, as shown in FIG.
A central processing unit 11, a memory access control integrated circuit 12, a memory bus connection conversion programmable logic array 13, and a memory chip 14 are mounted thereon.

The operation in the memory bus connection conversion system configured as described above will be described below.

When a memory read or write operation is performed, first, a memory bus signal including an address signal, a data signal, and a control signal is output from the central processing unit 11 and the output memory bus signal is output to the circuit board 7. Is input to the memory access control integrated circuit 12 via the signal pattern of

When the memory bus signal is input to the memory access control integrated circuit 12, the input memory bus signal is converted in the memory access control integrated circuit 12 so as to meet the signal input condition of the memory chip 14, The converted signal is output.

The signal output from the memory access control integrated circuit 12 is input to the memory bus connection conversion programmable logic array 13 via a signal pattern on the circuit board 7.

In the programmable logic array 13 for converting the memory bus connection, connection data between the input terminal and the output terminal is written in advance, and according to this connection,
The input signal is transferred to the output terminal and output.

A signal output from the memory bus connection conversion programmable logic array 13 is input to the memory chip 14 via a signal pattern on the circuit board 7.
In the memory chip 4, a memory read or write operation is performed according to the input signal.

Here, for example, the type of the memory chip 14 is changed from 4M DRAM (4M × 1b) to 16M DRAM.
(4M × 4b), the data signal line becomes 3
Since the number of signals is increased, the terminal arrangement of the memory chip 14 is different. Therefore, the connection data of the programmable logic array 13 for memory bus connection conversion is transferred to the 16M DR.
Operation is possible by rewriting according to the terminal arrangement of AM.

However, it is assumed that the signal patterns between the memory bus connection conversion programmable logic array 3 and the memory chips 14 are pre-wired on the circuit board 7 including spare signals.

[0034]

As described above, in the present invention,
Since the memory bus connection conversion means for controlling the connection between the memory element and the memory access control means is provided between the main storage means and the memory access control means, even when the type of the memory element is changed, The connection of the memory bus can be changed without redesigning and manufacturing.

As a result, the productivity can be improved, and the responsiveness when the type of the memory element is changed can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a memory bus connection system according to the present invention.

FIG. 2 is a diagram for explaining a connection operation in the memory bus connection system shown in FIG. 1;

FIGS. 3A and 3B are diagrams showing one embodiment of the memory bus connection system shown in FIGS. 1 and 2, wherein FIG. 3A is a board mounting diagram, and FIG. 3B is a programmable logic for memory bus connection conversion shown in FIG. It is a circuit diagram of an array.

FIG. 4 is a diagram showing a configuration example of a conventional memory bus connection method.

[Explanation of symbols]

1,11 central processing unit 2 memory access control unit 3 memory bus connection conversion unit 3a input terminal 3c internal signal line 3d output terminal 4 main storage device 4a to 4d memory element 5a processor bus address signal 5b processor bus data signal 5c processor bus control Signal 6a Memory bus address signal 6b Memory bus data signal 6c Memory bus control signal 7 Circuit board 12 Integrated circuit for memory access control 13 Programmable logic array for memory bus connection conversion

Claims (3)

[Claims] 1. A main storage means comprising a plurality of memory elements, a central processing means for outputting a signal to the main storage means, and a signal output from the central processing means being a signal according to an input condition of the memory element. A memory access control unit for converting the data into a central processing unit and the memory access control unit; and connecting the memory access control unit and the main storage unit via a bus, respectively. In a memory bus connection system in which a data write or read operation in the main storage means is performed according to a signal output from a processing means, the memory element and the memory access are provided between the main storage means and the memory access control means. A memory bus connection method comprising a memory bus connection conversion means for controlling connection with a control means. . 2. The memory bus connection system according to claim 1, wherein said memory bus connection conversion means comprises a logic circuit element capable of changing data in a programmable manner. method. 3. The memory bus connection method according to claim 1, wherein said memory bus connection conversion means is a physical switch.