JP2001111051A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can reduce its parasitic capacity while avoiding a remarkably increased number of process steps in the prior art. SOLUTION: The method for manufacturing a semiconductor device includes steps of (A) forming a conductor layer 155 patterned on a substrate 10, (B) forming a side wall on a side wall of the conductor layer 15 in a self alignment manner, (C) forming entirely a first insulating layer 31 with the top of the side wall being exposed, (D) removing the side wall to form a gap 32 between the first insulating layer 31 and conductor layer 15, and (E) forming a second insulating layer 33 on the conductor and first insulating layers 15 and 31 so as not to bury the gap 32.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device with reduced parasitic capacitance and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor devices, the degree of integration has been improved twice in three years in accordance with the scaling law, and accordingly, high speed and low power consumption of semiconductor devices have been continuously achieved. The miniaturization of the MOS FET has been achieved by reducing the size of the gate electrode, reducing the thickness of the gate insulating film, and controlling the impurity concentration profile in or near the channel formation region with high precision. With miniaturization of semiconductor devices, improvement of driving capability of semiconductor devices, reduction of parasitic capacitance, and the like have been attempted. In general, in a CMOS circuit, the operation speed is determined by the charge (or discharge) speed at which the output of a logic gate of a certain stage drives the capacitive load of the logic gate of the next stage. Therefore,
The operation speed is proportional to each of the reciprocal of the capacitance of the capacitive load and the driving capability.

[0003] By the way, the thickness of the gate electrode is not reduced according to the scaling law due to the requirement based on the resistance value of the gate electrode. That is, even if the gate length of the gate electrode is reduced, it is difficult to reduce the thickness of the gate electrode at the same ratio, and the aspect ratio of the gate electrode (the ratio between the thickness of the gate electrode and the gate length) tends to increase. It is in. Therefore,
The proportion of the fringe capacitance, which is one of the parasitic capacitances of the transistor, in the entire parasitic capacitance is increasing as compared with other parasitic capacitances. Here, the fringe capacitance is a parasitic capacitance generated between the side wall of the gate electrode and the source / drain region.

In recent years, in order to accurately control an impurity concentration profile of a channel formation region formed on a semiconductor substrate or a region of the semiconductor substrate adjacent to the channel formation region, a side wall of a gate electrode is formed in a semiconductor device manufacturing process. Many techniques for forming a wall are used. FIG. 8A is a schematic partial cross-sectional view of a conventional semiconductor device. 8, reference numeral 10 is a silicon semiconductor substrate, reference numeral 11 is an element isolation region, and reference numeral 1
2 is a gate insulating film, reference numeral 13 is a polysilicon layer forming a gate electrode, reference numeral 14 is a silicide layer forming a gate electrode, reference numeral 15 is a gate electrode, reference numeral 20 is an extension region, and reference numeral 23 is a source. /
The drain region, reference numeral 222 is a sidewall, reference numeral 231 is an insulating layer, reference numeral 234 is a contact hole, and reference numeral 235 is a wiring. The sidewalls 222 are made of silicon nitride (SiN) or polysilicon, which provides high processing accuracy, in addition to silicon oxide (SiO ₂ ). These silicon nitrides and polysilicon are compared with silicon oxide. The value of the relative dielectric constant ε is high.
The relative permittivity シ リ コ ン of silicon oxide is 4.2 to 4.4, while the relative permittivity シ リ コ ン of silicon nitride is 6 to 7.

When the sidewall 222 is made of a material having a high relative dielectric constant ε, the fringe capacitance becomes large as shown in FIG. 8B, and the gate electrode 15 As the value of the aspect ratio increases, the value of the fringe capacitance further increases. As described above, in a next-generation semiconductor device in which a fine transistor having a gate electrode 15 having a low resistance and a high aspect ratio is required to accurately control an impurity concentration profile and improve an operation speed, a fringe is used. The relative increase in the capacity is a major obstacle in improving the performance of the semiconductor device.

Further, with miniaturization of the semiconductor device, a parasitic capacitance generated between the gate electrode 15 and the contact hole 234 has become a problem. Since the sidewall 222 and the insulating layer 231 are interposed between the gate electrode 15 and the contact hole 234, if the sidewall 222 is made of silicon nitride (SiN) having a large relative dielectric constant ε, the gate electrode 15 and contact hole 234
It is difficult to reduce the parasitic capacitance between the two.

[0007]

In order to reduce various capacitances, it is most effective to reduce the relative dielectric constant of a portion where an electric field is easily concentrated due to its structure. In general, when a pair of electrodes are formed from an infinitely wide parallel plate, the electric field between the electrodes is uniform. However, when the areas of the two electrodes are different, the larger the area difference, the larger the area. The closer the electrode is to the electrode, the more the electric field concentrates. Furthermore, the electric field concentrates as the distance between the electrodes is shorter. Therefore, in the semiconductor device, the electric field is concentrated on the portion of the semiconductor substrate near the side wall of the gate electrode based on the fringe capacitance. On the other hand, based on the parasitic capacitance between the gate electrode and the contact hole, the electric field concentrates closer to the contact hole.

Means for reducing the fringe capacity are disclosed in, for example, JP-A-7-193233 and JP-A-9-24.
It is known from JP-A-6544 and JP-A-11-17166.

In the method disclosed in JP-A-7-193233, a vacuum region is formed near the side wall of the gate electrode. However, in the method disclosed in this patent publication, it is necessary to form a silicon layer on the source / drain regions by a selective growth method, which complicates the process. Further, in order to enhance the selectivity of Si growth on the surface of the oxide film and the surface of the silicon semiconductor substrate, there is a problem that a facet is generated at the end of the growth region and a vacuum region is hardly formed near the side wall of the gate electrode. In addition, since facets are formed, the opening after removing the sidewalls becomes large, and it is difficult to form an oxide film while forming a vacuum region, that is, without embedding such a region.

In the method disclosed in Japanese Patent Application Laid-Open No. 9-246544 or Japanese Patent Application Laid-Open No. 11-17166, a double or triple sidewall is formed on a side wall of a gate electrode, and then the side wall closest to the side wall of the gate electrode is formed. In this method, a void is formed near the side wall of the gate electrode by removing the sidewall. These methods, however, require the formation of double or triple sidewalls and are complex. Also, JP-A-11-171
According to the method disclosed in JP-A-66-66, no void is formed in the portion of the semiconductor substrate near the sidewall of the gate electrode which is most needed, and it is difficult to sufficiently reduce the fringe capacitance. Moreover, the method disclosed in Japanese Patent Application Laid-Open No. 9-246544 or Japanese Patent Application Laid-Open No. 11-17166 cannot substantially reduce the parasitic capacitance between the gate electrode and the contact hole.

Accordingly, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can reduce the parasitic capacitance without increasing the number of conventional process steps.

[0012]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device comprising: a patterned conductive layer; and (b) an insulating layer formed on a base including the conductive layer, wherein the insulating layer includes a first insulating layer; A second insulating layer formed on the first insulating layer, wherein the thickness of the first insulating layer is substantially equal to or greater than the thickness of the conductor layer, and A gap is formed between the layer and the side wall of the conductor layer.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises: (A) a step of forming a patterned conductive layer on a substrate; and (B) a step of forming a patterned conductive layer on a side wall of the conductive layer. Forming a sidewall in a self-aligned manner;
(C) a step of forming a first insulating layer on which the top of the sidewall is exposed on the entire surface; and (D) a step of removing the sidewall and forming a gap between the first insulating layer and the conductor layer. And (E) forming a second insulating layer on the conductor layer and the first insulating layer so as not to fill the void.

The combination of the substrate and the conductor layer in the semiconductor device of the present invention or the method of manufacturing the semiconductor device of the present invention includes a combination of the substrate as a semiconductor layer and the conductor layer as a gate electrode in a field-effect transistor. Can be. In the former combination, a gate insulating film is formed between the semiconductor layer as the base and the gate electrode as the conductor layer. In this case, a channel formation region is formed in a region of the semiconductor layer below the gate electrode, and source / drain regions can be formed in the semiconductor layer with the channel formation region interposed therebetween. Can be configured such that an extension region is formed in a region of the semiconductor layer located between each source / drain region and the channel formation region and below the gap, if necessary. .

In the method of manufacturing a semiconductor device according to the present invention, in the step (A), a gate insulating film is formed on the surface of the base, and then a conductive material layer and a polishing stop layer are formed on the gate insulating film. Are sequentially formed, and thereafter, the polishing stop layer and the conductive material layer are patterned, and the step (B) is performed.
In (2), sidewalls are formed in a self-aligning manner on sidewalls of the conductor layer and the polishing stop layer. In the step (C), after forming a first insulating layer on the entire surface, the top of the sidewall is exposed. Until the first insulating layer is chemically /
The polishing may be performed by a mechanical polishing method (CMP method). Alternatively, in the step (C), based on a high-density plasma CVD method (HDP-CVD method),
The first insulating layer can be formed under the condition that the first insulating layer is not deposited on the top surface of the conductor layer and the top of the sidewall. Further, in the step (C), after the first insulating layer is formed on the entire surface, the first insulating layer is subjected to an etch back method or a PACE until the top of the sidewall is exposed.
(Plasma Assisted Chemical Etching) may be removed to form a first insulating layer on the entire surface where the top of the sidewall is exposed. PACE processing, which is a type of local plasma etching, is described in, for example, PB Mumola et el.,
2nd Inter. Symp. On Semiconductor Wafer Bonding S
cience, Technology and Application (The Electroche
mical Society, Pennungton, NJ, 1994.) and the like.

In the method for manufacturing a semiconductor device according to the present invention,
When the conductor layer is used as a gate electrode in a field-effect transistor, a first impurity introduction step of introducing an impurity into the semiconductor layer is performed between the step (A) and the step (B), and the step (B) is performed. And a second impurity introduction step of introducing an impurity into the semiconductor layer between the step (C) and the step (C).
A channel formation region is formed in a region of the semiconductor layer below the gate electrode, and a source / drain region is formed in the semiconductor layer with the channel formation region interposed therebetween, and a source / drain region is formed between each source / drain region and the channel formation region. In addition, an extension region can be formed in a region of the semiconductor layer located below the gap. Alternatively, an impurity introduction step of introducing an impurity into the semiconductor layer is performed between the step (A) and the step (B), thereby forming a channel formation region in a region of the semiconductor layer below the gate electrode, A structure in which source / drain regions are formed in the semiconductor layer with the channel formation region interposed therebetween can be employed.

Alternatively, as a combination of the substrate and the conductor layer in the semiconductor device of the present invention or the method of manufacturing the semiconductor device of the present invention, a wiring in which the substrate is an insulating material layer and the conductor layer is formed on the insulating material layer Can be listed. In this case, the insulating material layer is formed, for example, on or above the semiconductor substrate or the semiconductor layer.

The semiconductor layer constituting the substrate may be composed of, for example, a silicon semiconductor substrate itself, or a so-called SOI (Semiconductor-On-Insulator) formed on an insulating film formed on the surface of the support. ) Layers. When the semiconductor layer is composed of the silicon semiconductor substrate itself, the semiconductor device is a so-called bulk semiconductor device. When the semiconductor layer is composed of the SOI layer, the semiconductor device is a so-called SOI semiconductor device. The semiconductor layer may be composed of Si or Si-G
It may be composed of an e mixed crystal system.

As a method for forming the SOI layer, a semiconductor substrate and a support substrate are bonded together via an insulating film, and then the semiconductor substrate is ground and polished from the back surface, whereby a support made of the support substrate, an insulating film, Substrate bonding method to obtain a semiconductor layer consisting of a semiconductor substrate after grinding and polishing. After forming an insulating film on the semiconductor substrate, implanting hydrogen ions into the semiconductor substrate and forming a peeling layer inside the semiconductor substrate. The substrate and the supporting substrate are bonded to each other with an insulating film interposed therebetween, and then the semiconductor substrate is separated (cleaved) from the separation layer by performing a heat treatment, and the remaining semiconductor substrate is ground and polished from the back surface, so that the substrate is separated from the supporting substrate. Smart cut method to obtain a semiconductor layer consisting of a support, an insulating film, and a semiconductor substrate after grinding and polishing. After that, a heat treatment is performed to form an insulating film inside the semiconductor substrate, a support consisting of a part of the semiconductor substrate below the insulating film, and a part of the semiconductor substrate above the insulating film. SIMOX (Separation b)
y IMplanted OXygen) method By forming a single crystal semiconductor layer in a gas phase or a solid phase on an insulating film formed on a semiconductor substrate corresponding to a support, a support consisting of a semiconductor substrate, an insulating film, A method of obtaining a semiconductor layer composed of a crystalline semiconductor layer By forming an insulating film by partially making the surface of the semiconductor substrate porous by anodic oxidation, a support comprising a part of the semiconductor substrate under the insulating film, And a method for obtaining a semiconductor layer composed of a part of a semiconductor substrate on an insulating film.

When the conductor layer is composed of a gate electrode, the gate electrode only needs to be composed of at least a polysilicon layer. That is, the gate electrode may be composed of one polysilicon layer, may have a two-layer structure (polycide structure) of a polysilicon layer and a silicide layer, or may have a polysilicon layer and a metal layer such as tungsten. It may have a two-layer structure. When the conductor layer is formed of a wiring, the wiring can be formed of a conductive polysilicon layer, a metal layer, an alloy layer, a metal compound layer, or a laminated structure of these.

The first insulating layer is made of a material having a relatively low relative dielectric constant ε, silicon oxide (SiO ₂ ), SOG (Spin On Glass), PSG (PhosphoSilica).
te Glass), BPSG (Boro-PhosphoSilicate Glas)
s), BSG, AsSG, PbSG, SbSG, NS
G, LTO (Low Temperature Oxide, Low Temperature CVD-S
iO ₂ ), HTO (High Temperature Oxide, high temperature CV)
D-SiO ₂ ), a low dielectric constant insulating material having a relative dielectric constant of 3.5 or less (for example, polyaryl ether, cycloperfluorocarbon polymer, benzocyclobutene), an organic polymer material such as polyimide, or a material such as these. Laminated ones can be mentioned.

When forming the second insulating layer, it is necessary to form the second insulating layer on the conductor layer and on the first insulating layer so as not to fill the voids. Low-coverage CVD method, in other words, supply-limited CV
D method, specifically, normal pressure CVD method or plasma C method
It is desirable to form a film by the VD method. As a material forming the second insulating layer, a material having a relatively low relative dielectric constant ε, silicon oxide (SiO ₂ ), SOG (Spin On Glass),
PSG (PhosphoSilicate Glass), BPSG (Boro-Ph
osphoSilicate Glass), BSG, AsSG, PbS
G, SbSG, NSG, LTO, a low dielectric constant insulating material having a relative dielectric constant of 3.5 or less (for example, polyarylether,
Organic polymer materials such as cycloperfluorocarbon polymer, benzocyclobutene) and polyimide, or a laminate of these materials can be used.

The sidewalls are eventually removed from the semiconductor device. Therefore, when the sidewall is removed by, for example, an etching method to form a gap between the first insulating layer and the conductor layer, the material forming the first insulating layer and the material forming the sidewall are mixed. The sidewall may be made of a material having an etching selectivity therebetween. Specifically, as a material forming the sidewall, silicon nitride (SiN) or polysilicon can be given.

The polishing stop layer may be made of a material having a polishing selectivity between the material forming the first insulating layer and the material forming the polishing stop layer. Specifically, as a material constituting the polishing stop layer, silicon nitride (Si
N).

The impurity concentration of the extension region may be lower, equal to, or higher than the impurity concentration of the source / drain region. In short, the impurity concentration of the extension region may be determined based on characteristics required for the semiconductor device. The junction depth of the extension region (the depth from the surface of the semiconductor layer to the bottom of the extension region) must be smaller than the junction depth of the source / drain region (the depth from the surface of the semiconductor layer to the bottom of the source / drain region). Is done.

In the present invention, since a gap (relative permittivity ε is about 1) is formed between the first insulating layer and the side wall of the conductor layer, the gap is formed between the side wall of the conductor layer and the base. And the value of the parasitic capacitance between adjacent conductor layers can be reduced.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings based on embodiments of the present invention (hereinafter, abbreviated as embodiments).

(Embodiment 1) Embodiment 1 relates to a semiconductor device of the present invention and a method of manufacturing the same. As shown in a schematic partial cross-sectional view in FIG. 5, the semiconductor device according to the first embodiment is formed on a base 10, and is formed by patterning a conductive layer 15 and a base 10 including the conductive layer 15. And an insulating layer formed on the substrate. The insulating layer is a first insulating layer 31
And a second insulating layer 33 formed on the first insulating layer 31
Consisting of The thickness of the first insulating layer 31 is larger than the thickness of the conductor layer 15, and a gap 32 is formed between the first insulating layer 31 and the side wall of the conductor layer 15. The relative permittivity ε of the gap 32 is about 1.

In the first embodiment, the base is a semiconductor layer (more specifically, a silicon semiconductor substrate 10), and the conductor layer is a gate electrode 15 in a field effect transistor (FET). Silicon semiconductor substrate 1 as base
A gate insulating film 12 is formed between the gate electrode 15 and the gate electrode 15 which is a conductor layer. Further, a channel formation region 24 is formed in a region of the silicon semiconductor substrate 10 below the gate electrode 15, and the channel formation region 24 is interposed therebetween.
The source / drain regions 23 are formed in the silicon semiconductor substrate 10.
Are formed. Further, each source / drain region 2
An extension region 20 is formed in a region of the silicon semiconductor substrate 10 located between the channel formation region 3 and the channel formation region 24 and below the gap 32. The gate electrode 15 is formed of a polysilicon layer 13 containing impurities.
And a polycide structure composed of two layers of a silicide layer 14. Reference numeral 11 denotes an element isolation region, reference numeral 16 denotes an offset oxide film, reference numeral 34 denotes a contact hole, and reference numeral 35 denotes a wiring.

Hereinafter, a method of manufacturing the semiconductor device shown in FIG. 5 will be described with reference to FIGS.

[Step-100] First, a gate electrode 15 as a patterned conductor layer is formed on a silicon semiconductor substrate 10 as a base. Specifically, first, an element isolation region 11 having a trench structure is formed in the silicon semiconductor substrate 10 by a known method, and then well ion implantation, channel stop ion implantation, and threshold adjustment ion implantation are performed. Note that the element isolation region 11 may have a LOCOS structure or a combination of a LOCOS structure and a trench structure. Thereafter, the surface of the silicon semiconductor substrate 10 is subjected to, for example, thermal oxidation to a thickness of about
A gate insulating film 12 of 5 nm is formed (see FIG. 1A). Next, for example, a polysilicon layer 1 having a thickness of 70 nm
3. A silicide layer 14 made of tungsten silicide having a thickness of 70 nm is formed on the entire surface by a known CVD method. Then, the polysilicon layer 1 is formed based on the ion implantation method.
Impurities are introduced into 3 (see FIG. 1B), and then an annealing process is performed to activate the introduced impurities.
Note that an n-type impurity such as phosphorus is introduced into the polysilicon layer 13 for forming an n-channel type semiconductor device (N-MOS) to form a p-channel type semiconductor device (P-MOS). A p-type impurity such as boron is introduced into the polysilicon layer 13. In some cases, the polysilicon layer 13 containing impurities may be formed in advance.

Thereafter, an offset oxide film 16 made of silicon oxide (SiO ₂ ) having a thickness of about 0.15 μm is deposited on the entire surface by the CVD method.
A silicon nitride (S) having a thickness of about 0.1 μm
A polishing stop layer 17 of iN) is deposited. The offset oxide film 16 is used for the silicon semiconductor substrate 1 in a later step.
When the source / drain regions are formed at 0, they are formed to prevent impurities from being introduced into the polysilicon layer 13. Thereafter, the polishing stop layer 17, the offset oxide film 16, the silicide layer 14, and the doped polysilicon layer 13 are patterned based on the lithography technique and the dry etching technique. Thus, a gate electrode 15 having a polycide structure in which the polysilicon layer 13 into which the impurities are introduced and the silicide layer 14 made of tungsten silicide can be obtained (see FIG. 1C). An offset oxide film 16 and a polishing stop layer 17 are formed on the gate electrode 15.

[Step-110] Next, a first impurity introduction step of introducing an impurity into the silicon semiconductor substrate 10 as a semiconductor layer by an ion implantation method is executed to form an extension region 20 (FIG. 2). (A)). Specifically, for example, when manufacturing a CMOS, a region of the silicon semiconductor substrate 10 on which a p-channel semiconductor device is to be formed is covered with a resist material (not shown), and arsenic (As) which is an n-type impurity is formed. ) Is ion-implanted into the silicon semiconductor substrate 10. Next, the resist material is removed, a region of the silicon semiconductor substrate 10 where an n-channel type semiconductor device is to be formed is covered with a resist material (not shown), and boron (B) as a p-type impurity is applied to the silicon semiconductor substrate 10. After the ion implantation, the resist material is removed. Thereafter, activation heat treatment for the introduced impurities is performed by RTA (Rapid Thermal Anneal).
aling) method.

[Step-120] Thereafter, although not essential, a silicon oxide film 21 having a thickness of about 10 nm is
-It is desirable to form a film by a CVD method. By forming the silicon oxide film 21, it is possible to prevent the silicon semiconductor substrate 10 from being damaged when the sidewall is formed. In addition, the silicon oxide film 2
If 1 is finally left on the side wall of the gate electrode 15, the polysilicon layer 13 forming the gate electrode 15 can be prevented from being altered or the like. The conditions for forming the silicon oxide film 21 are exemplified in Table 1 below.

[Table 1] Gas used: TEOS = 300 sccm Pressure: 93 Pa Substrate temperature: 700 ° C.

Next, on the silicon oxide film 21, a thickness of about 0.
Deposit a 1 μm layer of silicon nitride. Table 2 below shows examples of conditions for forming the silicon nitride layer. Thereafter, the silicon nitride layer is selectively removed by an etch-back method under the conditions exemplified in Table 3 below, and the gate electrode 15 serving as a conductor layer is removed.
In addition, sidewalls 22 are formed on the side walls of the offset oxide film 16 and the polishing stop layer 17 in a self-aligned manner (see FIG. 2B). The thickness at the lower portion of the sidewall 22 (the thickness in the direction parallel to the surface of the silicon semiconductor substrate 10) is about 0.1 μm, and the height of the sidewall 22 (the height along the side wall of the gate electrode 15) is about 0 μm. .3
μm. In addition, since the silicon oxide film 21 is also formed on the surface of the silicon semiconductor substrate 10, it is possible to prevent the silicon semiconductor substrate 10 from being damaged when the silicon nitride layer is etched back.

[Table 2] Film forming conditions for silicon nitride layer Gas used: SiH ₂ Cl ₂ / NH ₃ = 50/500 sccm Pressure: 35 Pa Substrate temperature: 760 ° C

[Table 3] Etch-back conditions for silicon nitride layer Gas used: CF ₄ / Ar = 50/950 sccm Pressure: 105 Pa Substrate temperature: 0 ° C. RF power: 200 W

[Step-130] Thereafter, a second impurity introduction step of introducing an impurity into the silicon semiconductor substrate 10 as a semiconductor layer is performed, and a channel formation region is formed in a region of the silicon semiconductor substrate 10 below the gate electrode 15. 24, and the source / drain regions 23 are formed in the silicon semiconductor substrate 10 with the channel formation region 24 interposed therebetween.
(C)). The extension region 20 is formed between the source / drain regions 23 and the channel forming region 24 and in a region of the silicon semiconductor substrate 10 located below the sidewall 22. Specifically, for example, when manufacturing a CMOS, a region of the silicon semiconductor substrate 10 on which a p-channel semiconductor device is to be formed is covered with a resist material (not shown), and arsenic (As) which is an n-type impurity is formed. ) Is ion-implanted into the silicon semiconductor substrate 10. Next, the resist material is removed, a region of the silicon semiconductor substrate 10 where an n-channel type semiconductor device is to be formed is covered with a resist material (not shown), and boron (B) as a p-type impurity is applied to the silicon semiconductor substrate 10. After the ion implantation, the resist material is removed. After that, heat treatment for activating the introduced impurities is performed by the RTA method.

[Step-140] After that, the first insulating layer 31 with the top of the sidewall 22 exposed is formed on the entire surface. More specifically, after a first insulating layer 31 made of silicon oxide (SiO ₂ ) is formed on the entire surface by a CVD method (FIG. 3).
(A), and the first insulating layer is polished by the CMP method until the top of the sidewall 22 is exposed (see FIG. 3B). Since the polishing stop layer 17 is formed, excessive polishing of the first insulating layer 31 can be suppressed. The width of the exposed top of the side wall 22 is about 0.
1 μm.

[Step-150] Next, the sidewalls 22 are removed, and a gap 32 is formed between the first insulating layer 31 and the gate electrode 15 which is a conductor layer (FIG. 4A).
reference). Specifically, the sidewall 22 and the polishing stop layer 17 made of silicon nitride (SiN) are
It is removed based on the wet etching method exemplified in Table 4 below. Since there is a high etching selectivity between silicon oxide and silicon nitride, the first insulating layer 31 is hardly etched. In some cases, after removing the sidewalls 22, the exposed silicon oxide film 21 is removed.
May be removed using a hydrofluoric acid-based solution. At this time,
Although the first insulating layer 31 is also slightly etched, the etching amount is not a problematic amount.

[Table 4] Solution used: Hot phosphoric acid solution Temperature: 155 ° C Processing time: 80 minutes

[Step-160] After that, the gate electrode 15 and the first
A second insulating layer 33 is formed on the insulating layer 31 (see FIG. 4B). Specifically, the second insulating layer 33 made of PSG is formed by a CVD method having a low step coverage, in other words, by a supply-controlled CVD method, specifically, a normal pressure CVD method exemplified in Table 5 below. The film is formed. The width of the top of the gap 32 is about 0.1 μm, and normal pressure CVD
Since the second insulating layer 33 is formed by the method, the void is not filled with the second insulating layer 33.

[Table 5] Gas used: SiH ₄ / PH ₃ / O ₂ / N ₂ = 35 / 2.8 /
670 / 22000sccm Pressure: Atmospheric pressure Substrate temperature: 390 ° C

[Step-170] Thereafter, an opening is formed in the second insulating layer 33 and the first insulating layer 31 above the source / drain region 23, and the second insulating layer 3 including the inside of the opening is formed.
3 is formed on the second insulating layer 33 by patterning the wiring material layer.
5, and a contact hole 34 is formed in the opening. In the opening, a contact plug of polysilicon, metal, or metal compound is formed by a CVD method and a CMP method, or a CVD method and an etch-back method.
The wiring 35 may be formed on the insulating layer 33. Thus, a semiconductor device having the structure shown in FIG. 5 can be obtained.

(Embodiment 2) Embodiment 2 is a modification of Embodiment 1. As shown in a schematic partial cross-sectional view in FIG. 7B, the semiconductor device according to the second embodiment includes a substrate 1
Conductive layer 11 formed on and patterned on 10
5 and an insulating layer formed on the base 110 including the conductor layer 115. The insulating layer is a first insulating layer 13
1 and a second insulating layer 133 formed on the first insulating layer 131. The thickness of the first insulating layer 131 is substantially equal to the thickness of the conductor layer 115,
A gap 132 is formed between 31 and the side wall of conductor layer 115. The relative permittivity ε of the void 132 is about 1. In the second embodiment, the base is the insulating material layer 110 formed on the silicon semiconductor substrate (not shown), and the conductor layer is the wiring 115.

Hereinafter, a method of manufacturing the semiconductor device shown in FIG. 7B will be described with reference to FIGS.

[Step-200] First, a TiN layer / Al—Cu layer / TiN layer /
A wiring (conductor layer) 115 having a stacked structure of a Ti layer (= 50/400/20/20 nm) is formed based on a sputtering method, a lithography technique, and a dry etching technique (see FIG. 6A). Here, the Ti layer is the lowermost layer. In the drawing, the wiring 115 is represented by one layer.

[Step-210] Thereafter, a thin (for example, about 10 nm thick) SiO ₂ film (not shown) is formed on the entire surface to protect the wiring, and then a thickness of about 0.1 nm is formed on the SiO ₂ film. Deposit a 1 μm layer of silicon nitride. Plasma C
Table 6 shows the conditions for forming the silicon nitride layer by the VD method.
An example is shown below. Thereafter, the silicon nitride layer was selectively removed by an etch-back method under the same conditions as illustrated in Table 3,
A sidewall 122 is formed in a self-aligning manner on the side wall of the wiring 115 which is a conductor layer (see FIG. 6B). The thickness at the lower portion of the sidewall 22 (the insulating material layer 11
0 in the direction parallel to the surface) is about 0.1 μm,
The height of the sidewall 122 (height along the side wall of the wiring 115) was set to about 0.5 μm.

[Table 6] Film forming conditions of silicon nitride layer Gas used: SiH ₄ / NH ₃ / N ₂ = 290/90/4
000sccm Pressure: 500Pa RF Power: 700W Substrate Temperature: 400 ° C

[Step-220] After that, the first insulating layer 131 in which the top of the sidewall 122 is exposed is formed on the entire surface. Specifically, after the first insulating layer 131 made of silicon oxide (SiO ₂ ) is formed on the entire surface by the CVD method, the first insulating layer 131 is kept until the top of the sidewall 122 is exposed.
Is polished by the CMP method (FIG. 6C).
reference). The width of the exposed top of the sidewall 122 is about 0.1 μm.

[Step-230] Next, the sidewall 122 is removed, and a gap 132 is formed between the first insulating layer 131 and the wiring 115 serving as a conductor layer (see FIG. 7A). Specifically, the sidewall 122 made of silicon nitride (SiN) is removed based on the wet etching method illustrated in Table 4. Since there is a high etching selectivity between silicon oxide and silicon nitride, the first insulating layer 131 is hardly etched.

[Step-240] After that, a second insulating layer 133 is formed on the wiring 115 serving as a conductor layer and on the first insulating layer 131 so as not to fill the void 132 (FIG. 7).
(B)). Specifically, the second insulating layer 133 made of PSG is formed by a low step coverage CVD method.
In other words, the film is formed by the supply-limited CVD method, specifically, the normal pressure CVD method exemplified in Table 5. The width of the top of the gap 132 is about 0.1 μm, and normal pressure CVD
Since the second insulating layer 133 is formed by the method,
Is not buried by the insulating layer 133.

Although the present invention has been described based on the embodiments, the present invention is not limited to these embodiments. The structure, manufacturing conditions, and materials used of the semiconductor device described in the embodiment are merely examples, and can be changed as appropriate.

In the first embodiment, the source / drain region and the extension region are formed on the silicon semiconductor substrate. In [Step-110], instead of forming the extension region, the source / drain region is formed. A semiconductor device having a structure in which [Step-130] is omitted can also be manufactured. Accordingly, a semiconductor device having a so-called single-drain structure in which a channel formation region is formed in a region of the semiconductor layer below the gate electrode and source / drain regions are formed in the semiconductor layer with the channel formation region interposed therebetween. can do.

The structure of the gate electrode is not limited to the polycide structure, but may be a single-layer structure of a polysilicon layer or a two-layer structure of a polysilicon layer and a metal layer (for example, a tungsten layer). A polysilicon layer and a metal compound layer (for example, W
It may have a three-layer structure of an N layer) and a metal layer (for example, a tungsten layer). The formation of the offset oxide film 16 and the polishing stop layer 17 and the formation of the silicon oxide film 21 are not essential and can be omitted as appropriate.

In the embodiment, the sidewall 2
2, 122 is composed of a single silicon nitride layer, but instead has a two-layer configuration of a silicon oxide layer and a polysilicon layer, and a two-layer configuration of a silicon oxide layer and a silicon nitride layer from the conductor layer side. You can also. In these cases, in [Step-150], the sidewall portion formed of the polysilicon layer or the silicon nitride layer may be removed.

[0058]

According to the semiconductor device of the present invention, a gap (relative permittivity ε: about 1) is formed between the first insulating layer and the side wall of the conductor layer. The value of the fringe capacitance, which is the parasitic capacitance generated between the side wall of the electrode and the source / drain region, can be reduced, and the parasitic capacitance generated between the gate electrode and the contact hole can be reduced. Alternatively, for example, the parasitic capacitance between wirings can be reduced.

In the method of manufacturing a semiconductor device according to the present invention, a sidewall is formed from a material having good dimensional control such as silicon nitride during the process, and the sidewall is removed. A void having a desired shape and dimensions can be formed.

As a result of the above, for example, while controlling the impurity concentration profile in the silicon semiconductor substrate in the vicinity of the channel formation region with high accuracy, the short channel effect is suppressed, and the driving capability is excellent and the low parasitic capacitance is excellent. A semiconductor device can be obtained, and high speed and low power consumption of the semiconductor device can be achieved.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for describing a method of manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for explaining the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 1;

FIG. 3 is a schematic partial cross-sectional view of the silicon semiconductor substrate and the like for explaining the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 2;

FIG. 4 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for explaining the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 3;

FIG. 5 is a schematic partial cross-sectional view of the silicon semiconductor substrate and the like for explaining the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 4;

FIG. 6 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for describing a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for explaining the method for manufacturing the semiconductor device of the second embodiment of the invention, following FIG. 6;

FIG. 8 is a schematic partial cross-sectional view of a conventional semiconductor device and an enlarged schematic diagram of a part of the semiconductor device for describing a problem in the conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Silicon semiconductor substrate, 11 ... Element isolation region, 12 ... Gate insulating film, 13 ... Polysilicon layer, 14 ... Silicide layer, 15 ... Gate electrode,
16 ... offset oxide film, 17 ... polishing stop layer, 20 ... extension region, 21 ... silicon oxide film, 22 ... side wall, 23 ... source / drain region, 24 ... .Channel forming region, 3
DESCRIPTION OF SYMBOLS 1 ... 1st insulating layer, 32 ... air gap, 33 ... 2nd insulating layer, 34 ... contact hole, 35 ...
Wiring, 110: insulating material layer, 115: wiring, 1
22 ... side wall, 131 ... first insulating layer, 132 ... void, 133 ... second insulating layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 H01L 29/78 621 29/786 F-term (Reference) 5F032 AA09 AA13 AA35 AC01 BB01 CA17 CA20 5F033 HH09 HH18 HH33 MM08 PP15 QQ08 QQ09 QQ10 QQ11 QQ12 QQ19 QQ25 QQ35 QQ48 QQ59 QQ65 QQ73 RR04 RR30 SS03 SS04 SS13 SS15 TT02 TT08 VV06 XX24 5F040 DA00 DA01 DA02 DA11 DB03 DC01 EB12 EC03 EC04 EC04 EC03 EC04 EC04 EC04 FA12 FA16 FA17 FA18 FA19 FB02 FC00 FC22 5F048 AA08 AC03 BA01 BA16 BB06 BB07 BB08 BB09 BB12 BB13 BC06 BF03 BF16 BG12 BG14 DA18 DA19 DA20 DA21 DA24 DA25 DA30 5F110 AA02 BB04 CC02 DD05 DD13 EE05 EE03 EE01 EE01 EE50 GG02 GG12 HJ01 HJ13 HJ23 HL08 HL24 HM15 NN13 NN14 NN15 NN23 NN24 NN35 NN66 QQ04 QQ05 QQ17 QQ19

Claims (9)

[Claims] 1. A semiconductor device comprising: (a) a conductive layer formed on a substrate and patterned; and (b) an insulating layer formed on the substrate including the conductive layer. The insulating layer includes a first insulating layer and a second insulating layer formed on the first insulating layer. The thickness of the first insulating layer is substantially equal to the thickness of the conductor layer. ,
A semiconductor device having a thickness larger than a thickness of a conductor layer, wherein a gap is formed between a first insulating layer and a side wall of the conductor layer. 2. The semiconductor device according to claim 1, wherein the base is a semiconductor layer, the conductive layer is a gate electrode in a field effect transistor, and a gate insulating film is formed between the base and the conductive layer. 2. The semiconductor device according to 1. 3. The semiconductor device according to claim 1, wherein a channel formation region is formed in a region of the semiconductor layer below the gate electrode, and source / drain regions are formed in the semiconductor layer with the channel formation region interposed therebetween. Item 3. The semiconductor device according to item 2. 4. An extension region is formed in a region of the semiconductor layer located between each source / drain region and a channel formation region and below a gap. 4. The semiconductor device according to 3. 5. A step of forming a patterned conductor layer on a substrate, a step of forming a sidewall on the side wall of the conductor layer in a self-aligned manner, (E) forming a first insulating layer on the entire surface where the top of the wall is exposed; (D) forming a gap between the first insulating layer and the conductor layer by removing the side wall; A) forming a second insulating layer on the conductor layer and on the first insulating layer so as not to fill the voids. 6. The semiconductor device according to claim 1, wherein the base is a semiconductor layer, the conductive layer is a gate electrode in a field effect transistor, and a gate insulating film is formed between the base and the conductive layer. 6. The method for manufacturing a semiconductor device according to item 5. 7. In the step (A), a gate insulating film is formed on the surface of the base, a conductive material layer and a polishing stop layer are sequentially formed on the gate insulating film. In the step (B), sidewalls are formed in a self-aligned manner on the side walls of the conductor layer and the polishing stop layer. In the step (C), the first insulating layer is formed on the entire surface. 7. The method according to claim 6, wherein after forming the first insulating layer, the first insulating layer is polished by a chemical / mechanical polishing method until the top of the sidewall is exposed. 8. A first impurity introduction step for introducing an impurity into a semiconductor layer is performed between step (A) and step (B), and a semiconductor impurity is introduced between step (B) and step (C). Performing a second impurity introduction step of introducing impurities into the layer,
A channel formation region is formed in a region of the semiconductor layer below the gate electrode, and a source / drain region is formed in the semiconductor layer with the channel formation region interposed therebetween, and a source / drain region is formed between each source / drain region and the channel formation region. 7. The method according to claim 6, wherein an extension region is formed in a region of the semiconductor layer located below the gap. 9. A step of introducing an impurity into a semiconductor layer between the steps (A) and (B), thereby forming a channel formation region in a region of the semiconductor layer below the gate electrode. 7. A source / drain region is formed in the semiconductor layer with the channel forming region interposed therebetween.
13. The method for manufacturing a semiconductor device according to item 5.