JP2001111045A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fine semiconductor device which prevents halation and peeling phenomena and which is manufactured with low cost and high reliability, and also to provide a method for manufacturing the semiconductor device. SOLUTION: A P-SiON film 9 is formed on a tungsten silicide film 9. Consequently, an ultraviolet ray reflected from the tungsten silicide film 9 on a step part C of an LOCOS oxide film 2 is shielded to prevent a halation phenomenon. Even during an oxidizing atmosphere step of a P-TEOS oxide film 21 formed on the film 9, a peeling phenomenon of the film 9 being peeled off from a polycrystalline silicon film 8 at the step part C is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a step formed on a semiconductor substrate by a LOCOS oxide film or the like and having an insulated gate structure formed on the semiconductor substrate having the step. The present invention relates to a semiconductor device in which an electrode wiring is formed of a polycide film composed of a polycrystalline silicon film and a tungsten silicide film or a molybdenum silicide film, and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the recent miniaturization and high speed operation of a semiconductor device, a field effect transistor (MOSFE) constituting the semiconductor device has been developed.
In a gate electrode wiring such as T), a tungsten polycide structure in which a low-resistance tungsten silicide film is laminated on a polycrystalline silicon film is used in order to reduce the resistance of the gate electrode wiring.

FIGS. 13A and 13B are main part configuration diagrams of a conventional n-type MOSFET using a tungsten polycide structure. FIG. 13A is a plan view, and FIG. 13B is a sectional view taken on line AA of FIG. FIG. 3C is a cross-sectional view taken along line BB of FIG. 3A.

In FIG. 1A, this plan view shows a tungsten silicide film 59, a LOCOS oxide film 52, n
FIG. 6B shows the low-concentration and n-type high-concentration source regions 53 and 55 and the n-type low-concentration and n-type high-concentration drain regions 54 and 56, and the interlayer insulating film 6 shown in FIGS.
4, the source electrode wiring 65 and the drain electrode wiring 66 are not shown. The n-type low-concentration and high-concentration source regions 53 and 55 and the n-type low-concentration and n-type high-concentration drain regions 54 and 56 are surrounded by a LOCOS oxide film 52.

In FIG. 1B, a LOCOS oxide film 52 is selectively formed on a surface layer of a semiconductor substrate.
The surface layer of p well region 51 sandwiched between S oxide films 52 has n
Low-concentration and high-concentration source regions 53 and 55 and n-type low-concentration and high-concentration drain regions 54 and 56 are formed.
-Type lightly doped source region 53 and n-type lightly doped drain region 54
A gate electrode interconnection 80 is formed on p-well region 51 sandwiched between the gate oxide film 57 and a gate electrode interconnection 80 formed of a polycrystalline silicon film 58 and a tungsten silicide film 59 thereon. It is a polycide film. The polycrystalline silicon film 58 determines the threshold voltage of the MOSFET, and the tungsten silicide film 59
Functions to reduce the gate resistance. The gate electrode wiring 80 and the LOCOS oxide film 52 are covered with an interlayer insulating film 64. Further, contact holes are formed in the interlayer insulating film 64 and the second screen oxide film 63 on the n-type high-concentration source region 55 and the n-type high-concentration drain region 56, and a source electrode wiring 65 and a drain electrode wiring 66 are formed. At a location not shown, a contact hole is also formed in the interlayer insulating film 64 on the tungsten silicide film 59 to form a gate metal wiring connected to the gate electrode wiring 80.

In FIG. 1C, this cross-sectional view is a cross-sectional view of a main part of a gate electrode wiring portion. The gate oxide film 57 on the silicon surface and the gate oxide film 57
On the COS oxide film 52, a polycrystalline silicon film 58, a tungsten silicide film 59, and an interlayer insulating film 64 are laminated.

FIGS. 14 to 23 are cross-sectional views of a main part of a conventional method of manufacturing an n-type MOSFET using a tungsten polycide structure, which are shown in the order of steps.

LOCOS (Local Oxidati)
The p-well region 51 on which the LOCOS oxide film 52 for element isolation is formed by an on-silicon method.
The gate oxide film 57 and subsequently the polycrystalline silicon 58 are deposited under reduced pressure CVD (Chemical Vapor Deposition).
Ion) method, a tungsten silicide 59 is formed by a sputtering method or a CVD method (FIG. 14).

Next, a pattern of a photoresist 72 in a region to be the gate electrode wiring 80 is formed by photolithography (FIG. 15), and the tungsten silicide film 59 and the polycrystalline silicon film 58 are etched by anisotropic dry etching (FIG. 15). After that, the photoresist 72 is removed (FIG. 16).

Next, in the anisotropic etching of the tungsten silicide film 59, etching is usually performed with a high selectivity with respect to the gate oxide film so as not to damage silicon under the gate oxide film. Therefore, only the upper layer of the gate oxide film 57 is etched, and the gate oxide film near the silicon surface is left. The remaining gate oxide film is the remaining gate oxide film 57a. Thereafter, a first screen oxide film is formed on the remaining film 57a of the gate oxide film. Here, the first screen oxide film 62 including the gate oxide film 57a is formed (FIG. 17).

Next, in order to reduce electric field concentration accompanying miniaturization, an LDD (Lightly Doped Draft) is used.
in) A source region and a drain region having a structure are formed. The first ion implantation is performed at a lower concentration than the subsequent second ion implantation using the gate electrode wiring 80 as a mask, and n
The LDD structure is obtained by forming the low-concentration source region 53 and the low-concentration drain region 54 (FIG. 18).

Next, an oxide film 73 is formed by a low pressure CVD method (FIG. 19). This oxide film 73 is, for example, 7
It can be formed by using monosilane (SiH ₄ ) and nitrous oxide (N ₂ O) at a temperature of 50 to 850 ° C., and the oxide film 73 in this case is usually made of HTO (High Tempera).
cure oxide), which is excellent in step coverage.
Because of its excellent insulating properties, it has been used in various applications in MOSFET manufacturing processes.

Thereafter, etching is performed on the entire surface until the surface of silicon is exposed, thereby forming the gate electrode wiring 8.
The oxide film is left only on the 0 side wall. This oxide film becomes the spacer oxide film 61, and the first screen oxide film is completely removed during the etching process. Then, the second
A screen oxide film 63 is formed (FIG. 20).

Next, a second ion implantation is performed using the gate electrode wiring 80 and the spacer oxide film 61 as a mask.
This is performed at a higher concentration than the first ion implantation to form an n-type high-concentration source region 55 and an n-type high-concentration drain region 56 (FIG. 21). Thus, a MOSFET having a source region and a drain region having an LDD structure is obtained.

Next, an interlayer insulating film 64 is formed (FIG. 2).
2) Then, a source electrode wiring 65 and a drain electrode wiring 66 are formed (FIG. 23).

[0016]

The above-described process of manufacturing a MOSFET using a tungsten polycide structure has the following problems, particularly when the element is miniaturized. The problem will be described with reference to FIGS. 24 and 25.

The first problem will be described with reference to FIG. FIG. 24 is a cross-sectional view of a conventional main part manufacturing process when miniaturized, and FIG. 24A is a cross-sectional view corresponding to FIG.
FIG. 17B is a cross-sectional view corresponding to the cross-sectional view of the main part manufacturing process in FIG. FIG. 14C is a cross-sectional view corresponding to the cross-sectional view of the main part manufacturing process in FIG.

As shown in FIG. 1A, a tungsten silicide film 5 which is an upper layer of a tungsten polycide structure is formed.
Reference numeral 9 denotes a high-reflectance material, which has an absolute reflectance of 5 in an i-line (wavelength 365 nm) region required for forming fine wiring.
Up to 2%. Therefore, from the formation of the gate electrode wiring 80 by photolithography, the tungsten silicide film 5 running over the step D of the LOCOS oxide film
9, the gate electrode wiring 80
Since the pattern of the photoresist resist 72 that forms the pattern 72 has a regular shape indicated by a dotted line, a part of the pattern is exposed to the reflected light 86a, resulting in a problem that the photoresist 72a does not have a regular shape. This phenomenon is called a halation phenomenon, and becomes more remarkable as the material having a processing symmetry has a higher reflectance. Further, miniaturization progresses, and the distance between the gate electrode wiring and the step portion D of the LOCOS oxide film 52 becomes shorter. As the distance between the stepped end of the tungsten silicide film 59 and the patterned photoresist 72 decreases, the halation phenomenon becomes more conspicuous. When the tungsten silicide film having a tungsten polycide structure and the polycrystalline silicon film are etched with the resist mask subjected to the halation, the side walls thereof become tapered and do not become vertical side walls (FIG. 9B). In such a shape,
Gate electrode wiring 3 using tungsten polycide structure
If the pattern of 0 has density, the wiring width becomes narrower in the dense pattern (in extreme cases, the wiring may be disconnected),
In a sparse pattern, since the wiring width is wide, fine and accurate dimensional control in a semiconductor chip becomes difficult. Further, the source region and the drain region formed using the tungsten polycide structure as a mask are not formed to their dimensions because impurities of ion implantation pass through the tapered bottom polycrystalline silicon film. In the figure, the distance W1 between the normal n-type low-concentration source region and the n-type low-concentration drain region indicates that the n-type low-concentration source region and the n-type low-concentration drain region when the photoresist 72a that has undergone halation is used as a mask. There is a problem that the interval W2 becomes narrow (FIG. 3C). Therefore, it is difficult to miniaturize the element at a high yield rate.

Next, a second problem will be described with reference to FIG. FIG. 25 shows the manufacturing process of FIG.
It is sectional drawing corresponding to the cross section cut | disconnected by the BB line of (a).

As shown in FIG. 25, in the tungsten polycide structure, since the film stress of the tungsten silicide film 59 is large, the adhesion to the underlying polycrystalline silicon film 58 is low, and the tungsten silicide film 59 is formed of a polycrystalline silicon film. It is easy to peel off from 58. Further, when exposed to an oxidizing atmosphere during the manufacturing process, the silicon in the tungsten silicide film 59 is generally consumed and a silicon oxide film is formed. Abnormal oxidation occurs. When this abnormal oxidation occurs, the tungsten silicide film 59 is formed at the step D of the LOCOS oxide film 52.
When the adhesion between the tungsten silicide film 59 and the polycrystalline silicon film 58 is extremely reduced in combination with the large film stress of the polysilicon film 58, the tungsten silicide film 59a on the step D of the LOCOS oxide film 59 becomes polycrystalline silicon film 58.
And a gap 95 is formed. This phenomenon occurs in the manufacturing process of FIG. 17 and is increased in the manufacturing process of FIG. Such a phenomenon that the adhesion is extremely reduced and the tungsten silicide film peels from the polycrystalline silicon film is called peeling. With this phenomenon, the reliability of the gate electrode wiring 80 decreases.

An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a low-cost, highly reliable and miniaturized semiconductor device which prevents the above-mentioned halation phenomenon and peeling phenomenon, and a method of manufacturing the same.

[0022]

In order to achieve the above object, in a semiconductor device having an insulated gate structure, a gate electrode wiring comprises a polycide film and an oxynitride film formed on the polycide film. Configuration.

The polycide film may be composed of a polycrystalline silicon film and a tungsten silicide film or a molybdenum silicide film formed on the polycrystalline silicon film. The oxynitride film is preferably a plasma oxynitride film (P-SiON).

In a method of manufacturing a semiconductor device having an insulated gate structure formed on a semiconductor substrate having a step,
Forming a polycrystalline silicon film covering the step, forming a tungsten silicide film or a molybdenum silicide film on the polycrystalline silicon film, and forming an oxynitride film on the tungsten silicide film or the molybdenum silicide film Forming a tetraethylorthosilicate oxide film (TEOS oxide film) on the oxynitride film, forming a resist film on the TEOS oxide film, exposing and developing the resist film. ,
Forming a resist mask, using the resist mask to selectively remove the TEOS oxide film and the oxynitride film by etching, removing the resist mask, and removing the TEOS oxide film and the oxynitride film. As a mask,
The polycrystalline silicon film and the tungsten silicide film or the molybdenum silicide film are removed by anisotropic etching.
A manufacturing method includes an OS oxide film and a step of removing an upper layer of the oxynitride film.

The thickness of the oxynitride film formed on the tungsten silicide film or the molybdenum silicide film is 20 nm or more and 40 nm or less, and the thickness of the TEOS oxide film formed on the oxynitride film is , 10
The thickness is preferably from 0 nm to 200 nm.

Preferably, the oxynitride film and the TEOS oxide film are a plasma oxynitride film and a plasma TEOS oxide film, respectively, formed by a plasma CVD method.

With the above-described structure, the halation phenomenon due to the reflection of light from the tungsten silicide layer or the molybdenum silicide layer can be prevented, and the peeling phenomenon in which the tungsten silicide layer is abnormally oxidized by the plasma TEOS oxide film can be prevented.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1A and 1B are main structural views of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view, and FIG. FIG. 2C is a cross-sectional view taken along line X-Y, and FIG. 2C is a cross-sectional view taken along line YY in FIG. This configuration diagram shows a MOSFET using a tungsten polycide structure.

In FIG. 3A, this plan view shows a tungsten silicide film 9, a LOCOS oxide film 2, n-type low-concentration and n-type high-concentration source regions 3, 5 and n-type low-concentration and n-type high-concentration drains. Regions 4 and 6 are shown, and the interlayer insulating film 14, PS shown in FIGS.
The iON film 10, the source electrode wiring 15, and the drain electrode wiring 16 are not shown. The n-type low-concentration and high-concentration source regions 3 and 5 and the n-type low-concentration and n-type high-concentration drain regions 4 and 6 are surrounded by a LOCOS oxide film 2. FIG. 13 is a plan view corresponding to FIG.

In FIG. 2B, this cross-sectional view is
FIG. 14 is a cross-sectional view of a main part of the FET, which is a cross-sectional view corresponding to FIG.

LOCOS is selectively applied to the surface layer of the semiconductor substrate.
An oxide film 2 is formed, and p is sandwiched between the LOCOS oxide films 2.
In the surface layer of the well region 1, n-type low-concentration and high-concentration source regions 3 and 5 and n-type low-concentration and high-concentration drain regions 4,
6 is formed, and a gate electrode wiring 30 is formed via a gate oxide film 7 on p well region 1 sandwiched between n-type low-concentration source region 3 and n-type low-concentration drain region 4. 30 is covered with a P-SiON film 10. The gate electrode wiring 30 is a tungsten polycide film composed of a polycrystalline silicon film 8 and a tungsten silicide film 9 thereon. The polycrystalline silicon film 8 is MOSF
The threshold voltage of ET is determined, and the tungsten silicide film 9 functions to reduce the gate resistance. Also, P-
The SiON film 10 is a film necessary in a manufacturing process for forming the gate electrode wiring 30 according to the mask pattern. These surfaces are covered with an interlayer insulating film 14.
Further, contact holes 18 and 19 are opened in the interlayer insulating film 14 and the second screen oxide film 13 on the n-type high-concentration source region 5 and the n-type high-concentration drain region 6, and the source electrode wiring 15 and the drain electrode wiring 16 are formed. Form. P-SiO on the tungsten silicide film 9 at a location not shown
A contact hole is also opened in the N film 10 and the interlayer insulating film 14, and a gate metal wiring
To form

The P-SiON on the gate electrode wiring 30
The film 10 is necessary for forming the gate electrode wiring 30 with high dimensional accuracy.

In FIG. 3C, this cross-sectional view is a cross-sectional view of a main part of a gate electrode wiring portion. It should be noted that FIG.
It is sectional drawing corresponding to (c).

A gate oxide film 7 on the silicon surface and a polycrystalline silicon film 8, a tungsten silicide film 9, a P-SiO 2 film on the gate oxide film 7 and on the LOCOS oxide film 2.
The N film 10 and the interlayer insulating film 14 are formed by lamination.

FIGS. 2 to 13 are cross-sectional views of a main part of a semiconductor device according to a second embodiment of the present invention. In the following figures, (a) is A in FIG.
FIG. 1B is a cross-sectional view corresponding to a cross section cut along line A, and FIG. 1B is a cross-sectional view corresponding to a cross section cut along line BB in FIG.

A gate oxide film 7 is formed on a silicon substrate having a LOCOS oxide film 2 and a p-well region 1 formed on a surface layer.
A tungsten silicide film 9 is further formed thereon by, for example, a sputtering method or a CVD method having a better step coverage, for example, 50 nm to 200 nm (FIG. 2).

Next, the refractive index n
= 2.4-2.7, and P-SiON10 (oxynitride film) having an extinction coefficient k = 0.35-0.45 is 20 nm-40.
nm, followed by a TEOS oxide film 2 by a plasma CVD method.
1 is formed in a thickness of 100 to 200 nm (FIG. 3).

The P-SiON film 10 contains a trace amount of nitrogen in the oxide film and controls the proportion thereof to change the film quality, that is, the refractive index n and the extinction coefficient k, which are typical optical constants. By selecting the optimized refractive index n, extinction coefficient k, and film thickness, P-SiON
The reflectance can be reduced for various combinations of the upper and lower layers of the film 10.

Here, the P-SiON film 10 was formed at a film formation temperature of about 350 ° C. by adjusting the flow rates of SiH ₄ , N ₂ O, and He gases. Also, the P-TEOS oxide film 2
No. 1 is a film forming temperature of about 480 ° C., and Si (OC
₂ H ₅ ) ₄ , O ₂ , and He were formed by adjusting the flow rate of each gas.

As a result, the absolute reflectance in the ultraviolet ray i-line (wavelength = 365 nm) region used for photolithography reaches approximately 52% in the case of a single layer of the tungsten silicide film 9, whereas This PS
In the structure in which the iON film 10 and the P-TEOS film 21 are stacked, the reduction can be reduced to 4 to 10%.

Next, a pattern of the photoresist 22 in a region to be the gate electrode wiring 30 is formed by photolithography (FIG. 4). As described above, by reducing the absolute reflectance to 4 to 10%, the reflection of light from the tungsten silicide film 9 running on the step C of the LOCOS oxide film 2 is reduced, and the gate electrode wiring 30 (FIG. (B)
P-SiON film 10 serving as a mask for forming
-Photoresist 2 for patterning TEOS film 21
The pattern shape of No. 2 becomes a vertical shape. As a result, the disturbance of the side surface of the photoresist due to the halation phenomenon as in the related art is suppressed.

Thereafter, by anisotropic dry etching,
Using the patterned photoresist 22 as a mask,
The P-TEOS oxide film 21 and subsequently the P-SiON film 10 are continuously etched (FIG. 5). In this case, P-Si
Since the ON film 10 contains a small amount of nitrogen, PT
Although the etching rate is lower by about 20 to 30% than that of the EOS oxide film 21, the P-SiON film 10 has an etching rate of 20 to 4%.
Since it is sufficiently thin, that is, 0 nm, it is etched according to the dimensions of the pattern of the photoresist 22.

Next, the photoresist 22 is removed, and P
The tungsten silicide film 9 and the polycrystalline silicon film 8 are dry-etched using the stacked cap film composed of the TEOS oxide film 21 and the P-SiON film 10 as a mask.

Normally, when the tungsten silicide film 9 and the polycrystalline silicon film 8 are etched, the remaining gate oxide film 7a of 5 nm or more is left to prevent damage to the silicon substrate. Thereafter, the first screen oxide film 12 is formed so that the silicon substrate is not damaged by ion implantation for forming the source region and the drain region (FIGS. 6A and 6B). Here, it is assumed that reference numeral 12 includes the remaining film 7a of the gate oxide film. Here, 5n
An apparatus having a high selectivity capable of stopping the etching of the gate oxide film 7 halfway so as to leave the remaining film 7a of the gate oxide film of m or more is used.

By using a device having a high selectivity, the P-TEOS oxide film 21 serving as a mask is almost completely eliminated when the tungsten polycide film composed of the tungsten silicide film 9 and the polycrystalline silicon film 8 is etched. And its disappearance is about 20 to 30 nm. Further, in the present invention, since the tungsten polycide structure is etched using a laminated cap film having a maximum thickness of about 0.24 μm, it is compared with the case where a photoresist having a height of 1 to 2 μm is used as a mask. As a result, the aspect ratio can be suppressed. Therefore, dimensional control by etching is further improved.

In forming the first screen oxide film, the P-SiON film 10 and the P-SiON film
Since the laminated cap film made of the TEOS oxide film 21 is covered, the tungsten silicide film 9 is not exposed to an oxidizing atmosphere, so that the LOCOS
The tungsten silicide film 9 formed on the step C of the oxide film 2 does not separate from the polycrystalline silicon film 8 (FIG. 6B).

Next, a MOSFET having an LDD structure
Is formed using the gate electrode wiring 30 made of the polycrystalline silicon film 8 and the tungsten silicide 9 as a mask at a lower concentration than the second ion implantation performed in a subsequent step. Low concentration source region 3 and n
A low-concentration drain region 4 is formed (FIG. 7).

Next, the oxide film 23 is formed by a low pressure CVD method.
Is formed on the entire surface (FIG. 8). The oxide film 23 thermally decomposes HTO or TEOS formed of monosilane (SiH ₄ ) and nitrous oxide (N ₂ O) at a relatively high temperature of 700 to 850 ° C., for example, at 600 to 800 ° C. Although a TEOS oxide film can be used, and the source gas is different, it is generally performed by a low-pressure CVD method of a thermal decomposition method because of good step coverage. At this time, oxygen in the atmosphere may be entrained in the furnace in the apparatus. In this case, since oxygen is also protected by the stacked cap film including the P-TEOS oxide film 21 and the P-SiON film 10, tungsten The surface of the silicide film 9 is not oxidized.

Next, oxide film spacers 11 are formed on the side walls of the gate electrode wiring 30 by performing anisotropic etching until the silicon surface is exposed. Thereafter, a second screen oxide film 13 is formed (FIG. 9A,
(B)). At this time, if there is a slight etching residue of the oxide film 23 in a partial region of the silicon surface, over-etching is usually performed in order to cause fluctuations in the characteristics of the MOSFET due to uneven implantation during subsequent ion implantation.
Ensure that the silicon surface is completely exposed. On the other hand, since the above-described P-TEOS oxide film 21 having a thickness of about 70 to 80 nm and the P-SiON film 10 having a low etching rate are present on the tungsten silicide film 9 when forming the oxide film spacer 11, Anisotropic etching and over-etching are performed on the tungsten silicide film 9 and the P-TEOS oxide film 21 and the P-SiO
Only the upper layer of the N film 10 is etched, and the lower layer P-S
The iON film 10 remains.

When the second screen oxide film 13 is formed, the P-SiO 2 film is formed on the tungsten silicide film 9 in the same manner as when the first screen oxide film 12 is formed.
Since the tungsten silicide film 9 is covered with the N film 10, the tungsten silicide film 9 is not exposed to an oxidizing atmosphere, so that the tungsten silicide film 9 formed on the step portion C of the LOCOS oxide film 2 is It does not peel off from the film 8 (FIG. 9B).

Next, the second ion implantation is performed at a higher concentration than the first ion implantation using the gate electrode wiring 30 and the oxide film spacer 11 as a mask, and the n-type high-concentration source region 5 and the n-type high A concentration drain region 6 is formed (FIG. 10).

Finally, the interlayer insulating film 14 is formed by low pressure CVD.
Or normal pressure CVD (FIG. 11).
The contact holes 19 and 20 are formed in the interlayer insulating film 14 and the second screen oxide film 13 on the n-type high-concentration source region 5 and the n-type high-concentration drain region 6, and the source electrode wiring 1 is formed.
5 and the drain electrode wiring 16 are formed. P-SiON film 1 on tungsten silicide film 9 at a location not shown
A contact hole is also formed in the interlayer insulating film 14 and the gate insulating film 14 to form a gate metal wiring (FIGS. 12A and 12B).

In the above description, the gate electrode wiring 30 has a tungsten polycide structure composed of a tungsten silicide film 9 and a polycrystalline silicon film 8, but it is composed of a molybdenum silicide film and a polycrystalline silicon film. A molybdenum polysite structure exhibits the same effect.

[0054]

According to the present invention, on a tungsten silicide film or a molybdenum silicide film, a P-SiON film for suppressing the reflectance and a P-TEOS oxide film for preventing exposure to an oxidizing atmosphere are formed. By forming the laminated cap film, the halation phenomenon at the time of processing the gate electrode wiring can be prevented, and the peeling phenomenon in which the tungsten silicide film or the molybdenum silicide film peels from the polycrystalline silicon film can be prevented.

As a result, a highly reliable miniaturized semiconductor device can be obtained at low cost.

[Brief description of the drawings]

FIGS. 1A and 1B are main part configuration diagrams of a semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a plan view, FIG. 1B is a cross-sectional view taken along line XX of FIG. Sectional drawing cut by the YY line of (a).

FIG. 2 is a sectional view of a main part manufacturing process of a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 2;

FIG. 4 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 3;

FIG. 5 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 4;

FIG. 6 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 5;

FIG. 7 is a cross-sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 6;

FIG. 8 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 7;

FIG. 9 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 8;

FIG. 10 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 9;

FIG. 11 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 10;

FIG. 12 is a sectional view of a main part manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 11;

13A and 13B are main part configuration diagrams of a MOSFET using a conventional tungsten polycide structure, where FIG. 13A is a plan view and FIG.
FIG. 3A is a cross-sectional view taken along the line AA in FIG.
Sectional view cut along the line BB

FIG. 14 is a cross-sectional view of a main part manufacturing process of a MOSFET using a conventional tungsten polycide structure.

FIG. 15 is a cross-sectional view of a main part manufacturing step, following FIG. 14;

FIG. 16 is a cross-sectional view of a main part manufacturing step, following FIG. 15;

FIG. 17 is a sectional view of a main part manufacturing process, following FIG. 16;

FIG. 18 is a cross-sectional view of a main part manufacturing step, following FIG. 17;

FIG. 19 is a sectional view of the main part manufacturing process, following FIG. 18;

FIG. 20 is a sectional view of the main part manufacturing process, following FIG. 19;

FIG. 21 is a sectional view of the main part manufacturing process, following FIG. 20;

FIG. 22 is a sectional view of the main part manufacturing process, following FIG. 21;

FIG. 23 is a sectional view of the main part manufacturing process, following FIG. 22;

24A and 24B are cross-sectional views of a conventional main part manufacturing process in the case of miniaturization, where FIG. 24A is a cross-sectional view corresponding to FIG. 15, and FIG.
FIG. 18 is a cross-sectional view corresponding to the cross-sectional view of the main part manufacturing process in FIG. 17.
(C) is a cross-sectional view corresponding to the cross-sectional view of the main part manufacturing process in FIG. 18.

FIG. 25 is a cross-sectional view taken along the line BB of FIG. 13A in the manufacturing process of FIG. 20;
Sectional view corresponding to the section cut along the line

[Explanation of symbols]

 Reference Signs List 1 p-well region 2 LOCOS oxide film 3 n-type low concentration source region 4 n-type low concentration drain region 5 n-type high concentration source region 6 n-type high concentration drain region 7 gate oxide film 7a remaining film of gate oxide film 8 polycrystal Silicon film 9 Tungsten silicide film 10 P-SiON film 11 Spacer oxide film 12 First screen oxide film 13 Second screen oxide film 14 Interlayer insulating film 15 Source electrode 16 Drain electrode 17, 18 Contact hole 21 P-TEOS oxide film 22 Photo Resist 23 oxide film 30 gate electrode wiring

Claims (6)

[Claims] 1. A semiconductor device having an insulated gate structure, wherein a gate electrode wiring comprises a polycide film and an oxynitride film formed on the polycide film. 2. The semiconductor device according to claim 1, wherein said polycide film comprises a polycrystalline silicon film and a tungsten silicide film or a molybdenum silicide film formed on said polycrystalline silicon film. 3. A plasma oxynitride film (P-film).
2. The semiconductor device according to claim 1, wherein the semiconductor device is SiON. 4. A semiconductor device having a stepped portion formed on a semiconductor substrate.
A method for manufacturing a semiconductor device having an insulated gate structure, a step of forming a polycrystalline silicon film covering the step portion; a step of forming a tungsten silicide film or a molybdenum silicide film on the polycrystalline silicon film; Forming an oxynitride film on the silicide film or the molybdenum silicide film; and forming a tetraethylorthosilicate oxide film (TEOS) on the oxynitride film.
Forming a resist film on the TEOS oxide film, exposing and developing the resist film to form a resist mask, and forming the resist mask using the TEOS oxide film. Selectively removing the oxynitride film by etching, removing the resist mask, and using the TEOS oxide film and the oxynitride film as a mask, removing the polycrystalline silicon film and the tungsten silicide film or the molybdenum silicide film. A method of manufacturing a semiconductor device, comprising: removing by anisotropic etching; and thereafter, removing, by etching, a TEOS oxide film serving as the mask and an upper layer of the oxynitride film. 5. The method according to claim 1, wherein the thickness of the oxynitride film formed on the tungsten silicide film or the molybdenum silicide film is not less than 20 nm and not more than 40 nm, and the thickness of the TEOS oxide film formed on the oxynitride film is The thickness is 10
5. The method according to claim 4, wherein the thickness is not less than 0 nm and not more than 200 nm. 6. The semiconductor device according to claim 4, wherein said oxynitride film and said TEOS oxide film are a plasma oxynitride film and a plasma TEOS oxide film, respectively, formed by a plasma CVD method. Manufacturing method.