JP2001111043A - Manufacturing method of mos fet - Google Patents
Manufacturing method of mos fetInfo
- Publication number
- JP2001111043A JP2001111043A JP28570699A JP28570699A JP2001111043A JP 2001111043 A JP2001111043 A JP 2001111043A JP 28570699 A JP28570699 A JP 28570699A JP 28570699 A JP28570699 A JP 28570699A JP 2001111043 A JP2001111043 A JP 2001111043A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- drift channel
- manufacturing
- channel layer
- valley
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 238000005468 ion implantation Methods 0.000 description 17
- 239000004065 semiconductor Substances 0.000 description 9
- 239000000758 substrate Substances 0.000 description 9
- 230000005684 electric field Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005094 computer simulation Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＭＯＳＦＥＴの製
造方法に関し、特に横型２重拡散ＭＯＳＦＥＴ（以下、
横型ＤＭＯＳＦＥＴと記す）の製造方法に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOSFET, and more particularly to a lateral double diffusion MOSFET (hereinafter, referred to as a lateral double diffusion MOSFET).
Horizontal DMOSFET).
【０００２】[0002]
【従来の技術】近年の携帯電子機器の普及、ＯＡ機器の
低消費電力化のため、より一層のスイッチング電源の小
型化、軽量化、低消費電力化、高信頼性が求められてい
る。このため、出力３０Ｗ程度のスイッチング電源で
は、パワーＭＯＳＦＥＴとＰＷＭ制御・保護補償機能を
集積したインテリジェントパワーＩＣを搭載した電源装
置がある。2. Description of the Related Art In recent years, in order to spread portable electronic devices and reduce power consumption of OA devices, further reduction in size, weight, power consumption, and reliability of switching power supplies have been required. For this reason, as a switching power supply having an output of about 30 W, there is a power supply device equipped with an intelligent power IC in which a power MOSFET and a PWM control / protection compensation function are integrated.
【０００３】一般的にインテリジェントパワーＩＣは、
スイッチングを行うパワーＭＯＳＦＥＴとこれを制御す
る制御回路は同一シリコン基板内に作り込まれ、パワー
ＭＯＳＦＥＴ自身はシリコン基板電位が接地される横型
ＤＭＯＳＦＥＴが採用される。[0003] Generally, intelligent power ICs
A power MOSFET for switching and a control circuit for controlling the power MOSFET are formed in the same silicon substrate, and the power MOSFET itself employs a horizontal DMOSFET whose silicon substrate potential is grounded.
【０００４】そして、スイッチング電源に使用されるイ
ンテリジェントパワーＩＣにおいては、横型ＤＭＯＳＦ
ＥＴのオン抵抗を低くする必要があるため、ゲートの幅
を長くしてドレイン電流の経路を確保するように、横型
ＤＭＯＳＦＥＴを櫛形に接続した構造とする場合があ
る。[0004] In an intelligent power IC used for a switching power supply, a horizontal DMMOS is used.
Since it is necessary to reduce the on-resistance of the ET, a structure in which a lateral DMOSFET is connected in a comb shape may be used to increase the gate width and secure a drain current path.
【０００５】以下に、図面を用いて従来の横型ＤＭＯＳ
ＦＥＴの製造方法を説明する。図５は、従来の横型ＤＭ
ＯＳＦＥＴの構成を示す平面図であり、図６（ａ），図
６（ｂ），図６（ｃ）は、それぞれ図５のＡ−Ａ‘断面
図、Ｂ−Ｂ’断面図、Ｃ−Ｃ‘断面図である。Hereinafter, a conventional lateral DMOS will be described with reference to the drawings.
A method for manufacturing an FET will be described. FIG. 5 shows a conventional horizontal DM.
6A, 6B, and 6C are cross-sectional views taken along the line AA ', the line BB', and the line CC of FIG. 5, respectively. FIG.
【０００６】図５において、横型ＤＭＯＳＦＥＴは、ド
レイン電極１、ドリフトチャネル層２、ゲート電極３、
ソース電極４が、それぞれが互いの周囲を囲むように中
心より順に櫛状に形成されている。In FIG. 5, a lateral DMOSFET includes a drain electrode 1, a drift channel layer 2, a gate electrode 3,
The source electrodes 4 are formed in a comb shape in order from the center so as to surround each other.
【０００７】そして、櫛状の横型ＤＭＯＳＦＥＴは、平
面上に曲率を有する半円状の先端部５と中心部が欠落し
た半円状の谷部６、そして先端部５と谷部６との間に直
線部７を形成している。The comb-shaped lateral DMOSFET has a semicircular tip 5 having a curvature on a plane, a semicircular valley 6 with a missing central portion, and a gap between the tip 5 and the valley 6. The linear part 7 is formed.
【０００８】図５、図６（ａ）〜（ｃ）において、ま
ず、低濃度のＰ型（以下Ｐ-と記す）半導体基板８に、
低濃度のＮ型（以下Ｎ-と記す）のドリフトチャネル層
２をイオン注入することによって櫛状に形成し、次にＰ
型の半導体層であるＰベース２０をイオン注入によって
ドリフトチャネル層２を取り囲むように離間して櫛状に
形成する。In FIGS. 5 and 6A to 6 C, first, a low-concentration P-type (hereinafter referred to as P − ) semiconductor substrate 8 is
A low-concentration N-type (hereinafter referred to as N − ) drift channel layer 2 is formed in a comb shape by ion implantation,
A P-type base 20, which is a semiconductor layer of a mold, is formed in a comb shape by ion implantation so as to be spaced around the drift channel layer 2.
【０００９】次に、Ｐ-のＰドリフト層２１を、谷部の
ドリフトチャネル層２とＰベース２０の間に、中心部が
欠落した半円状にイオン注入することによって形成す
る。Next, a P − P drift layer 21 is formed between the drift channel layer 2 at the valley portion and the P base 20 by ion implantation in a semicircular shape with a central portion missing.
【００１０】次に、選択酸化により厚い酸化膜であるＬ
ＯＣＯＳ２２を、先端部５と直線部７においてはドリフ
トチャネル層２の上部に、谷部６においてはドリフトチ
ャネル層２とＰベース２０の間に櫛状に形成し、ゲート
酸化膜３０とゲート電極３をＰベース２０上に順次形成
する。Next, L which is a thick oxide film by selective oxidation is formed.
The OCOS 22 is formed in a comb shape between the drift channel layer 2 and the P base 20 in the valley 6 at the tip portion 5 and the straight portion 7, and in the valley 6, the gate oxide film 30 and the gate electrode 3 are formed. Are sequentially formed on the P base 20.
【００１１】そして、Ｎ+のソース層４０と、このソー
ス層４０を半導体基板８にショートさせるＰ+半導体層
４１とを、Ｐベース２０の表面にイオン注入によって谷
部６で曲率を持つように櫛状に形成し（２重拡散）、Ｎ
+のドレイン層１０をドリフトチャネル層２の表面にイ
オン注入によって先端部で曲率を持つように櫛状に形成
する。Then, the N + source layer 40 and the P + semiconductor layer 41 for short-circuiting the source layer 40 to the semiconductor substrate 8 are ion-implanted into the surface of the P base 20 so as to have a curvature at the valley 6. Formed in a comb shape (double diffusion), N
The + drain layer 10 is formed in a comb shape by ion implantation into the surface of the drift channel layer 2 so as to have a curvature at the tip.
【００１２】そして、ソース電極４をソース層４０の上
に、ドレイン電極１をドレイン層１０の上に、例えばス
パッタリングしたアルミなどをフォトエッチングするこ
とにより形成する。Then, the source electrode 4 is formed on the source layer 40 and the drain electrode 1 is formed on the drain layer 10 by, for example, photo-etching of sputtered aluminum or the like.
【００１３】[0013]
【発明が解決しようとする課題】しかし、このような櫛
型の横型ＤＭＯＳＦＥＴの製造方法においては次のよう
な問題点があった。However, the method of manufacturing such a comb-shaped lateral DMOSFET has the following problems.
【００１４】先端部５ではドレイン層１０の曲率の影響
でドリフトチャネル層２の濃度が低い場合はドレイン層
１０の近傍で電界集中を起こしやすい。従って、先端部
５のドリフトチャネル長Ｌｄを、直線部７のドリフトチ
ャネル長Ｌよりも長くして、このドレイン層１０の近傍
の電界集中を回避し、ソースとドレイン間の耐圧（以
下、耐圧と記す）を確保している。At the tip 5, when the concentration of the drift channel layer 2 is low due to the influence of the curvature of the drain layer 10, electric field concentration is likely to occur near the drain layer 10. Therefore, the drift channel length Ld of the tip portion 5 is made longer than the drift channel length L of the linear portion 7 to avoid the electric field concentration near the drain layer 10 and to withstand the voltage between the source and the drain (hereinafter referred to as the withstand voltage). Note) is secured.
【００１５】しかし、先端部５のドリフトチャネル長Ｌ
ｄを直線部７のドリフトチャネル長Ｌよりも長くするこ
とは、チップ面積を増大させ、結果としてコストを高め
てしまうという問題点があった。However, the drift channel length L of the tip 5
Making d longer than the drift channel length L of the linear portion 7 increases the chip area, and consequently raises the cost.
【００１６】また、谷部６では、ドリフトチャネル層２
を先端部５と同様に配置し、オン抵抗を下げるためにそ
の濃度を高くすると、ソース層４０の曲率の影響によ
り、ソース層４０の近傍で電界集中を起こしやすく、耐
圧が低下する。この影響を除去することを目的に、Ｐド
リフト層２１を設けて、ソース層４０近傍の電界集中を
緩和している。In the valley 6, the drift channel layer 2
Are arranged in the same manner as the tip portion 5, and when the concentration is increased in order to reduce the on-resistance, electric field concentration is likely to occur near the source layer 40 due to the influence of the curvature of the source layer 40, and the breakdown voltage is reduced. For the purpose of removing this effect, the P drift layer 21 is provided to reduce the electric field concentration near the source layer 40.
【００１７】しかし、Ｐドリフト層２１は、他の領域と
同時に形成することができず、単独の製造工程を追加し
て形成されるため、結果としてコストが高くなるという
問題点があった。However, the P drift layer 21 cannot be formed at the same time as the other regions, and is formed by adding a single manufacturing process. As a result, there is a problem that the cost is increased.
【００１８】さらに、図７を用いて従来の横型ＤＭＯＳ
ＦＥＴの問題点を説明する。図７は、ドリフトチャネル
層２へのイオン注入量と先端部５、谷部６、直線部７そ
れぞれの場所における耐圧の関係をコンピューターシミ
ュレーションした結果を示す特性曲線図である。Further, referring to FIG. 7, a conventional horizontal DMOS
The problem of the FET will be described. FIG. 7 is a characteristic curve diagram showing the result of computer simulation of the relationship between the amount of ions implanted into the drift channel layer 2 and the breakdown voltage at each of the tip 5, valley 6, and linear portion 7.
【００１９】シミュレーション条件は、半導体基板８の
不純物濃度は５×１０13[ｃｍ-3]で、Ｐベース２０の表
面濃度は約１×１０17[ｃｍ-3]で、その接合深さは５ｕ
ｍである。また、谷部６のソース層４０の曲率は２０、
先端部５のドレイン層１０の曲率は１５である。The simulation conditions are as follows: the impurity concentration of the semiconductor substrate 8 is 5 × 10 13 [cm −3 ], the surface concentration of the P base 20 is about 1 × 10 17 [cm −3 ], and the junction depth is 5 u.
m. The curvature of the source layer 40 in the valley 6 is 20,
The curvature of the drain layer 10 at the tip 5 is 15.
【００２０】図７において、先端部５ではイオン注入量
が２．１×１０12[ｃｍ-3]、谷部６では２．３５×１０
12[ｃｍ-3]、直線部７では１．２×１０12[ｃｍ-3]、の
ポイントでそれぞれの場所における耐圧の最大値が存在
することが分かる。In FIG. 7, the amount of ion implantation is 2.1 × 10 12 [cm −3 ] at the tip 5 and 2.35 × 10 2 at the valley 6.
12 [cm -3], the linear portion 7 at 1.2 × 10 12 [cm -3] , it can be seen that at the point of presence is the maximum value of the withstand voltage at each location.
【００２１】従って、ドリフトチャネル層２へのイオン
注入を先端部５、谷部６、直線部７、の３回に分けて行
い、それぞれの不純物濃度を個別に設定すれば、素子全
体の耐圧をより高くすることができ、上述のようなチッ
プ面積の増大を防ぐことができる。Therefore, if the ion implantation into the drift channel layer 2 is performed in three steps of the tip part 5, the valley part 6, and the linear part 7, and the respective impurity concentrations are individually set, the breakdown voltage of the entire device can be reduced. The height can be increased, and the increase in the chip area as described above can be prevented.
【００２２】しかし、ドリフトチャネル層２へのイオン
注入を複数回に分けて行った場合は、その製造工程が増
えてしまう。従って、従来はドリフトチャネル層２の先
端部５、谷部６、直線部７を全て同一の不純物濃度とな
るように１回のイオン注入で形成していた。However, if the ion implantation into the drift channel layer 2 is performed in a plurality of times, the number of manufacturing steps increases. Therefore, conventionally, the tip portion 5, the valley portion 6, and the straight portion 7 of the drift channel layer 2 are formed by one ion implantation so as to have the same impurity concentration.
【００２３】その結果、素子の耐圧は、設定されたイオ
ン注入量に対する先端部５、谷部６、直線部７の最低耐
圧で決定され、耐圧を設計する自由度が小さくなるとい
う問題点があった。As a result, the breakdown voltage of the element is determined by the minimum breakdown voltage of the tip 5, the valley 6, and the linear portion 7 with respect to the set ion implantation amount, and there is a problem that the degree of freedom in designing the breakdown voltage is reduced. Was.
【００２４】例えば、図７において、イオン注入量を
１．２×１０12[ｃｍ-3]とした場合の耐圧は、先端部５
では約７２０Ｖ、谷部６では約７８０Ｖ、直線部では約
７００Ｖとなり、そのそし最低耐圧である約７００Ｖ
が、その素子の耐圧となる。For example, in FIG. 7, when the ion implantation amount is 1.2 × 10 12 [cm −3 ], the breakdown voltage is
About 720V, about 780V at the valley 6 and about 700V at the straight section, and the minimum withstand voltage of about 700V
Is the breakdown voltage of the element.
【００２５】本発明は上述した問題点を解決するために
なされたものであり、同一工程において、ドリフトチャ
ネル層の先端部５、谷部６、直線部７の不純物濃度を個
別に設定するプロセスを実現することにより、チップ面
積を増大させず、またその製造工程を増加させずに耐圧
設計の自由度を増した櫛型の横型ＤＭＯＳＦＥＴの製造
方法を提供することを目的とする。The present invention has been made in order to solve the above-described problems. In the same step, a process for individually setting the impurity concentrations of the tip portion 5, the valley portion 6, and the linear portion 7 of the drift channel layer is described. An object of the present invention is to provide a method of manufacturing a comb-type lateral DMOSFET in which the degree of freedom in withstand voltage design is increased without increasing the chip area and without increasing the number of manufacturing steps.
【００２６】[0026]
【課題を解決するための手段】本発明の請求項１におい
ては、ドレイン層、ドリフトチャネル層、ゲート電極、
ソース層が直線部と曲率を有する先端部及び谷部とを有
する櫛状をなし、互いの周囲を囲むように中心より順に
前記ドレイン層、前記ドリフトチャネル層、前記ゲート
電極、前記ソース層を形成するＭＯＳＦＥＴの製造方法
において、前記ドリフトチャネル層を、前記直線部と前
記先端部と前記谷部の不純物濃度が個別に設定可能な同
一工程で形成することを特徴とするＭＯＳＦＥＴの製造
方法である。According to the first aspect of the present invention, a drain layer, a drift channel layer, a gate electrode,
The source layer has a comb shape having a linear portion and a tip portion and a valley portion having a curvature, and the drain layer, the drift channel layer, the gate electrode, and the source layer are formed in order from the center so as to surround each other. The drift channel layer is formed in the same step in which the impurity concentration of the linear portion, the tip portion, and the valley portion can be individually set.
【００２７】本発明の請求項２においては、前記同一工
程は、部分的に半透明なフォトマスクを使用したフォト
工程を含むことを特徴とする請求項１記載のＭＯＳＦＥ
Ｔの製造方法である。According to a second aspect of the present invention, the same step includes a photostep using a partially translucent photomask.
This is a manufacturing method of T.
【００２８】本発明の請求項３においては、前記フォト
マスクは、部分的に遮光性部材をモザイク上に配置して
なることを特徴とする請求項２記載のＭＯＳＦＥＴの製
造方法である。According to a third aspect of the present invention, there is provided the method for manufacturing a MOSFET according to the second aspect, wherein the photomask has a light-shielding member partially arranged on a mosaic.
【００２９】本発明の請求項４においては、前記同一工
程は、前記ドリフトチャネル層の前記直線部を形成する
直線形成部が半透明であるフォトマスクを使用したフォ
ト工程を含むことを特徴とする請求項１記載のＭＯＳＦ
ＥＴの製造方法である。According to a fourth aspect of the present invention, the same step includes a photo step using a photomask in which a straight line forming portion forming the straight line portion of the drift channel layer is translucent. MOSF according to claim 1
It is a manufacturing method of ET.
【００３０】本発明の請求項５においては、前記フォト
マスクは、前記ドリフトチャネル層の前記直線部を形成
する直線形成部に遮光性部材をモザイク状に配置してな
ることを特徴とする請求項４記載のＭＯＳＦＥＴの製造
方法である。According to a fifth aspect of the present invention, in the photomask, a light-shielding member is arranged in a mosaic shape in a straight line forming portion of the drift channel layer that forms the straight line portion. 5. A method for manufacturing a MOSFET according to item 4.
【００３１】[0031]
【発明の実施の形態】次に、本発明の実施例について図
面を用いて説明する。尚、以下の図面において、図５〜
図７と重複する部分は同一番号を付してその説明は適宜
に省略する。図１は、本発明の一実施例の構成を示すド
リフトチャネル層形成用のフォトマスクの平面図であ
る。図２は、本発明により製造された横型ＤＭＯＳＦＥ
Ｔの平面図である。図３は、図２に示した横型ＤＭＯＳ
ＦＥＴのｂ−ｂ‘断面図である。Next, embodiments of the present invention will be described with reference to the drawings. In the following drawings, FIGS.
The same parts as those in FIG. 7 are denoted by the same reference numerals, and the description thereof will be appropriately omitted. FIG. 1 is a plan view of a photomask for forming a drift channel layer showing the configuration of one embodiment of the present invention. FIG. 2 shows a lateral DMOSFE manufactured according to the present invention.
It is a top view of T. FIG. 3 shows the horizontal DMOS shown in FIG.
It is bb 'sectional drawing of FET.
【００３２】図１において、ドリフトチャネル層２の先
端部５を形成するフォトマスクの先端形成部５０は、中
心部が欠落した半円状に白抜きとなっており、ドリフト
チャネル層２の直線部７を形成する直線形成部７０は、
四角形の遮光性部材１２がモザイク状に配置されてお
り、半透明になっている。尚、遮光性部材１２の形状は
四角形に限定されるものではなく、任意の形状とするこ
とができる。そして、先端形成部５０の幅ｄ１と直線形
成部７０の幅ｄ２の長さは等しくなっている。In FIG. 1, the tip forming portion 50 of the photomask forming the tip 5 of the drift channel layer 2 is outlined in a semicircular shape with a center portion missing, and the straight portion of the drift channel layer 2 is formed. 7, the straight line forming part 70
The rectangular light-shielding members 12 are arranged in a mosaic shape and are translucent. The shape of the light-shielding member 12 is not limited to a quadrangle, but may be any shape. The width d1 of the tip forming portion 50 and the length d2 of the straight line forming portion 70 are equal.
【００３３】そして、ドリフトチャネル層２の谷部６を
形成するフォトマスクの谷形成部６０は、ドレイン形成
部１１と接する部分が、中心部が欠落して幅ｄ３を持っ
た半円状に白抜きとなっており、ドレイン形成部１１
と、先端形成部５０と、谷形成部６０と、直線形成部７
０とを取り囲む領域には遮光性部材１２が高密度に形成
されており、全面的に遮光性を持たせている。In the trough forming portion 60 of the photomask forming the trough 6 of the drift channel layer 2, the portion in contact with the drain forming portion 11 is formed in a semicircular white shape having a width d 3 with a center portion being omitted. The drain forming portion 11
, Tip forming section 50, valley forming section 60, and straight line forming section 7
The light-shielding member 12 is formed at a high density in a region surrounding 0 and has light-shielding properties over the entire surface.
【００３４】このようなフォトマスクを使用したフォト
工程により、半導体基板８上に先端部５が白抜きで、直
線部７が半透明で、谷部６はその一部が白抜きとなって
いるイオン注入用のマスク（図示しない）を作成する。
そして、このマスク越しに半導体基板８にイオン注入を
一回行うことにより、図２に示した横型ＤＭＯＳＦＥＴ
のドリフトチャネル層の先端部５、谷部６、直線部７を
同時に形成する。By the photo process using such a photomask, the tip 5 is hollow, the linear portion 7 is translucent, and the valley 6 is partially hollow on the semiconductor substrate 8. A mask (not shown) for ion implantation is formed.
Then, ion implantation into the semiconductor substrate 8 is performed once through the mask, thereby forming the lateral DMOSFET shown in FIG.
Of the drift channel layer, a valley 6 and a straight line 7 are simultaneously formed.
【００３５】このようなマスクを使用した場合、マスク
のｄ１とｄ２の長さが等しいので、先端部５のドリフト
チャネル長Ｌｄと直線部７のドリフトチャネル長Ｌは等
しくなる。When such a mask is used, since the lengths d1 and d2 of the mask are equal, the drift channel length Ld of the tip portion 5 and the drift channel length L of the linear portion 7 are equal.
【００３６】また、イオン注入量を例えば２．０×１０
12[ｃｍ-3]とした場合、先端部５と谷部６の一部には、
２．０×１０12[ｃｍ-3]のイオンが全て注入され、直線
部７においては、マスクが半透明であるので、注入量は
２．０×１０12[ｃｍ-3]よりも少なく、例えば約１．４
０×１０12[ｃｍ-3]の注入量となる。また、直線部７の
イオン注入量を、モザイクの密度を変化させることによ
り任意に調整することが可能である、The ion implantation amount is set to, for example, 2.0 × 10
In the case of 12 [cm -3 ], the tip 5 and a part of the valley 6
All ions of 2.0 × 10 12 [cm −3 ] are implanted, and the mask is translucent in the linear portion 7. Therefore, the implantation amount is smaller than 2.0 × 10 12 [cm −3 ]. For example, about 1.4
The injection amount is 0 × 10 12 [cm −3 ]. Further, the ion implantation amount of the linear portion 7 can be arbitrarily adjusted by changing the density of the mosaic.
【００３７】そして、谷部６においては、イオン注入用
のマスクの一部が白抜きとなって半導体基板８が露出す
るので、図３に示すように、ドリフトチャネル層２は、
ドレイン層１０からＰベース２０の方向にＤ３の長さ分
だけ張り出して形成される。Then, in the valley 6, a part of the mask for ion implantation becomes hollow and the semiconductor substrate 8 is exposed. Therefore, as shown in FIG.
It is formed to extend from the drain layer 10 toward the P base 20 by the length of D3.
【００３８】図４は、谷部でのドリフトチャネル長と耐
圧との関係を示す特性曲線図である。図４に示すように
図１のｄ３の長さを変えることにより、谷部におけるド
リフトチャネル長Ｄ３を調整し、谷部６における耐圧を
最適値に設定することができる。例えば、図４において
は、谷部６におけるドリフトチャネル長Ｄ３が２５ｕｍ
となるポイントで耐圧を最大にすることができる。FIG. 4 is a characteristic curve showing the relationship between the drift channel length at the valley and the breakdown voltage. By changing the length of d3 in FIG. 1 as shown in FIG. 4, the drift channel length D3 in the valley can be adjusted, and the breakdown voltage in the valley 6 can be set to an optimum value. For example, in FIG. 4, the drift channel length D3 in the valley 6 is 25 μm.
The pressure resistance can be maximized at the following points.
【００３９】上記の条件でイオン注入を行い、谷部６で
のドリフトチャネル長Ｄ３を２５ｕｍとした場合は、図
７に示したシミュレーション結果によれば、先端部５と
直線部７での耐圧は約８３０Ｖ、谷部６での耐圧は約９
００Ｖとなり、素子全体としては約８３０Ｖの耐圧を得
ることができると考えられる。When the ion implantation is performed under the above conditions and the drift channel length D3 at the valley 6 is set to 25 μm, according to the simulation result shown in FIG. About 830V, withstand voltage at valley 6 is about 9
00V, and it is considered that a withstand voltage of about 830 V can be obtained for the entire device.
【００４０】このように、ドリフトチャネル層の先端部
５、谷部６、直線部７の不純物濃度を個別に設定するよ
うにしたので、耐圧を設計する自由度が増し、先端部５
のドリフトチャネル長Lｄと直線部のドリフトチャネル
長Lを等しくすることができる。従って、結果としてチ
ップ面積の増大を防ぐことができる。As described above, since the impurity concentrations of the tip portion 5, the valley portion 6, and the straight portion 7 of the drift channel layer are individually set, the degree of freedom in designing the withstand voltage increases, and the tip portion 5
And the drift channel length L of the linear portion can be made equal. Therefore, as a result, an increase in chip area can be prevented.
【００４１】また、同一の工程でドリフトチャネル層２
の先端部５、谷部６、直線部７を形成することができる
ので、その製造工程が増えることはなく、結果としてコ
ストを下げることができる。The drift channel layer 2 is formed in the same process.
Since the front end portion 5, the valley portion 6, and the straight portion 7 can be formed, the number of manufacturing steps does not increase, and as a result, the cost can be reduced.
【００４２】また、谷部６においては、耐圧が最適とな
るようにドリフトチャネル長Ｄ３を調整したので、従来
のＰドリフト層２１を形成する必要がなくなり、その製
造工程を削減することができる。In the valley portion 6, the drift channel length D3 is adjusted so that the breakdown voltage is optimized. Therefore, it is not necessary to form the conventional P drift layer 21, and the number of manufacturing steps can be reduced.
【００４３】[0043]
【発明の効果】以上説明したように、本発明の請求項１
から請求項５によれば、同一工程において、ドリフトチ
ャネル層２の先端部５、谷部６、直線部７の不純物濃度
を個別に設定可能としているため、チップ面積を増大さ
せず、またその製造工程を増加させずに耐圧設計の自由
度を増した櫛型の横型ＤＭＯＳＦＥＴの製造方法を提供
することができる。As described above, according to the first aspect of the present invention,
According to the fifth aspect, in the same step, since the impurity concentrations of the tip portion 5, the valley portion 6, and the linear portion 7 of the drift channel layer 2 can be individually set, the chip area is not increased, and It is possible to provide a method of manufacturing a comb-type lateral DMOSFET in which the degree of freedom in withstand voltage design is increased without increasing the number of steps.
【００４４】[0044]
【図１】本発明の一実施例の構成を示すフォトマスクの
平面図である。FIG. 1 is a plan view of a photomask showing a configuration of one embodiment of the present invention.
【図２】本発明により製造された横型ＤＭＯＳＦＥＴの
平面図である。FIG. 2 is a plan view of a lateral DMOSFET manufactured according to the present invention.
【図３】図２に示した横型ＤＭＯＳＦＥＴのｂ−ｂ‘断
面図である。FIG. 3 is a cross-sectional view of the horizontal DMOSFET shown in FIG.
【図４】谷部でのドリフトチャネル長と耐圧の関係を示
す特性曲線図であるFIG. 4 is a characteristic curve diagram showing a relationship between a drift channel length and a breakdown voltage in a valley.
【図５】従来の横型ＤＭＯＳＦＥＴの構成を示す平面図
である。FIG. 5 is a plan view showing a configuration of a conventional lateral DMOSFET.
【図６】図５に示した横型ＤＭＯＳＦＥＴの断面図であ
る。6 is a cross-sectional view of the lateral DMOSFET shown in FIG.
【図７】イオン注入量と耐圧との関係を示す特性曲線図
である。FIG. 7 is a characteristic curve diagram showing a relationship between an ion implantation amount and a breakdown voltage.
１ ドレイン電極 ２ ドリフトチャネル層 ３ ゲート電極 ４ ソース電極 ５ 先端部 ６ 谷部 ７ 直線部 ８ 半導体基板 １０ ドレイン層 ２０ Ｐベース ３０ ゲート酸化膜 ４０ ソース層 １２ 遮光性部材 ５０ 先端形成部 ６０ 谷形成部 ７０ 直線形成部 DESCRIPTION OF SYMBOLS 1 Drain electrode 2 Drift channel layer 3 Gate electrode 4 Source electrode 5 Tip part 6 Valley part 7 Linear part 8 Semiconductor substrate 10 Drain layer 20 P base 30 Gate oxide film 40 Source layer 12 Light shielding member 50 Tip formation part 60 Valley formation part 70 Straight line forming part
Claims (5)
ト電極、ソース層が直線部と曲率を有する先端部及び谷
部とを有する櫛状をなし、互いの周囲を囲むように中心
より順に前記ドレイン層、前記ドリフトチャネル層、前
記ゲート電極、前記ソース層を形成するＭＯＳＦＥＴの
製造方法において、 前記ドリフトチャネル層を、前記直線部と前記先端部と
前記谷部の不純物濃度が個別に設定可能な同一工程で形
成することを特徴とするＭＯＳＦＥＴの製造方法。1. A drain layer, a drift channel layer, a gate electrode, and a source layer having a comb shape having a linear portion, a tip portion having a curvature, and a valley portion, and the drain layer is arranged in order from the center so as to surround each other. A method of manufacturing a MOSFET for forming the drift channel layer, the gate electrode, and the source layer, wherein the drift channel layer is configured such that impurity concentrations of the linear portion, the tip portion, and the valley portion can be individually set. A method for manufacturing a MOSFET, comprising:
トマスクを使用したフォト工程を含むことを特徴とする
請求項１記載のＭＯＳＦＥＴの製造方法。2. The method according to claim 1, wherein the same step includes a photo step using a partially translucent photo mask.
材をモザイク上に配置してなることを特徴とする請求項
２記載のＭＯＳＦＥＴの製造方法。3. The method for manufacturing a MOSFET according to claim 2, wherein the photomask is formed by partially arranging a light shielding member on a mosaic.
層の前記直線部を形成する直線形成部が半透明であるフ
ォトマスクを使用したフォト工程を含むことを特徴とす
る請求項１記載のＭＯＳＦＥＴの製造方法。4. The MOSFET according to claim 1, wherein the same step includes a photo step using a photomask in which a straight line forming portion forming the straight line portion of the drift channel layer is translucent. Production method.
ネル層の前記直線部を形成する直線形成部に遮光性部材
をモザイク状に配置してなることを特徴とする請求項４
記載のＭＯＳＦＥＴの製造方法。5. The photomask according to claim 4, wherein light-shielding members are arranged in a mosaic shape in a straight line forming part of the drift channel layer forming the straight line part.
A manufacturing method of the MOSFET described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28570699A JP2001111043A (en) | 1999-10-06 | 1999-10-06 | Manufacturing method of mos fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28570699A JP2001111043A (en) | 1999-10-06 | 1999-10-06 | Manufacturing method of mos fet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001111043A true JP2001111043A (en) | 2001-04-20 |
Family
ID=17694982
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28570699A Withdrawn JP2001111043A (en) | 1999-10-06 | 1999-10-06 | Manufacturing method of mos fet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001111043A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014170821A (en) * | 2013-03-04 | 2014-09-18 | Lapis Semiconductor Co Ltd | Method of manufacturing semiconductor device, and development support system |
| CN111710720A (en) * | 2020-07-10 | 2020-09-25 | 杰华特微电子（杭州）有限公司 | Lateral double-diffused transistor and manufacturing method thereof |
-
1999
- 1999-10-06 JP JP28570699A patent/JP2001111043A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014170821A (en) * | 2013-03-04 | 2014-09-18 | Lapis Semiconductor Co Ltd | Method of manufacturing semiconductor device, and development support system |
| CN111710720A (en) * | 2020-07-10 | 2020-09-25 | 杰华特微电子（杭州）有限公司 | Lateral double-diffused transistor and manufacturing method thereof |
| CN111710720B (en) * | 2020-07-10 | 2022-07-19 | 杰华特微电子股份有限公司 | Lateral double diffused transistor and method of fabricating the same |
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