JP2001111012A - Non-volatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile memory wherein a read-out margin is large, with a reliable read-out characteristics. SOLUTION: Transistors of MFMIS structure are arrayed in matrix where a floating gate 4, ferroelectrics layer 5, and control gate 6 are sequentially laminated, through a gate insulating film 3, on the surface of a semiconductor substrate 1 between a source and drain regions formed on the semiconductor substrate. Here, the control gate is connected to a ward line, the source region is connected to a source line, and the drain region is connected to a drain line, while a floating line comprising a write-in gate so configured as to form a capacitor with the floating gate provided. The word line and the source line of the matrix in the same row are common-connected while the drain line and the floating line of the matrix in the same column are common-connected, with a source/drain voltage and a gate voltage allowed to be set independently.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory, and more particularly, to a nonvolatile memory capable of increasing a read margin.

[0002]

2. Description of the Related Art A memory cell in which memory transistors having an MFMIS structure, which is an example of a semiconductor memory device capable of electrically rewriting data and retaining data without a power supply, is arranged in a matrix, For example, as shown in FIG. 5, a 1T / 2C memory cell structure including one selection transistor and two memory capacitors has been proposed. In this structure, one electrode of the memory capacitor is commonly connected and connected to the gate electrode of the select transistor, and the other electrode of the memory capacitor is connected to the source and drain of the select transistor. Therefore, the source-drain voltage V
There is a problem that can not be independently set the _SD and the gate voltage V _G.

In this semiconductor memory device, the sources of the memory cells in each row in the horizontal direction are connected to form a bit line BL.
, BL2,... And the drains of the memory cells arranged in each column in the vertical direction are connected to form word lines WL1, WL2,.

The structure of this memory cell is, as shown in the sectional view of FIG. 6, an MF having a metal layer (M) and an insulator layer (I) interposed as a buffer layer at a ferroelectric / semiconductor interface.
An MIS structure FET is proposed. In the FET having the MFMIS structure, a gate oxide film 3, a floating gate 4, a ferroelectric film 5, and a control gate 6 are sequentially stacked on a channel region formed between source / drain regions S and D of a semiconductor substrate 1. It is.

In this structure, the semiconductor substrate 1 is usually installed,
When a positive voltage is applied to the control gate 6 as shown in FIG. 7A, the ferroelectric film 5 causes polarization reversal. Even if the voltage of the control gate 6 is removed, a negative charge is generated in the channel formation region due to the residual polarization of the ferroelectric film 5. This is referred to as "1".

Conversely, when a negative voltage is applied to the control gate 6, the ferroelectric film 5 causes polarization reversal in the opposite direction.
Even if the voltage of the control gate 6 is removed, a positive charge is generated in the channel formation region due to the residual polarization of the ferroelectric film 5. This is set to a state of “0”. Thus, F
Information "1" or "0" can be written in the ET. FIG. 7 (a) and FIG. 7 (b)
Indicates a state in which information “1” and information “0” have been written, respectively.

[0007] Reading of written information is executed by applying a read voltage _Vr to the control gate. The read voltage V _r is set to a value between the threshold voltage V _th1 in the “1” state and the threshold voltage V _th0 in the “0” state. Then, when the read voltage Vr is applied to the control gate 8, it is possible to determine whether the written information is "1" or "0" by detecting whether or not a drain current has flowed. It has become.

As described above, according to the FET having the MFMIS structure, one memory cell can be constituted by one element, and nondestructive reading can be performed satisfactorily.

Therefore, the two can be identified.

[0010]

SUMMARY OF THE INVENTION However, the gate
Capacitance C by insulating film_OXThan the capacity C of the memory capacitor
_f1, C_f2Is sufficiently large, the normal gate voltage V_GIs V_G
= 1 / 2V_SDWhen writing “1” and writing “0”
Drain current I_DAnd source-drain voltage V_SDWhen
Are shown in FIGS. 7A and 7B, respectively.
When reading, these values are recognized.
You must set an intermediate voltage so that
No. Therefore, as shown in FIG.
Read between level and maximum level when "0" is written
Switching voltage V_rTo read “1” and “0”
There was a problem that the margin was small. Therefore, "0"
Even if the cell is written,
There is a case where a “1” is written in a cell where a “0” write is
When it is determined that writing has been made or vice versa
was there.

The present invention has been made in view of the above circumstances, and has as its object to provide a nonvolatile memory capable of obtaining highly reliable reading characteristics without causing erroneous reading.

[0012]

A floating gate, a ferroelectric layer, and a control gate are sequentially laminated on a surface of the semiconductor substrate between source / drain regions formed on the semiconductor substrate with a gate insulating film interposed therebetween. MFMI
In a nonvolatile memory in which S-structure transistors are arranged in a matrix, the control gate is connected to a word line, the source region is connected to a source line, and the drain region is connected to a drain line. A write line configured to form a capacitor, the word line and the source line in the same row direction of the matrix are commonly connected, and the drain line and the floating line in the same column direction of the matrix are provided. The lines are connected in common, and the source / drain voltage and the gate voltage can be set independently.

According to a second aspect of the present invention, one memory cell comprises a floating gate, a ferroelectric layer, and a gate insulating film interposed between a source / drain region formed on the surface of the semiconductor substrate. And a control gate are sequentially stacked to form an MFMIS-structured FET, wherein the floating gate extends over the element isolation insulating film, and the floating gate is a write gate formed on the element isolation insulating film. And a capacitor insulating film between them to form a capacitor.

[0014]

By the way, in such an MFMIS transistor, the source / drain voltage and the gate voltage can be set independently, so that the read margin can be increased as shown in the current-voltage characteristics in FIG. In addition, it is possible to provide a highly reliable nonvolatile memory by reducing erroneous reading.

According to the second aspect of the present invention, in addition to the above effects, since the capacitor is constituted by the floating gate extending on the element isolation insulating film,
The above structure can be realized without increasing the cell area.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a nonvolatile memory and a method of driving the same according to the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of a nonvolatile memory according to the present invention. As shown in FIG. 1, a memory cell composed of memory transistors having an MFMIS structure is arranged in a matrix on a semiconductor substrate. . One memory cell is constituted by one memory transistor, and the memory cells are arranged vertically and horizontally, so that the sources of the memory cells in each row in the horizontal direction are connected to each other to form source lines SL1 and SL2.
The drains of the memory cells arranged in each column in the vertical direction are connected to form drain lines DL1, DL2, and the electrodes (write gates) of the capacitors formed below the floating gate are arranged in the column direction. The floating gates are arranged as floating lines FL1, FL2,... And the control gates of the memory cells arranged in each row in the horizontal direction are connected to form word lines WL1, WL2,. , So that a sufficient read margin can be obtained.

The column lines for selecting the columns of memory cells arranged in the vertical direction in FIG. 1 are configured to select, for example, about six or eight columns at a time in this example. The configuration is such that the potential can be set collectively for the data. In the memory cells arranged in the vertical direction on the paper, a drain line DL is formed by connecting drain regions of the respective transistors, and a floating line FL is formed by connecting capacitor electrodes (write gates). Are configured to be able to collectively set the potential.

On the other hand, in the memory cells arranged in the horizontal direction on the paper, a source line SL is formed by connecting the source regions of the respective transistors, and a word line WL is formed by connecting the control gates. The configuration is such that the data of the rows can be collectively set for the potential.

One cell unit of this memory cell is shown in FIG.
(A) As shown in (b), the surface of the semiconductor substrate 1 between the source / drain regions formed on the surface of the semiconductor substrate,
In an FET having an MFMIS structure in which a floating gate 4, a ferroelectric layer 5, and a control gate 6 are sequentially stacked with a gate insulating film 3 interposed therebetween, the floating gate extends over an element isolation insulating film and The gate is provided with a capacitor insulating film 8 between the gate and the capacitor electrode 7 formed on the element isolation insulating film to constitute a capacitor.

According to such a configuration, the data is read out by the usual method as in the prior art. However, as shown in FIG. 3, by setting the potential of each line, as shown in FIG.
The read margin of “1” and “0” can be increased, and a memory with less malfunction can be obtained.

In the above embodiment, the ferroelectric memory having the MFMIS structure has been described. However, the present invention is not limited to this, and the capacitor insulating film formed between the floating gate and the write electrode is limited to the ferroelectric film. Alternatively, a high dielectric constant dielectric or a normal dielectric may be used.

[0023]

As described above, according to the nonvolatile memory of the present invention, the source / drain voltage and the gate voltage can be independently set so that the read margin can be increased, and the reliability can be improved. It is possible to perform highly accurate reading.

[Brief description of the drawings]

FIG. 1 is a diagram showing an equivalent circuit of a nonvolatile memory according to a first embodiment of the present invention.

FIG. 2 is a top view and a cross-sectional view of the nonvolatile memory.

FIG. 3 is a diagram showing a voltage applied to each line of the nonvolatile memory.

FIG. 4 is a diagram showing a relationship between a source / drain voltage and a drain current of the nonvolatile memory.

FIG. 5 is a diagram showing a conventional memory cell.

FIG. 6 is a structural diagram of a conventional nonvolatile memory.

FIG. 7 is a diagram showing signal states when writing (“1”) (“0”) is performed on a selected cell of a conventional nonvolatile memory.

FIG. 8 is a diagram illustrating a read margin of a conventional nonvolatile memory.

[Brief description of reference numerals]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate S Source region D Drain region 2 Element isolation insulating film 3 Gate insulating film 4 Floating gate 5 Ferroelectric film 6 Control gate 7 Write gate (capacitor electrode) 8 Capacitor insulating film

Claims (2)

[Claims] An MFMIS structure in which a floating gate, a ferroelectric layer, and a control gate are sequentially stacked on a surface of the semiconductor substrate between source / drain regions formed on the semiconductor substrate via a gate insulating film. A non-volatile memory in which the transistors are arranged in a matrix, wherein the control gate is connected to a word line, the source region is connected to a source line, the drain region is connected to a drain line, and a capacitor is connected between the floating gate and the floating gate. A floating line composed of a write gate configured to form a matrix, a word line and a source line in the same row direction of the matrix are commonly connected, and a drain line and a floating line in the same column direction of the matrix are Common connection A nonvolatile memory characterized in that a source / drain voltage and a gate voltage can be independently set. 2. A memory cell comprising: a floating gate, a ferroelectric layer, and a control gate sequentially formed on a surface of a semiconductor substrate between a source / drain region formed on the surface of the semiconductor substrate via a gate insulating film; Laminated, MFMI
An S-structure FET, wherein the floating gate extends on an element isolation insulating film, and the floating gate includes a capacitor insulating film between the floating gate and a write gate formed on the element isolation insulating film. A non-volatile memory comprising a capacitor.