JP3153606B2 - Nonvolatile storage element, nonvolatile storage device using the same, and method of driving nonvolatile storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory element, a nonvolatile memory device using the same, and a method of driving the nonvolatile memory device.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile memory device using a ferroelectric material (hereinafter referred to as a nonvolatile memory), as shown in FIG. 6, one ferroelectric capacitor 1 and one switching MOS Type field effect transistor (hereinafter referred to as MOSFET (MetalOxide Semiconductor)
conductor Field Effect Tra
2) as one non-volatile memory element (hereinafter, referred to as a memory cell), and the memory cells are arranged in an array (“VLS”).
I SYSTEM DESIGN "1988 MAY
PP 117-123 S.P. BAKE and JP-A-63
20201998).

In the above-mentioned nonvolatile memory, since destructive reading is performed instead of non-destructive reading, the polarization inversion of the ferroelectric material is large, the fatigue of the ferroelectric thin film is increased, and the number of rewritable times is reduced. In addition, a charge amount (about 30 fF) equivalent to that of a DRAM is required for sensing, and a relatively large residual polarization is required. For this reason, the selection range of the ferroelectric material is reduced, and the suitability for miniaturization is limited, so that it is difficult to manufacture a memory.

To cope with this, a field effect transistor (hereinafter referred to as M) having a ferroelectric gate film in a memory cell is used.
FS (Metal Ferroelectric Se
(hereinafter referred to as M.FET).
Non-destructive reading becomes possible, and the number of rewritable times is improved as compared with the nonvolatile memory of FIG. Also, since what is needed for sensing is not the amount of charge due to remanent polarization but the charge density, it is possible to miniaturize the MOSFET. Furthermore, the remanent polarization required for sensing is 1 μC / cm ²
It is relatively small as follows, and the choice of materials is increased, and the manufacture of the memory is simplified.

FIG. 7 is a sectional view of the MFSFET.
You. In the figure, A is a P-type silicon substrate, SD is an N-type silicon substrate.
Source-drain diffusion layer, 3 is conductive as gate electrode
Thin film, 4 a ferroelectric gate film, 5 an interlayer insulating film, 6 a
A source-drain electrode, comprising a conductive thin film 3 and a ferroelectric
The gate film 4 has an MFS structure. Ferroelectric material
As PZT, PLZT, PbTiO_Three, Ba
TiO_ThreeABO such as_ThreeType (A, B: metal element)
A lobskite structure is used, but ferroelectric
It is not limited as long as the material shows As other material
Is, for example, BaMgF_Four, NaCaF_Three, K_TwoZnC
l_FourHalogen compounds such as Zn_1-XCd _xTe, GeT
e, Sn_TwoP_TwoS₆Such as chalcogen compounds
You. However, the conductive thin film 3 and the ferroelectric gate film 4,
Represents a ferroelectric gate film 4 and a source-drain diffusion layer SD.
It is also possible to insert a buffer layer between them.

The ferroelectric material of the MFSFET has a PE hysteresis characteristic as shown in FIG. In the figure, a voltage that gives an electric field E _sat or more to the ferroelectric is referred to as V
_max (> 0). When a voltage of + V _max is applied to the gate, it is polarized to the state of A and a channel is formed. Thereafter, even if the gate voltage is set to 0, the state becomes B, polarization remains, and the channel remains formed. Conversely, when a voltage of -V _max (or a voltage of + V _max is applied to the substrate) is applied to the gate, polarization is performed to the state of C, and when the voltage is set to 0, D is applied.
State. No channel is formed in this process.

As a non-volatile memory using an MFSFET, as shown in FIG. 9, switching MOSFETs 8 and 9 are connected in series to the source and the drain of an MFSFET 7, respectively, and a total of three transistors constitute one memory cell. An arrangement arranged in an array has been proposed (JP-A-2-64993). A write operation and a write operation of the nonvolatile memory using the MFSFET of FIG. 9 will be described. First, at the time of writing, the word line WL1 is set to the _Vcc potential to turn on the MOSFET 8, the word line WL2 is set to the V _ss potential (ground potential), the MOSFET 9 is turned off, and the data is transferred from the bit line BL to the source-substrate of the MFSFET 7. Is applied. As a result, in the MFSFET 7, a potential of V _cc / 2 is applied between the gate and the substrate, and the ferroelectric enters a predetermined electric polarization state,
Data can be written.

On the other hand, in the read operation, the word line WL2 is set to the _Vcc potential and the MOSFET 9 is turned on, and the word line WL1 is set to the _Vcc potential and the MOSF is set.
Turn ET8 ON. Here, if a potential of _Vcc / 2 or more is pre-charged to the bit line BL by a pre-charge circuit (not shown) in advance, a current flows when the MFSFET 7 is conducting, and the MFSFET 7 is connected. The potential of the bit line BL falls. On the other hand, when the MFSFET 7 is not conducting, no current flows, so that the potential of the bit line BL to which the MFSFET 7 is connected does not change. Therefore, MFSFE
The conduction and non-conduction of T7 are made to correspond to data "1" and "0", and the potential change of the bit line BL is detected and amplified by a corresponding sense amplifier (not shown), so that data can be read. . In this case, it is necessary to set the precharge level of the bit line BL to a potential close to V _cc / 2 as described above so that the electric polarization state of the ferroelectric of the MFSFET 7 is not greatly affected by the disturbance due to the reading. .

[0009]

The nonvolatile memory shown in FIG. 9 has a well 7a formed on a semiconductor substrate on which an MFSFET 7 is formed.
Is formed. In principle, if the inversion voltage is not applied to the MFSFET 7 from the well 7a by operating the substrate voltage, the MF
The data written in SFET 7 is not erased. However, in the nonvolatile memory of FIG. 9, an unnecessary weak voltage is applied to the ferroelectric gate film of the MFSFET of the non-selected cell at the time of writing. In addition, this voltage changes depending on the write state of other cells, and becomes very unstable. Therefore, although the data written in the MFSFET does not break down, a voltage lower than the polarization inversion of the ferroelectric material is applied. In some cases, the reliability may decrease.

Further, since the well 7a is formed to apply an inversion voltage to the ferroelectric gate film of the MFSFET 7, the manufacturing process and the circuit configuration are complicated, and the area is increased. In view of the above, it is an object of the present invention to realize a non-destructive readout nonvolatile memory element having high reliability and a nonvolatile memory device using the same with a small area using an MFSFET. Another object is to provide a driving method.

[0011]

According to a first aspect of the present invention, there is provided a nonvolatile memory element comprising: a first field effect transistor having a ferroelectric gate film for storing electric charges; A second field effect transistor for readout connected in series to the first field effect transistor;
And a thin-film transistor for writing / erasing connected to the gate of the field-effect transistor.

According to a second aspect of the present invention, there is provided the nonvolatile memory element according to the first aspect.
In the nonvolatile memory element described above, a channel portion of the thin film transistor is formed on the impurity diffusion layer of the first field effect transistor via an insulating film. A non-volatile storage device according to a third aspect includes a configuration in which the non-volatile storage elements according to the second aspect are arranged in a matrix.

According to a fourth aspect of the present invention, in the nonvolatile storage device according to the third aspect, a word line for writing / erasing is connected to a source of the thin film transistor, and a gate of the second field effect transistor is connected. A word line for reading is connected to the source, and a bit line is connected to the source. At the time of reading, the current SA is supplied to the bit line connected to the nonvolatile memory element to be read, and the nonvolatile memory element to be read is selected. _Therefore , the voltage _Vcc is applied to the read word line connected to the nonvolatile memory element, and at the time of writing, other than the write / erase word line and bit line connected to the nonvolatile memory element to be written. All lines are grounded, and write / read connected to the nonvolatile memory element to be written. The voltage Vpp is applied to the word line for removed by, for selecting the nonvolatile memory element to write, the voltage V _cc is applied against the non-volatile connected to the storage element bit line, at the time of erasing, the erase All lines other than the write / erase word line and bit line connected to the nonvolatile memory element to be written are grounded, and writing is performed to the write / erase word line connected to the nonvolatile memory element to be written. and applying different voltages -Vpp of time and polarity, for selecting the nonvolatile memory element to write, it is used to apply the voltage V _cc to the connected bit line to the non-volatile memory element.

[0014]

According to the first aspect of the present invention, since a thin film transistor is used as a writing / erasing element, it is not necessary to form a channel portion and a source-drain portion of the thin film transistor on a semiconductor substrate. Therefore,
The area of the nonvolatile memory element can be reduced.

According to a second aspect of the present invention, the channel portion of the thin film transistor is formed on the impurity diffusion layer of the first field effect transistor via the insulating film so that the channel portion is not grounded to the impurity diffusion layer of the first field effect transistor. Therefore, an erase voltage having a polarity different from the write voltage can be applied to the source-drain portion of the thin film transistor without forming an erase well in the semiconductor substrate. Therefore, not only can the manufacturing process and the circuit configuration of the nonvolatile memory element be simplified, but also the area of the nonvolatile memory element can be further reduced because the well does not need to be formed.

The third aspect of the present invention includes a configuration in which the nonvolatile memory elements according to the second aspect are arranged in a matrix, so that the area of the nonvolatile memory device can be reduced. Claim 4
At the time of reading, the second field effect transistor for reading of the selected nonvolatile memory element is turned on,
If the first field-effect transistor is in a write state,
The bit line voltage drops. By detecting and amplifying the voltage change of the bit line, the data of the selected nonvolatile memory element is read.

At the time of writing, a voltage V _pp is applied to the ferroelectric gate film of the first field-effect transistor of the selected nonvolatile memory element, and data is written to the selected nonvolatile memory element. At this time, since the voltage _Vpp is not applied to the ferroelectric gate film of the first field-effect transistor of the non-selected nonvolatile memory element, the data of the non-selected nonvolatile memory element does not need to be soft-written, and Of the non-volatile memory element is surely held.

At the time of erasing, a voltage -V _pp is applied to the ferroelectric gate film of the first field effect transistor of the selected nonvolatile memory element, and the data of the selected nonvolatile memory element is erased. At this time, since the ferroelectric gate film of the first field effect transistor of the unselected nonvolatile storage elements not applied voltage -V _pp, data of the non-selected nonvolatile memory element is not erased.

Therefore, the reliability of the nonvolatile memory at the time of reading is improved, and random access in bit units becomes possible.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to FIGS. First, a circuit configuration of a nonvolatile memory device (hereinafter, referred to as a nonvolatile memory) of the present embodiment will be described with reference to an electric circuit diagram shown in FIG. As shown in FIG. 1, the nonvolatile memory according to the present embodiment includes a plurality of nonvolatile memory elements (hereinafter, referred to as memory cells) 10A, 10B, 10A.
Are arranged in a matrix, and the memory cells 10A, 10B, 10C, 10D,.
Is a first field effect transistor (hereinafter, referred to as an MFSFET (MeSFET) having a ferroelectric gate film for accumulating electric charges.
tal Ferroelectric Semiconductor
ductor Field Effect Trans
istor)) 11A, 11B, 11C, 11D
... and MFSFETs 11A, 11B, 11C, 11
D... Are connected in series to a second MOS field effect transistor for reading (hereinafter referred to as MOS (Metal O.D.
xAxide Semiconductor) FET) 12A, 12B. 12C, 12D ... and MFS
The MOS type thin film transistor for writing / erasing (hereinafter referred to as a MOSTFT (Thin Film Tr) connected to the gates of the FETs 11A, 11B, 11C, 11D,.
anistor) 13A, 13B, 13C,
13D...

MOSTFTs 13A, 13B, 13C, 1
Are connected to write / erase word lines WEWL1, WEWL2,. On the other hand, MOSFETs 12A, 12B. 12C, 12D ...
Gates are read word lines RWL1, RWL
In WL2, the sources are bit lines BL1, BL
2 are connected to each other. And MOST
The gates of the FTs 13A, 13B, 13C, 13D,. 12C, 12D ...
. And bit lines BL1, BL2,...

FIG. 2 shows the structure of the nonvolatile memory.
This will be described with reference to FIG. FIG. 2 is a cross-sectional view of a part of the nonvolatile memory, and shows the configuration of the MFSFET and the MOSTFT. FIG. 3 is a plan view of the same. In the figure, 20 is a P-type silicon substrate, 21 is a field oxide film, 22A and 22B are N-type impurity diffusion layers serving as source-drain regions of MFSFET, and 23 is MFS
An interlayer insulating layer 24 is formed on the gate electrode 23 of the MFSFET. The ferroelectric film 25 and the MOSTF are formed on the interlayer insulating layer 24.
A conductive thin film 26 serving as a T gate electrode is sequentially laminated.

Then, on the conductive thin film 26 serving as the gate electrode of the MOSTFT and the source-drain diffusion layer 22A, the source-drain portions 27A, 27 of the MOSTFT are provided.
B and a channel portion 28 are provided. In particular, MO
The channel portion 28 of the STFT is connected to the MF through an insulating film 29.
It is formed on the source-drain diffusion layer 22A of the SFET. In FIG. 2, reference numeral 30 denotes an interlayer insulating layer, and 31 denotes a protective film.

FIG. 4 is a sectional view showing a method for manufacturing the above-mentioned nonvolatile memory in the order of steps. The method for manufacturing the nonvolatile memory will be described with reference to this figure. The step shown in FIG. 4A is almost similar to the step of the conventional MOSTFT. The difference from the conventional MOSTFT process is that, when forming an element region on the P-type silicon substrate 20, one side of the impurity diffusion layer 22A serving as the source-drain region of the MFSFET is formed only on one side of the gate electrode 23 of the MFSFET. And forming the interlayer insulating layer 24 on the gate electrode 23 in advance. The reason why the interlayer insulating layer 24 is formed on the gate electrode 23 is to prevent the polarization reversal of the ferroelectric layer laminated in a later step. Therefore, it is preferable to use a material having a low dielectric constant, such as silicon oxide, for the interlayer insulating layer 24.

Then, as shown in FIG. 4B, the silicon substrate 20, the field oxide film 21, the source-drain diffusion layer 22A of the MFSFET and the gate electrode 23 of the MFSFET are patterned by the photolithography technique. PZT ferroelectric film 25 and MO
A conductive thin film 26 serving as a gate electrode of the STFT is sequentially laminated. Although PZT is used as the ferroelectric material, the material is not limited as long as the material has ferroelectricity as described above. However, since PZT has poor matching with silicon, it is preferable to provide an intermediate layer on the ferroelectric film 25. As the intermediate layer, a fluoride having a fluorite structure such as CaF ₂ or SrF ₂ is preferable.

Next, as shown in FIG. 4C, the ferroelectric film 2
5 and the gate electrode 26 of the MOSTFT are etched. As the processing method of the ferroelectric, wet etching may be used, but etching by ion milling, RIBE, RIE, or the like, which is excellent in fine workability, is preferable. Next, as shown in FIG. 4D, the other-side impurity diffusion layer 22B serving as the source-drain region of the MFSFET is
The one-sided impurity diffusion layer 22A serving as the source-drain region of the MFSFET formed in the step of FIG.
The ET is formed on the opposite side across the gate electrode 23. Then, after forming a silicon oxide film and etching back to form a sidewall, an insulating film 29 is formed on an exposed portion of the silicon substrate 20 by a thermal oxidation method. Then, the source-drain portions 27A and 27B of the MOSTFT
And polysilicon for forming the channel portion 28 or amorphous silicon, and the source-drain portion 27
Impurities are implanted into the source-drain portions 27A and 27B so that A and 27B and the channel portion 28 have different conductivity types.

The step shown in FIG. 4E is the same as that of the conventional semiconductor device manufacturing process, in which an interlayer insulating layer 30 such as PSG or BPSG, a contact, a wiring layer such as aluminum, and a protective film 31 are sequentially formed. Thus, the nonvolatile memory is completed. As shown in FIG. 1, MOST is used for the write / erase element.
Since the FTs 13A, 13B, 13C, 13D... Are used, the MOSTFTs 13A, 13B, 13C, 13D
.. Need not be formed on the semiconductor substrate. That is, as shown in FIG. 2, the TFT is formed in the field region 21 of the semiconductor substrate, the ferroelectric film 25 of the MFSFET and the source-drain diffusion layer 2 of the MFSFET.
Since it can be formed over 2A or the like, the area of the memory cell can be reduced.

Further, in the nonvolatile memory shown in FIG. 9, only a positive or negative voltage can be applied to the MFSFET unless a well is formed in the semiconductor substrate and the substrate voltage is not manipulated. As shown in FIG.
The channel portion 28 of the FT is
ET formed on the source-drain diffusion layer 22A of ET,
Since the source-drain diffusion layer 22A of the SFET is not grounded, the source-drain diffusion layer 22A of the MFSFET can be formed without forming a well in the semiconductor substrate.
Can be applied to the positive and negative voltages. Therefore, not only the manufacturing process and the memory circuit are simplified, but also the area of the memory cell is further reduced by not forming the well.

Next, a method of driving the nonvolatile memory will be described with reference to FIG. 1 and Table 1. The MFSF shown in FIG.
ET11A, 11B, 11C, 11D ..., MOSF
ET12A, 12B. 12C, 12D ... and MO
STFTs 13A, 13B, 13C, 13D,... Are all N-channel transistors,
The conduction state (ON state) of A, 11B, 11C, 11D,... Is defined as a write state “1”. For convenience of explanation, the memory cell 10A is selected, and the memory cell 10A is selected.
It is assumed that the data processing is performed.

[0030]

[Table 1]

<Read (READ)> Bit line B
Supplying a current SA to the sources of the MOSFETs of all the memory cells connected to the bit line BL1 via L1;
To select the memory cell 10A, the voltage _Vcc is applied to the gates of the MOSFETs of all the memory cells connected to the word line RWL1 via the read word line RWL1. Then, the read MOSFET 12A of the memory cell 10A turns on, and the MFSFET 1
If 2A is "1", the voltage of bit line BL1 drops. By detecting and amplifying the voltage change of the bit line BL1, the data of the memory cell 10A is read.

Since the current SA is not supplied to the bit line BL2 and the voltage _Vcc is not applied to the read word line RWL2, the read MOSFETs of the non-selected memory cells other than the memory cell 10A are turned off.
The data of the non-selected memory cell is not read. <Write> All lines other than the word line WEWL1 and the bit line BL1 are grounded. Word line WEWL1 for writing / erasing
A voltage V _pp is applied to MOSTFT sources of all the memory cells connected to the word line WEWL1 through,
In order to select the memory cell 10A, the bit line BL
A voltage _Vcc is applied to the sources of the MOSFETs of all the memory cells connected to the bit line BL1 via the bit line BL1.
As a result, the voltage V _pp is applied to the ferroelectric gate film of the MFSFET 11A of the memory cell 10A,
Data “1” is written to 0A.

At this time, the voltage V _pp is applied to the ferroelectric gate films of the MFSFETs of the non-selected memory cells other than the memory cell 10.
, The data of the non-selected memory cells does not have to be soft-written, and the data of the non-selected memory cells is reliably held. <Erasing (ERASE)> Erasing is basically the same as in writing. The difference is that the word line WEW
A voltage -V _pp having a polarity different from that at the time of writing is applied to the sources of the MOS TFTs of all the memory cells connected to the word line WEWL1 via L1, and data "0" is written to the memory cell 10A to write data "0" to the memory cell 10A. The only point is to erase the data.

At this time, the voltage −V is applied to the ferroelectric gate films of the MFSFETs of the non-selected memory cells other than the memory cell 10.
_{Since pp} is not applied, the data of the non-selected memory cell is not erased. Therefore, the reliability of the nonvolatile memory at the time of reading is improved, and random access in bit units becomes possible.

It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that many modifications and changes can be made within the scope of the present invention. For example, in the above embodiment, the diffusion layer between the MFSFET and the read MOSFET has no particular signal input / output, so the diffusion layer between the MFSFET and the MOSFET is removed as shown in FIG. One MFSFET and one MOSFET for reading
Two split-type FETs may be used. As a result, the area of the nonvolatile memory can be further reduced.

Further, the configuration may be such that the memory cell of the present invention is used as a part of the nonvolatile memory.

[0037]

As is apparent from the above description, according to the first aspect of the present invention, the channel portion and the source-drain portion of the thin film transistor for writing / erasing do not need to be formed on the semiconductor substrate, and the nonvolatile memory element is provided. Area can be reduced. According to the second aspect, an erase voltage having a polarity different from a write voltage can be applied to the source-drain portion of the thin film transistor without forming an erase well in the semiconductor substrate. Therefore, not only can the manufacturing process and the circuit configuration of the nonvolatile memory element be simplified, but also the area of the nonvolatile memory element can be further reduced because the well does not need to be formed.

According to the third aspect, the area of the nonvolatile memory device can be reduced. According to claim 4, at the time of writing,
A voltage V _pp is applied to the ferroelectric gate film of the first field effect transistor of the selected non-volatile memory element. At this time, the ferroelectric of the first field effect transistor of the non-selected non-volatile memory element Since the voltage V _pp is not applied to the body gate film, the data of the non-selected nonvolatile memory element does not need to be soft-written. Therefore, since the data of the non-selected nonvolatile memory elements is securely held, the reliability of the nonvolatile memory device at the time of reading is improved, and random access in bit units becomes possible.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram of a nonvolatile memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a part of the nonvolatile memory device.

FIG. 3 is a plan view of a part of the nonvolatile memory device.

FIG. 4 is a sectional view illustrating a method of manufacturing the nonvolatile memory device in the order of steps.

FIG. 5 is an electric circuit diagram of a nonvolatile memory device according to another embodiment.

FIG. 6 is an electric circuit diagram of a conventional nonvolatile memory element using a ferroelectric capacitor.

FIG. 7 is a sectional view of a field-effect transistor having a ferroelectric gate film.

FIG. 8 is a diagram showing PE hysteresis characteristics of a ferroelectric substance.

FIG. 9 is an electric circuit diagram of a conventional nonvolatile memory element using a field effect transistor having a ferroelectric gate film.

[Explanation of symbols]

10A, 10B, 10C, 10D ... Memory cells 11A, 11B, 11C, 11D ... MFSFETs 12A, 12B, 12C, 12D ... MOSFETs 13A, 13B, 13C, 13D ... MOSTFTs 22A, 22B MFSFET Source-drain diffusion layer 23 Gate electrode of MFSFET 25 Ferroelectric film 26 Gate electrode of MOSTFT 27A, 27B Source-drain part of MOSTFT 28 Channel part of MOSTFT 29 Insulating film WEWL1, WEWL2 ... Word line for writing / erasing RWL1, RWL2 ... Read word line BL1, BL2 ... Bit line

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ identification code FI H01L 29/792 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 27/105 H01L 21/8247 H01L 29/786 H01L 29/788 H01L 29/792 G11C 11/22

Claims (4)

(57) [Claims] A first field-effect transistor having a ferroelectric gate film for storing electric charge; a second field-effect transistor for reading connected in series with the first field-effect transistor; And a write / erase thin film transistor connected to the gate of the field effect transistor. 2. The nonvolatile memory device according to claim 1, wherein a channel portion of the thin film transistor is formed on an impurity diffusion layer of the first field effect transistor via an insulating film. element. 3. The nonvolatile memory device according to claim 2, wherein the nonvolatile memory element includes a configuration arranged in a matrix. 4. The non-volatile memory device according to claim 3, wherein a word line for writing / erasing is connected to a source of the thin film transistor, a word line for reading is connected to a gate of the second field effect transistor, and a bit is connected to a source of the second field effect transistor. The lines are connected to each other, and at the time of reading, the current SA is supplied to the bit line connected to the nonvolatile memory element to be read, and the bit line connected to the nonvolatile memory element is selected to select the nonvolatile memory element to be read. A voltage _Vcc is applied to the read word line, and at the time of writing, all lines other than the write / erase word line and bit line connected to the nonvolatile memory element to be written are written to the ground state. The voltage Vpp is applied to the write / erase word line connected to the nonvolatile memory element. And pressure, for selecting the nonvolatile memory element to write, the voltage V _cc is applied to the connected bit line to the non-volatile storage elements, at the time of erasing, writing and connected to non-volatile storage elements to erase With all lines other than the erase word line and the bit line grounded, a voltage -Vpp having a polarity different from that at the time of writing is applied to the write / erase word line connected to the nonvolatile memory element to be written. Applying a voltage _Vcc to a bit line connected to the nonvolatile memory element to select a nonvolatile memory element to be written.