JPH07176184A - Semiconductor memory and writing and reading method for data in the semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory which can surely read and write data even when a memory cell is more miniaturized, and a writing and reading method for data in the semiconductor memory. CONSTITUTION:A memory cell MC comprises a storage node SN which holds a high potential VH or a low potential VL indicating a binary signal, a writing transistor Q1, and a reading transistor Q2. When data is read out, after a read- out bit line BL1' is previously charged, a potential of a read-out word line WL1' is dropped and a threshold value of the transistor Q2 is varied, the transistor Q2 is turned on or off in accordance with the potential VH or VL of the storage node SL. The potential VH or VL of the storage node SN is discriminated by detecting a current flowing the read-out bit line BL1' by a sense amplifier S/A1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of writing and reading data in the semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of memory cells arranged in rows and columns to read and write data. The present invention relates to a possible semiconductor memory device and a data writing / reading method in the semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 10 is a circuit block diagram showing a structure of a conventional semiconductor memory device H with a part thereof omitted. This semiconductor memory device H includes a plurality of memory cells MC arranged in rows and columns (abbreviated in 2 rows and 2 columns in the figure), each memory cell MC being a transistor Q and a storage connected in series. Includes node SN and capacitor CP. In this semiconductor memory device H, word lines WL1 and WL2 provided corresponding to each memory cell row, and bit lines BL1 and BL2 provided corresponding to each memory cell column.
And a precharge line PCL and transistors QB1 and QB for precharging the bit lines BL1 and BL2.
2 and sense amplifiers S / A1 and S / A2 for detecting potential changes of bit lines BL1 and BL2.

The source of the transistor Q of each memory cell MC is connected to the bit line BL1 or BL2 of that memory cell column, and the gate of the transistor Q of each memory cell MC2 is connected to the word line WL1 or WL2 of that memory cell row. , One electrode of the capacitor C of each memory cell MC is grounded. Further, one ends of the bit line lines BL1 and BL2 are connected to the sense amplifiers S / A1 and S / A2,
The other end of the bit lines BL1 and BL2 is a transistor QB
It is connected to the precharge line PCL via 1 and QB2.

When writing data, for example, the potential of bit line BL1 is set to high potential VH or low potential VL (corresponding to binary signal "1" or "0") and then word line WL1 is set. Boost. Thereby, the word line WL1
The transistor Q of the memory cell MC connected to is turned on, and the storage node SN of the memory cell MC connected to both the bit line BL1 and the word line WL1 becomes the same potential as the bit line BL1 and the potential V of the storage node SN
An electric charge of an amount corresponding to H or VL is stored in the capacitor C. Thereafter, the word line WL1 is stepped down to turn off the transistor Q, and the writing of data to the memory cell MC is completed. In such a semiconductor memory device H, since the electric charge accumulated in the capacitor CP diffuses from the drain of the transistor Q to the semiconductor substrate and gradually decreases, data is periodically rewritten (refresh). There is a need to.

When data is read, the transistor QB1 is turned on to precharge the bit line BL1 to a potential between the low potential VL and the high potential VH, and then the word line WL1 is boosted to turn on the transistor Q. . As a result, the charge stored in the capacitor C is transferred to the bit line B.
It flows into L1 and the potential of the bit line BL1 changes. When the potential written in storage node SN is high potential VH, the potential of bit line BL1 rises, and conversely, when the potential written in storage node SN is low potential VL, the potential of bit line BL1 is increased. The potential drops. This change in potential is detected by the sense amplifier S / A1 to detect the storage node S
It is determined whether N is the high potential VH or the low potential VL,
It is determined whether the binary signal stored in the memory cell MC is "1" or "0".

[0006]

However, in such a semiconductor memory device H, when the miniaturization of the memory cell MC is advanced, the electrode area of the capacitor CP is reduced and the amount of charge accumulated in the capacitor C is reduced. However, the sense amplifiers S / A1 and S / A2 cannot determine the amount of change in the potentials of the bit lines BL1 and BL2 during reading, which makes it difficult to read data.

Attempts have been made to extend the limit of miniaturization by increasing the area of electrodes by increasing the electrode area by adopting a three-dimensional structure for the capacitor CP or by adopting a high dielectric constant insulating film, but it is not easy. .

Therefore, a main object of the present invention is to provide a semiconductor memory device capable of surely reading and writing data even when the miniaturization of memory cells is advanced, and a data writing and reading method in the semiconductor memory device. Is.

[0009]

According to another aspect of the present invention, there is provided a semiconductor memory device having a plurality of memory cells arranged in rows and columns, wherein the memory cells can read and write data. A storage node holding a first or second potential representing a binary signal, a first electrode thereof connected to the storage node, and a second electrode to which the first or second potential is applied. A write transistor to which a write command signal for instructing the writing of the binary signal to the storage node is input to the control electrode, and a first control electrode connected to the storage node, And the second
Is connected to a conduction state detecting means for detecting a conduction state between the first and second electrodes, and the second control electrode reads out the binary signal written in the storage node. And a read transistor to which a read command signal for commanding is input.

A second semiconductor memory device according to the present invention comprises a plurality of memory cells arranged in the row and column directions and is capable of reading and writing data, wherein the memory cells are binary signals. A ferroelectric capacitor polarized to a first or second state, and its first electrode connected to one electrode of the ferroelectric capacitor,
A first or second potential for polarizing the ferroelectric capacitor to the first or second state is applied to its second electrode, and the binary value to the ferroelectric capacitor is applied to its control electrode. A write transistor to which a write command signal for commanding signal writing is input, a first control electrode thereof is connected to the other electrode of the ferroelectric capacitor, and first and second electrodes thereof are connected to the first electrode and the second electrode. A read command signal which is connected to a conductive state detecting means for detecting a conductive state between the first and second electrodes and commands the second control electrode to read the binary signal written in the storage node. And a read transistor to which is input.

Further, the write transistor may be a bulk transistor formed on a semiconductor substrate, and the read transistor may be a thin film transistor formed above the read transistor in an insulating manner.

The second control electrode of the read transistor may be provided directly on the channel region of the read transistor or via an insulating film.

Further, the insulating film may have a film thickness equal to or smaller than that of the gate insulating film.

A write word line and a read word line provided corresponding to each memory cell row, and a write bit line and a read bit line provided corresponding to each memory cell column are provided. The control electrode of the write transistor of each memory cell forming each memory cell row is connected to the write word line, and the second control electrode of the read transistor of each memory cell forming each memory cell row is read out. A second electrode of a write transistor of each memory cell connected to a word line and forming each memory cell column is connected to the write bit line, and a read transistor of each memory cell forming each memory cell column is connected. The second electrode of may be connected to the read bit line.

Further, the second electrode of the write transistor of each memory cell forming each memory cell column is connected to the storage node of the memory cell adjacent in one direction, and the write transistor of the memory cell at one end in one direction. The second electrode of may be connected to the write bit line.

Further, the second electrode of the read transistor of the memory cell forming each of the memory cell columns is connected to the first electrode of the read transistor of the memory cell adjacent in one direction, and the memory cell at the end of the one direction is connected. The second electrode of the read transistor may be connected to the read bit line.

The write bit line and the read bit line may be shared. The write transistor and the read transistor may be transistors having different conductivity types, and the write word line and the read word line may be shared.

According to the first method of writing and reading data in the semiconductor memory device of the present invention, a storage node holding a first or second potential representing a binary signal, and the storage node having the binary value are provided. A method of writing and reading data in a semiconductor memory device having a memory cell including a write transistor for writing a signal and a read transistor for reading the binary signal written in the storage node. Then, the first or second potential is applied to the second electrode of the write transistor, the write command signal is output to the control electrode of the write transistor, and the first or second potential is applied to the storage node. 2 is held, a read command signal is output to the second control electrode of the read transistor to change the threshold value of the read transistor, and the read state is detected by the conduction state detecting means. It is characterized by determining the potential of the storage node from the conduction state between the first and second electrodes.

A second method of writing and reading data in a semiconductor memory device of the present invention is a ferroelectric capacitor polarized to a first or second state representing a binary signal, and the ferroelectric capacitor. Of a data in a semiconductor memory device including a memory transistor including a write transistor for writing the binary signal in the memory and a read transistor for reading the binary signal written in the ferroelectric capacitor. A writing and reading method, wherein a first or second potential is applied to a second electrode of the write transistor, and a write command signal is output to a control electrode of the write transistor to output the ferroelectric substance. The capacitor is polarized into the first or second state, a read command signal is output to the second control electrode of the read transistor to change the threshold value of the read transistor, and the conduction state is changed. It said detected by the detection means first
And the state of polarization of the ferroelectric capacitor is determined from the conduction state between the second electrodes.

[0020]

According to the first semiconductor memory device of the present invention and the method of writing and reading data in the semiconductor memory device, a memory node and a write holding a first or second potential representing a binary signal are provided. A memory cell including a built-in transistor and a read transistor is provided. The storage node is connected between the first electrode of the write transistor and the first control electrode of the read transistor. When writing data, the first or second potential is applied to the second electrode of the write transistor, the write command signal is output to the control electrode, and the first or second potential is applied to the storage node. Hold it. When reading data, a read command signal is output to the second control electrode of the read transistor to change its threshold value, the conduction state between the first and second electrodes is detected, and the potential of the storage node is detected. To judge. Since the potential of the storage node is converted into the conductive state of the read transistor and the data is read in this way, the amount of charge at the time of data read does not become insufficient unlike the conventional case even when the miniaturization of the memory cell is advanced. , The data can be read reliably.

Further, according to the second semiconductor memory device of the present invention and the method of writing and reading data in the semiconductor memory device, the ferroelectric is polarized to the first or second state representing a binary signal. A memory cell including a body capacitor, a write transistor and a read transistor is provided. The ferroelectric capacitor is connected between the first electrode of the write transistor and the first control electrode of the read transistor. When writing data, the first or second potential is applied to the second electrode of the write transistor, and the write command signal is output to the control electrode to set the ferroelectric capacitor to the first or second.
To the state of. When reading data, a read command signal is output to the second control electrode of the read transistor to change its threshold value, the conduction state between the first and second electrodes is detected, and the ferroelectric capacitor is detected. Determine the polarization state of. In this way, the polarization state of the ferroelectric capacitor is converted into the conduction state of the read transistor for reading, so that even if the miniaturization of the memory cell is advanced, the amount of charge at the time of data reading is insufficient as in the conventional case. Data can be read without fail. Further, since the binary signal is converted into the polarization state of the ferroelectric capacitor and stored, the stored data does not volatilize.

[0022]

[Embodiment 1] FIG. 1 is a partially omitted circuit block diagram showing a configuration of a semiconductor memory device A according to a first embodiment of the present invention. In the figure, this semiconductor memory device A is provided corresponding to a plurality of memory cells MC (abbreviated in 2 rows and 2 columns in the figure) arranged in the row and column directions and corresponding to each memory cell row. Write word lines WL1 and WL2 and read word lines WL1 'and WL2', write bit lines BL1 and BL2 and read bit lines BL1 'and BL2' provided corresponding to each memory cell column, and read bit lines. BL1 ',
Precharge line PC for precharging BL2 '
L and transistors QB1 and QB2, and sense amplifiers S / A1 and S / A2 for detecting potential changes on read bit lines BL1 'and BL2' are included.

Each memory cell MC has a storage node SN holding high potential VH or low potential VL representing a binary signal, write transistor Q1 for writing potential VH or VL to storage node SN, and storage node SN. Read transistor Q2 for reading potential VH or VL of. The gate of the write transistor Q1 of each memory cell MC2 is connected to the write word line WL1 or WL2 of that memory cell row, its source is connected to the write bit line BL1 or BL2 of that memory cell column, and its drain is It is connected to the storage node SN. In addition, the read transistor Q2 of each memory cell MC
Is connected to the storage node SN, its drain is grounded, its source is connected to the read bit line BL1 'or BL2' of that memory cell column, and its back gate is the read word line WL1 'of that memory cell row. Or it is connected to WL2 '. In addition, the read bit line B
One ends of L1 'and BL2' are sense amplifiers S / A1 and S
/ A2 and the other ends of the read bit lines BL1 'and BL2' are connected to the precharge line PCL via the transistors QB1 and QB2.

During the standby, the read word lines WL1 ', WL
A back gate bias is applied to 2'to increase the threshold voltage of the read transistor Q2 and turn off the read transistor Q2 regardless of the potentials VH and VL of the storage node SN and the potentials of the read bit lines BL1 'and BL2'. deep.

When writing data, first, for example, the potential of write bit line BL1 is set to high potential VH or low potential VL.
Then, the write word line WL1 is boosted to turn on the write transistor Q2. As a result, the write bit line B
The potential of the storage node SN of the memory cell MC connected to both L1 and the write word line WL1 is the write bit line B.
It becomes the same as the potential VH or VL of L1. After that, when the write word line WL1 is stepped down to turn off the write transistor Q1, the potential of the storage node SN becomes high potential VH.
Alternatively, it is fixed to the low potential VL. That is, high potential VH or low potential VL is written in storage node SN.

When reading data, first, the transistor QB1 is turned on to precharge the potential of the read bit line BL1 'to the potential of the judgment reference. After closing the transistor QB1, the potential of the read word line WL1 'is lowered, the read transistor Q2 is turned on if the storage node SN is at the high potential VH, and the read transistor Q2 is turned off if the storage node SN is at or below the low potential VL. Set it to such a potential. When the read transistor Q2 is turned on, the potential of the read bit line BL1 'changes toward the ground potential,
When the read transistor Q2 is off, the potential of the read bit line BL1 'does not change. Therefore, the potential of the storage node SN can be detected by detecting the current flowing through the read bit line BL1 'with the sense amplifier S / A1 having a capacitive or resistive load. Since the read transistor Q2 of the other memory cell MC connected to the same read bit line BL1 'is in the off state, it does not affect the determination operation. The refresh is performed by sending the data detected by the sense amplifier S / A1 to the write bit line BL1.

FIG. 2 is a partially cutaway sectional view illustrating a specific structure of the memory cell MC shown in FIG. Hereinafter, by explaining a method of manufacturing the memory cell MC,
To clarify its structure. First, on the active region partitioned by the silicon oxide film 10 of the silicon substrate 1, the gate electrode 2 (write word line W) forming the write transistor Q1 is formed.
L), the source region 1a and the drain region 1b are formed. Write bit line B in contact with source region 1a
After forming L, the whole is covered with the interlayer insulating film 11. Next, the storage node SN is penetrated through the interlayer insulating film 11.
Is formed, its lower end is brought into contact with the drain region 1b, and its upper end is projected from the interlayer insulating film 11. Up to this point, the steps are the same as those of a normal DRAM.

Next, the surface of the storage node SN protruding from the surface of the interlayer insulating film 11 is covered with a thin insulating film 5 (for example, a thermal oxide film), and the silicon thin film 6 is overlaid thereon.
The silicon thin film 6 serves as a channel region of the read transistor Q2, and the storage node SN also serves as the gate electrode of the read transistor Q2. Read transistor Q2
The threshold voltage of is adjusted by ion implantation at this time.
Furthermore, a back gate 7 made of, for example, silicon is further formed thereon.
And ion implantation is performed, the source region 6a and the drain region 6b are formed in the silicon thin film 6 in a self-aligned manner.

In this embodiment, the charge of the storage node SN is amplified by the read transistor Q2 and supplied to the read bit line BL1 ', so that the charge of the storage node SN is supplied as it is to the bit line BL1. , Can supply a lot of charge. Therefore,
Even if the miniaturization of the memory cell MC is advanced,
It is possible to surely read data without causing a shortage of the amount of electric charge at the time of reading data as in the conventional case.

Further, in the conventional technique, the portion of the storage node SN protruding from the insulating film 11 is the capacitor C.
Since it corresponds to one of the electrodes, it is necessary to increase the surface area of the protruding portion of the storage node SN in order to increase the charge amount, which makes it difficult to miniaturize the storage node SN. Since the protruding portion of SN serves as the gate of the read transistor Q2, its size may be about the gate length of the write transistor Q1. It is also possible to increase the gate length of the read transistor Q2 by increasing the film thickness of the protruding portion of the storage node SN, and to make the gate length of the read transistor Q2 longer than the gate length of the write transistor Q1. Therefore, the read transistor Q2 can be formed above the write transistor Q1 in the same area as or smaller than that of the write transistor Q1. Therefore, the write transistor Q1 is not restricted by the electrode area of the capacitor C as in the conventional case.
The miniaturization of the memory cell MC can be advanced to the limit of miniaturization.

[Embodiment 2] FIG. 3 is a partially cutaway sectional view showing the structure of a memory cell MC 'of a semiconductor memory device according to a second embodiment of the present invention. The memory cell MC 'is different from the memory cell MC shown in FIG. 2 in that an insulating film 8 is provided between the silicon thin film 6 and the back gate 7 of the read transistor Q2. Since the other structure is the same as that of the memory cell MC shown in FIG. 2, description thereof will be omitted.

Since the silicon thin film 6 usually has grain boundaries and the like, the leakage current from the PN junction is large. Therefore, if the silicon thin film 6 and the back gate 7 are directly connected as usual, the current leaking from the source region 6a and the drain region 6b of the silicon thin film 6 to the back gate 7 may not be negligible. Therefore, the silicon thin film 6 and the back gate 7 are separated by the insulating film 8 in order to reduce the leakage current.

However, it is necessary to make the thickness of the insulating film 8 as thin as possible. When the insulating film 8 has a large thickness, when hot carriers are generated in the silicon thin film 6, a large amount of hot carriers toward the back gate 7 are trapped between the silicon thin film 6 and the insulating film 8 and trapped. This is because the electric field due to hot carriers behaves as a back gate voltage, which is equivalent to applying a certain voltage without applying the back gate voltage, and the read transistor Q2 does not operate normally. If the insulating film 8 is thinned,
The amount of hot carriers trapped decreases, and the read transistor Q2 operates normally.

[Third Embodiment] FIG. 4 is a partially omitted circuit block diagram showing a structure of a semiconductor memory device B according to a third embodiment of the present invention. This semiconductor memory device B has the write bit line BL1 and the read bit line BL1 'in common in the semiconductor memory device A shown in FIG. That is, in the semiconductor memory device B, the write bit lines BL1 and BL2 are omitted in the semiconductor memory device A, and each memory cell MC
Of the write transistor Q1 is connected to the read bit line BL1 'or BL2' of the memory cell column. In the semiconductor memory device A of FIG. 1, unless data is written to the memory cell MC of the same memory cell column during data reading, the write bit line BL of the memory cell column is written.
No need to use 1, BL2. Therefore, if such an operation is prohibited, there is no problem in operation even if the write bit lines BL1 and BL2 and the read bit lines BL1 'and BL2' are shared.

When writing data, first, for example, the potential of bit line BL1 'is set to high potential VH or low potential VL, and then write word line WL1 is boosted to turn on write transistor Q1. As a result, the bit line BL1 '
Memory cell M connected to both the write word line WL1 and the write word line WL1
The potential of the storage node SN of C becomes the same as the potential VH or VL of the bit line BL1 '. Next, when the write word line WL1 is stepped down to turn off the write transistor Q1, the potential VH or VL of the storage node SN is fixed.

When reading data, first, the transistor QB1 is turned on to precharge the bit line BL1 'to the potential of the judgment reference. After turning off the transistor QB1, the potential of the read word line WL1 'is lowered, the read transistor Q2 is turned on if the potential of the storage node SN is about the high potential VH, and turned off if the potential of the storage node SN is lower than the low potential VL. The potential is set as follows. When the read transistor Q2 is turned on, the bit line BL1 '
When the read transistor Q2 is off, the potential of the bit line BL1 'does not change. Therefore, the potential of storage node SN can be detected by detecting the current flowing through bit line BL1 'with sense amplifier S / A1.

In this embodiment, the number of bit lines is halved as compared with the semiconductor memory device A of FIG. 1, which is advantageous for miniaturization. However, it is functionally inferior to the semiconductor memory device A of FIG. 1 in that data cannot be written to other memory cells in the same memory cell column during data reading.

[Embodiment 4] FIG. 5 is a circuit block diagram showing a structure of a semiconductor memory device C according to a fourth embodiment of the present invention with a part thereof omitted. This semiconductor memory device C is similar to the semiconductor memory device A shown in FIG.
L2 and the read word line WL1 'or WL2' are commonly used. That is, in the semiconductor memory device C, the read word lines WL1 ′ and WL2 ′ of the semiconductor memory device A are omitted, and the back gate of the read transistor Q2 of each memory cell MC is set to the write word line WL1 or WL2 of the memory cell row. It is connected. Also, write word line WL
One of the write transistor Q1 and the read transistor Q2 is an N-channel MOS transistor and the other is a P-channel MOS transistor so that the write transistor Q1 and the read transistor Q2 do not turn on at the same time when the voltage WL1, WL2 is stepped up or down. There is. In FIG. 5, the write transistor Q1 is an N-channel MOS transistor,
The read transistor Q2 is a P-channel MOS transistor.

During standby, the transistors Q1 and Q2 of all memory cells MC are turned off. That is, the read transistor Q2 and the write transistor Q1 are irrespective of the potentials of the storage node SN and the bit lines BL and BL '.
Is applied to the word lines WL1 and WL2 in advance.

When writing data, for example, the write bit line BL1 is set to the high potential -VH or the low potential -VL,
The word line WL1 is boosted from the standby voltage in the positive voltage direction to turn on the write transistor Q1. At this time, the read transistor Q2, which is a P-channel MOS transistor, is
It does not turn on because the threshold voltage rises in the negative direction. Then, when the word line WL1 is returned to the original standby voltage, the write transistor Q1 is turned off and the potential of the storage node SN is fixed to the high potential −VH or the low potential −VL.

When reading data, first, the transistor QB1 is turned on to precharge the read bit line BL1 '. Next, after turning off the transistor QB1, the potential of the word line WL1 is reduced in the negative potential direction,
If the storage node SN is at a high potential -VH, the read transistor Q2 is turned on, and if the storage node SN is smaller than the low potential -VL in absolute value, the read transistor Q2.
The potential is set so that 2 turns off. By this operation, the conduction state of the read transistor Q2 becomes the storage node SN.
Changes depending on the potential -VH or -VL. Therefore, the potential -VH or -VL written in storage node SN can be determined by detecting the current flowing through read bit line BL1 'at this time with sense amplifier S / A1. In this operation, write transistor Q1, which is an N-channel MOS transistor, is not turned on, and storage node SN potential -VH or -VL is reached.
Does not change.

This embodiment has the advantage that the number of word lines WL is halved compared to the semiconductor memory device A shown in FIG. 1, but has the following disadvantages. That is, in the semiconductor memory device A, the transistors Q1 and Q2 may be transistors of the same conductivity type, whereas in the semiconductor memory device C, the transistors Q1 and Q2 must be P-channel MO.
It is necessary to make a pair of an S transistor and an N channel MOS transistor. In the semiconductor memory device A, the characteristics of the write transistor Q1 and the read transistor Q2 can be set independently, but in the semiconductor memory device C, the write transistor Q1 is set.
Since the gate of No. 1 and the back gate of the read transistor Q2 are connected together, the characteristics of the write transistor Q1 and the read transistor Q2 cannot be set independently, and the characteristics of both are weak.

[Embodiment 5] FIG. 6 is a partially omitted circuit block diagram showing a structure of a semiconductor memory device D according to a fifth embodiment of the present invention. This semiconductor memory device D is the same as the semiconductor memory device C shown in FIG.
L2 and read bit lines BL1 'and BL2' are made common. That is, the semiconductor memory device D omits the write bit lines BL1 and BL2 in the semiconductor memory device C, and sets the source of the write transistor Q1 of each memory cell MC to the read bit line BL1 ′ or BL of that memory cell column.
It is connected to 2 '. As described in the third embodiment, the write bit lines BL1 and BL2 and the read bit lines BL1 ′ and BL are written unless the data is written to the memory cells MC of the same memory cell column during the reading of the data of the memory cells MC.
There is no problem even if 2'is shared.

In this embodiment, the number of word lines WL, WL 'and bit lines BL, BL' is halved compared to the semiconductor memory device A shown in FIG. 1, which is advantageous for integration.

[Sixth Embodiment] FIG. 7 is a circuit block diagram showing a structure of a semiconductor memory device E according to a sixth embodiment of the present invention with a part thereof omitted. This semiconductor memory device E is a memory that is adjacent to the semiconductor memory device A shown in FIG. It is connected to the storage node SN of the cell MC.

More specifically, this semiconductor memory device E
Is a plurality of memory cells MC arranged in rows and columns.
(Abbreviated to 3 rows and 2 columns in the figure.). The source of the write transistor Q1 of the first memory cell MC11 in the first column is the second memory cell MC12 in the column.
Storage node SN of the second memory cell MC12 and the source of the write transistor Q1 of the second memory cell MC12 is the storage node S of the third memory cell MC13 of the column.
The source of the write transistor Q1 of the third memory cell MC13 connected to N is connected to the write bit line BL1 provided corresponding to the column. The same applies to the second column. Since the other configurations are the same as those of the semiconductor memory device A, description thereof will be omitted. When writing data, first, for example, the write bit line BL1 is applied with the potential VH or VL to be written to the storage node SN of the first memory cell MC11, and then the write word lines WL1, WL2.
Memory cells MC11 and MC1 are boosted by boosting WL3 at the same time.
2, the write transistor Q1 of MC13 is turned on, then only the write word line WL1 is stepped down, and the memory cell MC
The write transistor Q1 of 11 is turned off. Thereby, the storage node SN of the first memory cell MC11
The writing to is completed. Next, the write bit line BL1 is set to the second
The potential VH or VL to be written to the th memory cell MC12 is applied, the write word line WL2 is stepped down, and the write transistor Q1 of the memory cell MC12 is turned off. This completes the writing of data to the storage node SN of the second memory cell MC12. Finally, the write bit line BL1 is set to the potential VH or VL to be written in the storage node SN of the third memory cell MC13,
The write word line WL3 is stepped down to turn off the write transistor Q1 of the memory cell MC13. This completes the writing to the storage node SN of the third memory cell MC13. Since the data reading is the same as that of the semiconductor memory device A shown in FIG. 1, description thereof will be omitted.

In this embodiment, the semiconductor memory device A
Write transistor Q of all memory cells MC as
Since it is not necessary to connect the source of 1 to the write bit line BL, it is very advantageous for miniaturization. However, for example, the first
When data is written again to the first storage node SN of the column, the write word lines WL1, WL2, WL3 are boosted to not only the first memory cell MC but also the second and third memory cells. Since the write transistors Q1 of MC12 and MC13 must also be turned on, the second and third memory cells MC12 and MC1 are left as they are.
The potential VH or VL of the storage node SN3 of 3 disappears. Therefore, before boosting the write word lines WL2, WL3, the second and third memory cells MC
12, it is necessary to read the potential VH or VL of the storage node SN of MC13 and store it somewhere. Therefore, with respect to the writing operation, the randomness is obstructed, or the writing becomes slower if the randomness is maintained. However, since reading is not affected at all, access is not delayed.

[Embodiment 7] FIG. 8 is a circuit block diagram, partially omitted, showing the structure of a semiconductor memory device F according to a seventh embodiment of the present invention. In this semiconductor memory device F, the source of the read transistor Q2 of the memory cell MC forming the memory cell column in the semiconductor memory device A shown in FIG. 1 is connected to the read transistor Q2 of the memory cell MC adjacent in one direction.
It is connected to the drain of.

Explaining in detail, this semiconductor memory device F
Is a plurality of memory cells MC arranged in rows and columns.
(Abbreviated to 2 rows and 2 columns in the figure). The source of the read transistor Q2 of the first memory cell MC11 in the first column is the second memory cell MC12 in the column.
Connected to the drain of the read transistor Q2, and the source of the read transistor Q2 of the second memory cell MC12 is connected to the sense amplifier S / A via the read bit line BL1 '.
Connected to 1. The read bit line BL1 'is connected to the precharge line PCL via the transistor QB1. The same applies to the second column. Since the other configurations are the same as those of the semiconductor memory device A, description thereof will be omitted.

In the standby state, the read transistors Q2 of all the memory cells MC set the potentials of the read word lines WL1 'and WL2' so that they are always turned on regardless of the potentials VH and VL of the storage node SN. Keep it.

When writing data, as in the semiconductor memory device A shown in FIG. 1, the potentials of the write bit lines BL1 and BL2 and the write word lines WL1 and WL2 are changed to store the data in each memory cell MC. The high potential VH or the low potential VL is written in the node SN.

When reading data, for example, the potential of the read word line WL1 'is changed, and if the storage node SN is at the high potential VH, the read transistor Q2 is turned on,
If the storage node SN is lower than the low potential VL, the potential is set so that the read transistor Q2 is not turned on. As a result, the conduction state of the read transistor Q2 changes according to the potential VH or VL of the storage node SN. Since the other read transistor Q2 connected in series is in the ON state, it serves as a mere wiring. Therefore,
The transistor QB1 is turned on to turn on the sense amplifier S / A1.
By detecting the current flowing through the memory cell MC11, the potential written in the storage node SN of the first memory cell MC11 in the first column can be read.

In this embodiment, the semiconductor memory device A
Since it is not necessary to connect the sources of all the read transistors Q2 to the read bit lines BL1 'and BL2' in that column, it is advantageous for miniaturization and the process is simplified. However, since the channel of the read transistor Q2 is used as a wiring, it is necessary to increase the conductance of the read transistor Q2.

[Embodiment 8] FIG. 9 is a partially omitted circuit block diagram showing a structure of a semiconductor memory device G according to an eighth embodiment of the present invention. This semiconductor memory device G is provided with a ferroelectric capacitor CS between the write transistor Q1 of each memory cell MC of the semiconductor memory device A shown in FIG. 1 and the storage node SN.

When writing data, first, for example, read bit line BL1 'is set to 0V, write bit line BL1 is set to positive potential + VH or negative potential -VH, and then write word line WL1 is boosted. Write transistor Q1
Turn on. At this time, some voltage is applied to the ferroelectric layer of the ferroelectric capacitor CS, and this voltage causes polarization inversion in the ferroelectric layer to cause an appropriate amount of spontaneous polarization. The polarization direction of the ferroelectric layer is either positive or negative depending on the potential + VH or -VH applied to the write bit line BL1, and therefore, a binary signal is represented by these two polarization directions. The write transistor Q1 is turned off to complete the data writing.

To read data, first, write bit line BL1 is set to 0 V, for example, and then write word line WL1.
Is turned on to turn on the write transistor Q1. Then, the storage node SN in the floating state has a positive or negative potential depending on the polarization direction of the ferroelectric capacitor C. Then, the transistor QB1 is turned on to precharge the potential of the read bit line BL1 'to the potential of the judgment standard. After turning off the transistor QB1, the potential of the read word line WL1 ′ is lowered so that the read transistor Q2 is turned on when the storage node SN is at a positive potential, and the read transistor Q2 is turned on when the storage node SN is at a negative potential. Set the potential to turn off. The sense amplifier S / A1 detects the conduction state of the read transistor Q2,
The polarization state of the ferroelectric capacitor CS is determined.

In this embodiment, since the data is recorded by utilizing the polarization of the ferroelectric capacitor CS, the data will not be volatilized. Therefore, it is not necessary to refresh data as in the conventional semiconductor memory device H.

[0058]

As described above, according to the first semiconductor memory device of the present invention and the method of writing and reading data in the semiconductor memory device, the first or second potential representing a binary signal is provided. A memory cell including a storage node for holding a memory cell, a write transistor, and a read transistor is provided, and the potential of the storage node is converted into a conductive state of the read transistor for reading. Therefore, even when the miniaturization of the memory cell is advanced, As described above, it is possible to reliably read the data without causing the shortage of the charge amount at the time of reading the data.

According to the second semiconductor memory device of the present invention and the method of writing and reading data in the semiconductor memory device, the ferroelectric is polarized to the first or second state representing a binary signal. A memory cell including a body capacitor, a write transistor, and a read transistor is provided, and the polarization state of the ferroelectric capacitor is converted into the conductive state of the read transistor for reading, so that even if the memory cell is miniaturized, the conventional As described above, it is possible to reliably read the data without causing the shortage of the charge amount at the time of reading the data. Further, since the binary signal is converted into the polarization state of the ferroelectric capacitor and stored, the stored data does not volatilize.

[Brief description of drawings]

FIG. 1 is a semiconductor memory device A according to a first embodiment of the invention.
3 is a circuit block diagram showing the configuration of FIG.

FIG. 2 is a memory cell M of the semiconductor memory device A shown in FIG.
It is a partially broken sectional view showing a specific structure of C.

FIG. 3 is a partially cutaway sectional view showing a specific structure of a memory cell MC ′ of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a semiconductor memory device B according to a third embodiment of the present invention.
3 is a circuit block diagram showing the configuration of FIG.

FIG. 5 is a semiconductor memory device C according to a fourth embodiment of the present invention.
3 is a circuit block diagram showing the configuration of FIG.

FIG. 6 is a semiconductor memory device D according to a fifth embodiment of the present invention.
3 is a circuit block diagram showing the configuration of FIG.

FIG. 7 is a semiconductor memory device E according to a sixth embodiment of the present invention.
3 is a circuit block diagram showing the configuration of FIG.

FIG. 8 is a semiconductor memory device F according to a seventh embodiment of the present invention.
3 is a circuit block diagram showing the configuration of FIG.

FIG. 9 is a semiconductor memory device G according to an eighth embodiment of the present invention.
3 is a circuit block diagram showing the configuration of FIG.

FIG. 10 is a partially omitted circuit block diagram showing a configuration of a conventional semiconductor memory device H.

[Explanation of symbols]

 1 Silicon Substrate 6 Silicon Thin Film 7 Back Gate 8 Insulating Film A to G Semiconductor Memory Device MC Memory Cell SN Storage Node Q1 Write Transistor Q2 Read Transistor CS Ferroelectric Capacitor BL Write Bit Line BL 'Read Bit Line WL Write Word Line WL 'Read word line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/10 451 7210-4M

Claims (13)

[Claims] 1. A semiconductor memory device comprising a plurality of memory cells arranged in rows and columns and capable of reading and writing data, wherein the memory cell holds a first or second potential representing a binary signal. A storage node having a first electrode connected to the storage node and a second electrode connected to the storage node.
A write transistor to which the first or second potential is applied to an electrode of the first electrode and a write command signal for instructing the writing of the binary signal to the storage node is input to its control electrode; A control electrode is connected to the storage node, and first and second electrodes thereof are connected to a conduction state detecting means for detecting a conduction state between the first and second electrodes,
A semiconductor memory device, comprising: a read transistor to which a read command signal for commanding the reading of the binary signal written in the storage node is input to the second control electrode. 2. A semiconductor memory device comprising a plurality of memory cells arranged in rows and columns and capable of reading and writing data, wherein the memory cells are polarized in a first or second state representing a binary signal. A ferroelectric capacitor having a first electrode connected to one electrode of the ferroelectric capacitor, and a second electrode for polarizing the ferroelectric capacitor to the first or second state. A write transistor to which a first or second potential is applied, and a write command signal for instructing the writing of the binary signal to the ferroelectric capacitor is input to a control electrode thereof, and a first control thereof. An electrode is connected to the other electrode of the ferroelectric capacitor, and its first and second electrodes are connected to a conduction state detecting means for detecting a conduction state between the first and second electrodes, 2 control Characterized in that it comprises a read transistor reading instruction signal for instructing the readout of the binary signals written in said ferroelectric capacitor electrode is inputted, the semiconductor memory device. 3. The write transistor is a bulk transistor formed on a semiconductor substrate, and the read transistor is a thin film transistor formed above the read transistor in an insulated manner. 2. The semiconductor memory device according to 2. 4. The semiconductor memory device according to claim 3, wherein the second control electrode of the read transistor is provided directly on the channel region of the read transistor or via an insulating film. 5. The semiconductor memory device according to claim 4, wherein the insulating film has a film thickness equal to or less than that of the gate insulating film. 6. A write word line and a read word line provided corresponding to each memory cell row, and a write bit line and a read bit line provided corresponding to each memory cell column, The control electrode of the write transistor of each memory cell forming each memory cell row is connected to the write word line, and the second control electrode of the read transistor of each memory cell forming each memory cell row is read out. The second electrode of the write transistor of each memory cell connected to the word line and forming each memory cell column is connected to the write bit line, and the read transistor of each memory cell forming each memory cell column is connected. 6. The semiconductor memory device according to claim 1, wherein the second electrode of is connected to the read bit line. 7. A write word line and a read word line provided corresponding to each memory cell row, and a write bit line and a read bit line provided corresponding to each memory cell column, The control electrode of the write transistor of each memory cell forming each memory cell row is connected to the write word line, and the second control electrode of the read transistor of each memory cell forming each memory cell row is read out. The second electrode of the write transistor of each memory cell, which is connected to the word line and constitutes each memory cell column, is connected to the storage node of the memory cell adjacent in one direction, and the memory cell at the end in one direction is written. A second electrode of the transistor is connected to the write bit line, and a second electrode of the read transistor of each memory cell forming each memory cell column is connected to the read bit line. It characterized Rukoto The semiconductor memory device according to any one of claims 1 to 5. 8. A write word line and a read word line provided corresponding to each memory cell row, and a write bit line and a read bit line provided corresponding to each memory cell column, The control electrode of the write transistor of each memory cell forming each memory cell row is connected to the write word line, and the second control electrode of the read transistor of each memory cell forming each memory cell row is read out. A second electrode of a write transistor of each memory cell that is connected to a word line and that configures each memory cell column is connected to the write bit line; The second electrode is connected to the first electrode of the read transistor of the memory cell adjacent in one direction, and the second electrode of the read transistor of the memory cell at the one direction end is connected to the read bit. Characterized in that it is connected to line, the semiconductor memory device according to any one of claims 1 to 5. 9. A write word line and a read word provided corresponding to each memory cell row, and a write bit line and a read bit line provided corresponding to each memory cell column, each of said The control electrode of the write transistor of each memory cell forming the memory cell row is connected to the write word line, and the second control electrode of the read transistor of each memory cell forming each memory cell row is the read word. A second electrode of the write transistor of each memory cell forming each memory cell column is connected to a storage node of a memory cell adjacent in one direction, and the write transistor of the memory cell at one end is connected. The second electrode of the read transistor of the memory cell forming each memory cell column is connected to the write bit line and the second electrode of the read transistor of the memory cell adjacent in one direction. 6. The read electrode according to claim 1, wherein the read electrode is connected to the first electrode of the transistor and the second electrode of the read transistor of the memory cell at one end is connected to the read bit line. Semiconductor memory device. 10. The semiconductor memory device according to claim 6, wherein the write bit line and the read bit line are commonly used. 11. The write transistor and the read transistor are transistors having different conductivity types from each other, and the write word line and the read word line are commonly used. The semiconductor memory device according to any one of 1. 12. A storage node holding a first or second potential representing a binary signal, and a first electrode thereof connected to the storage node, and a second node thereof.
A write transistor to which the first or second potential is applied to an electrode of the first electrode and a write command signal for instructing the writing of the binary signal to the storage node is input to its control electrode; A control electrode is connected to the storage node, and first and second electrodes thereof are connected to a conduction state detecting means for detecting a conduction state between the first and second electrodes,
Writing data in a semiconductor memory device including a memory cell including a read transistor to which a read command signal for instructing the reading of the binary signal written in the storage node is input to the second control electrode, and A read method, wherein the first or second potential is applied to the second electrode of the write transistor, and the write command signal is output to the control electrode of the write transistor to output the storage node. To hold the first or second potential, output the read command signal to the second control electrode of the read transistor to change the threshold value of the read transistor, and detect by the conduction state detecting means. A method of writing and reading data in a semiconductor memory device, characterized in that the potential of the storage node is determined from the conductive state between the first and second electrodes. 13. A ferroelectric capacitor polarized to a first or second state that represents a binary signal, a first electrode of which is connected to one electrode of the ferroelectric capacitor, and a second electrode of which is connected. A first or second potential for polarizing the ferroelectric capacitor to the first or second state is applied, and its control electrode is instructed to write the binary signal to the ferroelectric capacitor. A write transistor to which a write command signal is input, a first control electrode of which is connected to the other electrode of the ferroelectric capacitor, and a first and second electrodes of which are connected between the first and second electrodes. Is connected to a conduction state detecting means for detecting the conduction state of the above, and a reading command signal for instructing the reading of the binary signal written in the ferroelectric capacitor is input to the second control electrode thereof. With a transistor A method of writing and reading data in a semiconductor memory device including a memory cell, comprising: applying the first or second potential to the second electrode of the write transistor, The write command signal is output to a control electrode to polarize the ferroelectric capacitor to the first or second state, and the read command signal is output to the second control electrode of the read transistor to output the read command signal. A semiconductor device characterized in that the threshold value of the read transistor is changed, and the polarization state of the ferroelectric capacitor is judged from the conduction state between the first and second electrodes detected by the conduction state detecting means. A method of writing and reading data in a storage device.