JP2001103386A - Digital broadcast receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital broadcast receiver that can reduce a capacity of its memory and time required for decoding. SOLUTION: The digital broadcast receiver is provided with a memory 1001 for interleave decoding and an equal space calculation device 1002 that calculates an equal space in a frame period on the basis of a total number of in-frame packets to which a number coincident with an externally designated number is assigned during a period of a data write to the interleave memory 100 that is conducted for interleave decoding. In data read from the interleave memory 1001, read addresses of the interleave memory are skipped in the unit of packets only for packets selected and distributed in a frame and the packets are read at an equal space within the frame period so as to conduct interleave decoding and uniform output of the packets in the frame period altogether.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a configuration of a digital broadcast receiving apparatus for receiving a digital satellite broadcast.

[0002]

2. Description of the Related Art [Transmission frame configuration] In a data compression method such as MPEG2, a transport stream TS that can cope with an environment having an error is defined. In BS digital broadcasting, transmission using this TS packet is performed.

FIG. 8 is a schematic block diagram for explaining a configuration of a transmission signal of a BS digital broadcast.

Referring to FIG. 8, in BS digital broadcasting,
A broadcast from a satellite is transmitted using a superframe composed of eight frames as one unit.

[0005] The frame further includes a synchronization signal, a transmission multiplex control signal (hereinafter referred to as a TMCC signal) (Transmission & Multi
tiplexing Configuration Control: Includes parity) and main signals. The main signal is MPEG
The system is basically configured, and one frame includes 48 (slot) MPEG-TSs (Transport Streams). Here, a plurality of MPEG-TSs can be transmitted up to eight. Any number from 0 to 7 is assigned to MPEG-TS.

As a modulation method, BPSK (Binary Phase Shift Keying) is applied to the synchronization signal and the TMCC signal.
Modulation is used. The main signal mainly uses 8PSK modulation, but 8PSK and QPSK (Quadrature Pha
se Shift Keying) and BPSK modulation can be mixed.

[0007] The transmission signal content is such that the main signal is video, audio,
This is a data signal, and the TMCC signal contains information necessary for signal processing of a main signal such as a modulation method.

[0008] A convolutional code is applied to the synchronization signal, the TMCC signal, and the main signal as an error correction code. TMCC
In addition to the convolutional code, a Reed-Solomon (RS) code using only the TMCC signal portion is added to the signal as parity. Although not shown, a Reed-Solomon (RS) code using only the main signal portion is similarly added as a parity to the main signal portion in addition to the convolutional code.

The main signal includes 48 slots as described above, and each slot includes a transport stream (eg, 188 bytes) added with a Reed-Solomon error correction code (eg, 16 bytes) to an MPEG signal packet (eg, 188 bytes). TS), and this TS is a unit for selecting a modulation method. This frame is a basic transmission unit of transmission path coding, and signal processing is performed in units of 8 frames (superframes) for interleaving of a main signal, energy spreading, and transmission coding of a TMCC signal. That is, for example, a PN sequence for the energy spreading process is initialized at the beginning of each superframe.

FIG. 9 is a conceptual diagram for explaining the structure of a TMCC signal. As shown in FIG. 9, the TMCC signal includes a change instruction for notifying that the modulation scheme of the main signal changes, a transmission mode / slot information for notifying the modulation scheme such as an 8PSK modulation scheme, and 0-7.
Relative TS / slot information indicating how a plurality of MPEG-TSs (hereinafter referred to as a plurality of TSs) each of which is associated with one of the above numbers is assigned to a slot, an absolute TS number corresponding to a relative TS number simply assigned , A control signal for notifying the presence or absence of an emergency broadcast, an uplink control signal used by a broadcasting station, spare extension information, and an RS code (not shown) as a parity code. I have.

FIG. 10 is a conceptual diagram showing a procedure from the TS packet multiplexing to the frame configuration. On the other hand, FIG.
FIG. 3 is a conceptual diagram showing a lapse of time of interleaving readout performed between frames.

As described above, each slot has a length of 204 bytes and has a TMCC signal to enable transmission of a plurality of TSs and control of each slot. It corresponds to the period of energy spreading and interleaving.

In transmitting a frame signal, a frame synchronization signal and a TMCC signal are first transmitted collectively (192 symbols), and thereafter, when a plurality of modulation methods are transmitted on the same carrier, TC8PSK, QPSK and BPSK are used. In the order of signals modulated by the modulation method having a large number of phases, and in QPSK, each piece of information is arranged in a frame from slot numbers 1 to 48 in order of coding rate and transmitted. The assignment of each signal is as follows.

(1) The signal for TC8PSK is one slot unit. (2) A QPSK signal having a coding rate of n / m is allocated in units of m slots, and the information that can be transmitted is n slots. Information is not allocated to the (mn) slot as a dummy slot.

(3) Signals for BPSK (r = 1/2) are allocated in units of four slots, of which three slots are dummy slots.

(4) When a plurality of schemes requiring a dummy slot are used, an effective slot is first placed in an assigned slot of a unit.

In such a configuration, in order to ensure flexibility and expandability in transmission coding, a frame structure composed of 48 slots (each slot is 204 bytes long) is used, a plurality of TS transmissions and a Control (TS
TM, selection of modulation method, etc.)
A CC signal is provided.

After the timing of each TS is adjusted and rearranged, Reed-Solomon (204, 188) encoding
A slot is created by adding a 16-byte arrangement signal, and transmission scrambling is performed using an energy spread signal.

Thereafter, a frame is formed in slot units (48 slots) having a fixed period, and the frame synchronization signal and the TMCC signal are replaced with the first byte for each frame.

According to this method, it is possible to allocate data for each of a plurality of TSs for each of a plurality of slots in a frame configuration, and the communication device uses a TMCC signal to assign a single TS from among a plurality of TSs. You can choose.

The modulation scheme of each slot may not be constant, and modulation such as QPSK can be selected in addition to TC8PSK for each of a plurality of slot groups.
The receiver can automatically demodulate by transmitting with the CC signal.

In addition, except for the signal for TC8PSK, a signal for each modulated wave is inserted with a dummy slot to make the clock for frame processing constant.

FIG. 12 is a conceptual diagram showing an example of such slot allocation. The number of slots is determined so that each slot can be efficiently allocated for a 1/2 repeater. That is, a slot unit (m = 2, 3, 4, 6, 6) at a coding rate that can be obtained by QPSK modulation
The minimum common multiple of 24 (8 slots) is 24.

[Transmission scrambling] (1) Interleave method The main signal has a block interleave configuration of 8 × 203 bytes, and interleave is performed for each slot in the superframe direction.

That is, the i-th (i: natural number) slots of 1 to 8 frames are collectively interleaved, and return to the i-th slot of each frame in 1/8 cycle. FIG. 13 is a conceptual diagram showing the structure of block interleaving.

In general, there are two types of interleaving methods, block interleaving and convolutional interleaving. A sufficient effect can be obtained in units of 8 slots, and interleaving is performed for each same slot in the superframe direction. In the above-described configuration, the block interleave scheme is adopted because the interleave for each different modulation scheme can be controlled without depending on the frame structure.

(2) Energy Spreading Method A pseudo random signal generated by the 15th M-sequence in the superframe period from the second byte from the head of each superframe is added to each data. However, while the first byte of each slot does not perform energy spreading, the generation of the pseudo random signal is continued during this time. Also, TC8PSK
In other modulation schemes, spreading processing including a necessary dummy slot portion is performed.

Therefore, when the transport stream TS encoded by the above-described transmission frame configuration is decoded by performing the encoding process in the reverse order, the interleaving, energy spreading, Reed-Solomon decoding, and TS packet equalization are performed. A configuration for performing output and the like is required.

In this case, it is necessary to store the data once in a memory or the like because the speed change is involved in performing the TS packet equal output, and when performing the processing in the above order, the interleave memory and the TS packet equal Requires separate memory from output memory.

FIG. 14 is a schematic block diagram showing a configuration of a digital receiver (STB) 2000 for receiving a conventional BS digital broadcast.

As shown in FIG. 14, a digital receiver 2000 for receiving a BS digital broadcast has the following main components.
A tuner 1 for frequency-converting an RF input signal into a baseband signal, a link IC 2 for receiving the output of the tuner 1 and performing digital demodulation and decoding processing, and receiving an output from the link IC 2 for an MPEG video or audio signal. It comprises an MPEG processing unit 3 for decoding and extracting a data signal, and a CPU 4 for controlling the operation of the digital receiver 2000.

The link IC 2 is added on the transmitting side, with a PSK demodulation unit 6 for demodulating any one of 8PSK to BPSK of a modulation scheme specified by the TMCC signal, a synchronization detection unit 11 for detecting a frame synchronization signal, and a transmission side. Viterbi decoder 7 that performs error correction on the transmission side using the convolutional code
And a signal processing unit 8 for performing deinterleaving and de-randomizing (energy despreading processing) of the main signal, and an RS code decoding unit for performing error correction of a transmission path using an RS code added to the main signal on the transmission side. 9, a TS selecting unit 10 for selecting a desired MPEG-TS from a plurality of TSs according to a designated number given from the outside, a TMCC signal processing unit 12 for integrating TMCC signals divided and transmitted over eight frames. , An RS decoding unit 13 that performs error correction using an RS code added exclusively for the TMCC signal,
A TMCC register 14 for holding the content of the CC;
A CPU I / F unit 15 is provided for performing data interface processing between the C register 14 and the CPU 4.

FIG. 15 is a schematic block diagram for explaining the configurations of the signal processing unit 8, the RS code decoder 9, and the TS selection unit 10.

The input data from the Viterbi decoding unit 7 is stored in an interleave memory 2010 in the signal processing unit 8 in accordance with an address controlled by an interleave memory write address calculator 2070.
The data is read from the interleave memory 2010 in accordance with the address controlled by the interleave memory read calculator 2060 which receives a designated number from 0 to 7 as an input.

With such an operation, the interleaved data is read out in the order before the interleaving.

Subsequently, the data read from the interleave memory 2010 is composed of the pseudo random data generated by the PN sequence generator 2020 and the PN sequence adder 203.
0 is added, and energy despreading processing is performed.

After the output of the PN sequence adder 2030 is decoded by the Reed-Solomon (RS) code decoder 9, the TS selection in the TS selector 10 is performed in accordance with the address controlled by the write address calculator 2080. Memory 2
Written during 050.

The data written in the TS selection memory 2050 has a designated number in accordance with the output address from the memory read address calculator 2100 based on the equal output interval calculated by the equal output interval calculator 2090. Based on the selection of the MPEG-TS, the TS selection memory 20
By reading the data from 50, data output at equal time intervals can be obtained.

[0039]

That is, in the conventional satellite digital broadcast receiving apparatus 2000, a separate memory is required from an interleave memory and a memory for TS packet equal output, so that the circuit scale becomes large and the redundancy becomes large. Therefore, there is a problem that the time required for decoding is long.

The present invention has been made to solve the above problems, and has as its object to eliminate the need to prepare separate memories for interleaving and TS packet equal output, and to use only an interleaving memory. It is an object of the present invention to provide a digital broadcast receiving apparatus capable of reducing the memory for TS packet equal output and shortening the time required for decoding by also performing TS packet equal output.

[0041]

A digital broadcast receiving apparatus according to the present invention is divided into a plurality of frames and transmitted at a superframe period including a predetermined number of frames. And a digital broadcast receiving apparatus for receiving a transmission signal including a transmission multiplex control signal having an assignment number assigned to each packet.
The interleave memory for receiving and storing the transmission signal and decoding the interleave processing performed on the packet, and the specified number and the allocation number specified from the outside during the period of writing data to the interleave memory match. An equal interval calculating means for calculating an equal interval within the frame period from the number of packets in the frame; and a timing which is based on the equal interval within the frame period, and in the order in which the interleave processing is decoded, the selected interval exists in the frame. Read address calculating means for selectively reading packets from the interleave memory.

[0042] The digital broadcast receiving apparatus according to claim 2 is
In addition to the configuration of the digital broadcast receiving apparatus according to claim 1,
The transmission signal is P initialized at the beginning of the superframe.
Energy diffusion processing is performed by N code sequences,
PN code sequence generating means which operates during a super frame period including a data write period to the interleave memory to generate a PN code sequence, and a head data position of a plurality of packets selected according to a designated number in the super frame Storage means for sequentially storing the value of the PN code sequence from the PN code sequence generation means corresponding to the relative position each time the relative position from the head of the super frame is detected, and a plurality of the PN code sequences selected from the interleave memory. When packets are read out at equal intervals within the frame period,
Each time the leading data of the selected packet is read, the corresponding PN code sequence value is read from the storage means, and the corresponding PN code sequence value is set as the initial value in synchronization with the data reading from the interleave memory. A PN code sequence reproducing unit for reproducing the PN code sequence; and an adding unit for performing the energy diffusion decoding process by adding the data read from the interleave memory and the output from the PN code sequence reproducing unit. Prepare.

According to a third aspect of the present invention, there is provided a digital broadcast receiving apparatus.
In addition to the configuration of the digital broadcast receiving apparatus according to claim 2,
The PN code sequence generation means operates in synchronization with a clock higher than the operating frequency of the interleave memory, operates for a predetermined period at the rear of a superframe including a period in which data is written to the interleave memory, and And second PN sequence storage means, and the first and second P
The N-sequence storage means operates alternately at superframe intervals.

[0044]

FIG. 1 is a schematic block diagram showing the configuration of a digital broadcast receiving apparatus 1000 according to an embodiment of the present invention.

The configuration of digital broadcast receiving apparatus 1000 is different from that of conventional digital broadcast receiving apparatus 2000 shown in FIG. 14 in that signal processing section 8 is replaced by signal processing section 100 and TS selecting section 10 is omitted. The point is that it has a configuration. For other configurations, the digital broadcast receiver 2
000, the same parts are denoted by the same reference characters, and description thereof will not be repeated.

FIG. 2 is a schematic block diagram showing a configuration of signal processing section 100 shown in FIG. The signal processing unit 100 receives data from the Viterbi decoding unit 7 and T
MCC information and a designation number from 0 to 7 are given.

Since the interleave decoding is performed in units of a superframe, data is written to the interleave memory 1001 during one superframe period, and at the same time, previously written data is output to the equal output interval calculator 1002. The reading is performed at the timing generated in step (1).

Here, FIG.
10 is a timing chart showing write and read access timings to 001. As shown in FIG. 3, write and read accesses to the interleave memory 1001 are sequentially performed without interruption.

Referring to FIG. 2 again, while data is being written to interleave memory 1001, uniform output interval calculator 1002 calculates an equal output interval according to the number of selected packets in the frame. You.

That is, the signal processing unit 100 shown in FIG.
Focuses on the fact that the block interleave, the TMCC change cycle, and the PN cycle are all performed in a superframe cycle, and attempts to perform interleave, PN decoding, and equivalent data output collectively.

Reading from the interleave memory 1001 is performed by the interleave memory read address calculator 1.
After calculating the address by 006, only the data of the selected packet is performed.

The read timing is performed based on the interval calculated by the equal output interval calculator 1002.

Thus, the interleave memory 100
1 can be output at equal intervals of intra-frame data.

While data is being written to the memory, the total number of effective slots in the frame structure is calculated from the contents of the TMCC, and the interval value for jumping the memory address for performing the equal output is output uniformly. The interval calculator 1002 will calculate.

By performing data output while performing address jumps at the time intervals calculated by the equal output interval calculator 1002, the interleave memory 1
That is, it is possible to perform equal output from 001.

That is, the digital broadcast receiver 1000 according to the present invention comprises a memory 10 for interleave decoding.
01, during the period of writing data to the interleave memory 1001 for the interleave decoding, during the frame period, the total number of packets to which a number corresponding to the number specified from the outside is allocated within the frame. Equal interval calculator 1002 for calculating the interval
And In reading data from the interleave memory 1001, only selected packets scattered in a frame are read at an equal interval within the frame period while the read address to the interleave memory is jumped in packet units. , The interleave decoding and the equal output of the packet within the frame period are collectively performed.

Therefore, according to such a configuration, it is not necessary to prepare a new memory for packet selection after all the data in the frame is read, and the interleave decoding and the uniform output of the packet within the frame period are collectively performed. You can do it.

On the other hand, the PN sequence generator 1003 is reset at the head of the seventh frame in the super frame period, starts generating the PN sequence, and continues the operation during the period from 7 to 8 frames.

As the clock used in PN sequence generator 1003, a clock having a frequency four times the frequency of the byte clock is used. That is, the link memory 2 includes the read memory 10
For example, a byte clock for controlling a read / write operation such as 01 and a clock generation circuit (not shown) for generating a clock having a frequency four times higher than the byte clock are provided.

As a result, the operation can be performed in a period of ４ of the operation period originally required for the super frame period.

FIG. 4 shows the operation period of the PN sequence generator 1003. During the operation of PN sequence generator 1003, TM
By comparing the content of the CC with the designated number from the outside, the leading position of the selected packet is sequentially obtained from a total of 48 packets in each frame in the super frame, and the count of the operation clock of the PN sequence generator 1003 is calculated. When the number matches the start position of the selected packet,
The PN value of the PN sequence generator 1003 is stored in the PN storage memory 10.
Save to 04.

FIG. 5 shows the correspondence between the selected packet position in each frame and the PN sequence storage memory 1004.

The PN sequence reproducer 1005 operates at the same timing as the read timing of the interleave memory 1001.

Only the selected packet data is read from interleave memory 1001. The data corresponding to the head position of the selected packet is the interleave memory 1
When reading from 001, the PN value is retrieved from the PN storage memory 1004 and input to the PN sequence reproducer 1005.

The PN sequence regenerator 1005 receives the input P
The operation is started and continued again using the N value. Thus, the PN sequence is regenerated at the same timing as the data read from interleave memory 1001.

FIG. 6 is a timing chart showing the timing of reading the PN value from the PN sequence storage memory 1004. As described above, the PN sequence regenerator 1005
By starting and continuing the operation again using the input PN value, the PN sequence adder 1008
Read data from interleave memory 1001 and P
The PN value calculated by the N-sequence generator 2 is added, and PN
By performing the removal, the decoding process of the energy diffusion can be performed.

That is, the signal processing unit 100 performs the interleave decoding for the interleave decoding.
01, and a PN code sequence generator 1003 operating during a superframe period including a period during which data is written to the first frame from the head of the superframe at the head data position in a packet group within a frame selected by external number designation. The relative position is determined, and the PN corresponding to the relative position is determined.
A memory 1004 for storing the PN code sequence generated by the code sequence generator 1003.

The signal processing unit 100 operates the PN code sequence generation circuit 1003 during the period of writing data to the interleave memory 1001 for interleave decoding, and assigns a number that matches the number specified from the outside. When the PN code sequence approaches the same position as the head position of the packet, the PN code sequence storage memory 1
004 is stored in the interleave memory 100
When the head data of the packet in the packet data read from No. 1 is read, the PN value stored in the PN code sequence storage memory 1004 is read and input to the PN code sequence regenerator 1005, and the interleave memory 1001 is read. P at the same timing as the data read from
The N code sequence reproducing circuit is continuously operated, and the data read from the interleave memory and the PN value output from the PN code sequence reproducing circuit are added.

With such a configuration, a PN sequence which originally operates in a superframe cycle and in which it is difficult to instantaneously calculate a value in the middle of a period is used for a packet selected in a frame. Regardless, the reproduction of the PN sequence can be performed, and when there are consecutive packets to be selected, the P
Only the N value needs to be stored, and it is not necessary to store the PN values at the head of all the packets in the superframe, and the PN sequence can be removed from the data.

Here, as described above, the PN sequence generator 1003 operates at four times the speed of the byte clock, and its operation starts from the seventh frame. In this case, the contents of the PN storage memory 1004 for the eighth frame may be updated with the PN value from the PN sequence generator 1003 before the input to the PN sequence reproducer 1005 is performed.

For this reason, two sets of PN sequence storage memories 1004 corresponding to the eighth frame are prepared, and are used by switching in superframe units. Thus, the capacity of the PN sequence storage memory 1004 can be minimized.

FIG. 7 shows such a PN sequence storage memory 1.
9 is a timing chart showing an operation in which a writing period to 004 and a reading period overlap each other.

That is, the operation period of the PN sequence regenerator 8
In the frame, the eighth frame of the PN sequence generator operation period overlaps with each other. During this period, before data is input to the PN sequence reproducer 1005, P
The contents of the PN storage memory 1004 may be updated by the PN value from the N-sequence generator 1003.

As described above, there are two sets of PN storage memories, which are switched on a superframe basis, so that rewriting due to such unintended updating can be suppressed.

That is, in the satellite digital broadcast receiving circuit having the above configuration, when the PN code sequence generator 1003 operates, a super frame including a period in which data is written to the interleave memory is used by using a high-speed clock. It is prevented from being updated by the output of the PN code sequence generator 1003 before the contents of the PN code sequence storage memory 1004 are input to the PN code sequence regenerator 1005, and updating is unavoidable. Two systems of PN code series storage memories are provided corresponding to the period, and are controlled so as to be switched and used at superframe intervals.

According to this configuration, in a situation where writing and reading to the interleave memory are always performed, P
It is not always necessary to prepare all the N code sequence storage memories 1002 in two systems, but only two systems in which the storage and retrieval periods in the PN code sequence storage memory overlap are provided.

Therefore, the capacity of the PN code series storage memory can be reduced. In the present invention,
Although the digital broadcast receiving apparatus constituted by the link IC (LINK-IC) 2 has been described, the LINK-IC
And MPEG-IC, or LINK-IC and MPEG
-The IC and the CPU can be integrated into one IC.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0079]

As described above, according to the present invention,
Interleave decoding and data frame period equal output processing can be performed collectively using only the interleave memory, and there is no need to separately receive a memory for the frame period equal output processing, thereby reducing the time required for the decoder. Is possible.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a configuration of a digital broadcast receiving apparatus 1000 according to an embodiment of the present invention.

FIG. 2 is a schematic block diagram illustrating a configuration of a signal processing unit 100 illustrated in FIG.

FIG. 3 is a timing chart showing write and read access timings to an interleave memory 1001.

FIG. 4 is a timing chart showing an operation period of the PN sequence generator 1003.

FIG. 5 is a timing chart showing a correspondence between a selected packet position in each frame and a PN sequence storage memory 1004.

FIG. 6 is a timing chart showing the timing of reading a PN value from a PN sequence storage memory 1004.

FIG. 7 is a timing chart showing an operation in which writing and reading periods in the PN series storage memory 1004 overlap.

FIG. 8 is a schematic block diagram illustrating a configuration of a transmission signal of a BS digital broadcast.

FIG. 9 is a conceptual diagram for explaining a configuration of a TMCC signal.

FIG. 10 is a conceptual diagram showing a procedure from TS packet multiplexing to a frame configuration.

FIG. 11 is a conceptual diagram showing a lapse of time of interleaving readout performed between frames.

FIG. 12 is a conceptual diagram showing an example of allocation of each slot.

FIG. 13 is a conceptual diagram showing a structure of block interleaving.

FIG. 14 is a schematic block diagram illustrating a configuration of a digital receiver (STB) 2000 for receiving a conventional BS digital broadcast.

FIG. 15 is a schematic block diagram illustrating a configuration of a signal processing unit 8, an RS code decoder 9, and a TS selection unit 10.

[Explanation of symbols]

1000 digital broadcast receiver, 1001 interleave memory, 1002 equal output interval calculator, 100
3 PN sequence generator, 1004 PN sequence storage memory,
1005 PN sequence regenerator, 1006 interleave memory read address calculator, 1007 interleave memory write address calculator, 1008 PN sequence adder.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hiroshi Nakajima 2-5-2-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. F-term (reference) 5C025 BA27 DA01 DA04 5C059 KK08 MA00 RB02 RB10 RD07 RF05 SS02 UA36 5C064 DA02 DA03 5K004 AA05 FA05 FA06 FH06 5K028 BB05 EE08 FF13 KK11 LL13 MM06 RR02 SS24

Claims (3)

[Claims] 1. A transmission that is divided into a plurality of frames and is transmitted in a superframe period including a predetermined number of the frames, and includes, for each of the frames, a plurality of packets and an assignment number assigned to each of the packets. A digital broadcast receiving apparatus for receiving a transmission signal including a multiplex control signal, an interleave memory for receiving and storing the transmission signal and decoding an interleave process performed on the packet, During the period of writing data to the memory,
An equal interval calculating means for calculating an equal interval within a frame period from the number of packets in the frame in which the assigned number matches the assigned number specified from the outside, and at a timing based on the equal interval within the frame period, and A digital broadcast receiving apparatus, comprising: read address calculating means for selectively reading selected packets present in the frame from the interleave memory in the order of decoding the interleave processing. 2. The transmission signal has been subjected to an energy spreading process by a PN code sequence initialized at the beginning of the superframe, and operates during the superframe period including a data writing period to the interleave memory. A PN code sequence generating means for generating a PN code sequence; and detecting, in the superframe, a relative position from a head of the superframe of a head data position of a plurality of packets selected according to the designated number. Storage means for sequentially storing the value of the PN code sequence from the PN code sequence generation means corresponding to the relative position; and wherein the plurality of packets selected from the interleave memory are stored in the frame period. When read at equal intervals, the leading data of the selected packet is read. Each time the corresponding PN code sequence value is read from the storage means, and the PN code sequence is reproduced using the corresponding PN code sequence value as an initial value in synchronization with data reading from the interleave memory. Code reproducing means for reading data from the interleave memory and the PN code sequence
2. The digital broadcast receiving apparatus according to claim 1, further comprising an adding unit for performing an energy spreading decoding process by adding an output from the code sequence reproducing unit. 3. The PN code sequence generating means operates in synchronization with a clock higher than an operating frequency of the interleave memory, and operates for a predetermined period at a rear part of a superframe including a period during which data is written to the interleave memory. The digital broadcast according to claim 2, wherein the storage unit includes first and second PN sequence storage units, and wherein the first and second PN sequence storage units operate alternately at the superframe interval. Receiver.