JP2001094379A - Ceramic base, piezoelectric device and piezoelectric oscillator - Google Patents

Ceramic base, piezoelectric device and piezoelectric oscillator

Info

Publication number
JP2001094379A
JP2001094379A JP26674099A JP26674099A JP2001094379A JP 2001094379 A JP2001094379 A JP 2001094379A JP 26674099 A JP26674099 A JP 26674099A JP 26674099 A JP26674099 A JP 26674099A JP 2001094379 A JP2001094379 A JP 2001094379A
Authority
JP
Japan
Prior art keywords
bottom wall
ceramic base
wall
piezoelectric
frame wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26674099A
Other languages
Japanese (ja)
Inventor
Chisato Ishimaru
千里 石丸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nihon Dempa Kogyo Co Ltd
Original Assignee
Nihon Dempa Kogyo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nihon Dempa Kogyo Co Ltd filed Critical Nihon Dempa Kogyo Co Ltd
Priority to JP26674099A priority Critical patent/JP2001094379A/en
Publication of JP2001094379A publication Critical patent/JP2001094379A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Oscillators With Electromechanical Resonators (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a ceramic base for constantly securing a seal path though the deviation of a cover position with respect to a ceramic base occurs and a piezoelectric device, a quartz oscillator in particular, satisfactorily maintaining reliability and oscillation characteristic through the use of this. SOLUTION: (1) In a ceramic base which is obtained by laminating a bottom wall and a frame wall and holds a piezoelectric piece on the bottom wall and where a cover is connected to the upper surface of the frame wall with a sealing material, the outline of the frame wall is made smaller than that of the bottom wall. (2) In a piezoelectric device consisting of the ceramic base obtained by laminating the bottom wall and the frame wall, a piezoelectric piece held on the bottom wall and a cover connected with the upper surface of the frame wall with the sealing material, outline of the frame wall is made smaller than that of the bottom wall. (3) In a piezoelectric device consisting of the ceramic base obtained by laminating the bottom wall and the frame wall, a piezoelectric piece held on the bottom wall and an IC chip housed in a recess part formed at the bottom wall and a cover connected with the upper surface of the frame wall with the sealing material, the outline of the frame wall is made smaller than that of the bottom wall.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はセラミックベース及
びこれに圧電片を収容してなる圧電装置特には圧電発振
器を産業上の技術分野とし、特に樹脂又はガラス等の封
止材によってセラミックベースの開口面にカバーを接合
されて密閉される表面実装型の水晶発振器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an industrial technical field of a ceramic base and a piezoelectric device having a piezoelectric piece housed therein, especially a piezoelectric oscillator. In particular, the opening of the ceramic base is formed by a sealing material such as resin or glass. The present invention relates to a surface mount type crystal oscillator which is hermetically sealed by joining a cover to a surface.

【0002】[0002]

【従来の技術】(発明の背景)圧電装置、例えば水晶発
振器は周波数及び時間の基準源として、通信機器を含む
各種の電子機器に広く使用されている。このようなもの
の一つに、セラミックベースにICチップ及び水晶片を
収容して、ガラスや樹脂等の封止材によってカバーを接
合したものがある。
2. Description of the Related Art Piezoelectric devices, for example, crystal oscillators, are widely used as various frequency and time reference sources in various electronic devices including communication devices. As one of such devices, there is a device in which an IC chip and a crystal piece are accommodated in a ceramic base and a cover is joined with a sealing material such as glass or resin.

【0003】(従来技術の一例)第6図は一従来例を説
明する水晶発振器の断面図である。水晶発振器はセラミ
ックベース1とICチップ2と水晶片3とカバー4とか
らなる。セラミックベース1は、第1と第2の底壁5
(ab)の焼成による積層体からなる。最下位層の第1
底壁5aは平板で、第2底壁5bは孔を有して、凹部6
を形成する。第1底壁5aの4隅には、表面実装用の図
示しない電極が延出する。ICチップ2は発振回路を構
成する素子を集積化してなり、凹部底面に例えばフェー
スダウンによって固着される。
FIG. 6 is a cross-sectional view of a crystal oscillator for explaining a conventional example. The crystal oscillator includes a ceramic base 1, an IC chip 2, a crystal piece 3, and a cover 4. The ceramic base 1 has first and second bottom walls 5.
It consists of a laminate obtained by firing (ab). First in the lowest layer
The bottom wall 5a is a flat plate, the second bottom wall 5b has a hole,
To form At four corners of the first bottom wall 5a, electrodes (not shown) for surface mounting extend. The IC chip 2 is formed by integrating elements constituting an oscillation circuit, and is fixed to the bottom of the recess by, for example, face-down.

【0004】水晶片3はICチップ2を覆って、図示し
ない励振電極から引出電極の延出した両端部が第2底壁
5bの表面に固着される。カバー4はセラミックベース
1より外形が小さく、凹状とする。ここでは、樹脂7が
開口端面に塗布される。そして、セラミックベース1
(第2底壁5b)の上面に、カバー4の開口端面を位置
決めし、樹脂を加熱溶融して接合する。なお、図中の符
号8はバンプ、同9は導電性接着剤である。
The crystal blank 3 covers the IC chip 2 and both ends of the extraction electrode extending from the excitation electrode (not shown) are fixed to the surface of the second bottom wall 5b. The outer shape of the cover 4 is smaller than that of the ceramic base 1 and is concave. Here, the resin 7 is applied to the opening end surface. And ceramic base 1
The opening end face of the cover 4 is positioned on the upper surface of the (second bottom wall 5b), and the resin is heated and melted and joined. In the drawings, reference numeral 8 denotes a bump, and reference numeral 9 denotes a conductive adhesive.

【0005】[0005]

【発明が解決しようとする課題】(従来技術の問題点)
しかしながら、上記構成の水晶発振器では、封止時にお
けるセラミックベース1に対するカバー4の許容誤差内
の位置ズレによって、次の問題を生じていた。すなわ
ち、セラミックベース1とカバー4との間に例えば左右
の位置ズレを生じた場合には、外側(左側)ではカバー
4の開口端面とセラミックベース1の表面との接合面の
幅、いわゆるシールパスWが小さくなる(第7図)。し
たがって、この場合には接合強度を悪化させたり、特に
樹脂封止では湿気が浸透しやすくなって耐湿性を低下さ
せたりして、信頼性に欠ける問題があった。
[Problems to be Solved by the Invention]
However, in the crystal oscillator having the above configuration, the following problem has occurred due to a positional deviation of the cover 4 with respect to the ceramic base 1 within an allowable error during sealing. That is, when, for example, left and right positional shifts occur between the ceramic base 1 and the cover 4, the width of the joint surface between the open end surface of the cover 4 and the surface of the ceramic base 1 on the outside (left side), a so-called seal path W Becomes smaller (FIG. 7). Therefore, in this case, there has been a problem that the bonding strength is deteriorated, and particularly in the case of resin encapsulation, moisture easily penetrates, and the moisture resistance is reduced, resulting in a lack of reliability.

【0006】また、内側(右側)では溶融した樹脂7が
水晶片3に付着して振動特性を劣化させるおそれもあっ
た(未図示)。このため、水晶片3を小さくする必要が
あり、設計の自由度を損う問題もあった。特に、これら
は小型になるほど顕著な問題となっていた。なお、許容
誤差を越えた位置ズレは外観不良となる。
Further, on the inner side (right side), there is a possibility that the molten resin 7 adheres to the crystal blank 3 to deteriorate the vibration characteristics (not shown). For this reason, it is necessary to reduce the size of the crystal blank 3, and there is a problem that the degree of freedom in design is impaired. In particular, these have become more serious problems as the size of the device has become smaller. Note that a positional deviation exceeding the allowable error results in poor appearance.

【0007】(発明の目的)本発明は位置ズレがあって
もシールパスを一定に確保するセラミックベース及びこ
れを用いて信頼性及び振動特性を良好に維持した圧電装
置特に圧電発振器を提供することを目的とする。
(Object of the Invention) It is an object of the present invention to provide a ceramic base which ensures a constant seal path even when there is a displacement, and a piezoelectric device, particularly a piezoelectric oscillator, which uses the ceramic base to maintain good reliability and vibration characteristics. Aim.

【0008】[0008]

【課題を解決するための手段】本発明は、底壁5上に枠
壁12を積層して底壁5よりも枠壁12の外形を小さく
してセラミックベース10としたことを基本的な解決手
段とする。
The basic solution of the present invention is to form a ceramic base 10 by laminating a frame wall 12 on a bottom wall 5 and making the outer shape of the frame wall 12 smaller than the bottom wall 5. Means.

【0009】[0009]

【作用】本発明では、底壁5の上面に外形が底壁5より
小さな枠壁12を設けて、カバー11を接合する。した
がって、カバー11が許容誤差の範囲内で位置ズレを生
じてもシールパスWを一定に維持する。以下、本発明の
一実施例を説明する。
According to the present invention, a frame wall 12 whose outer shape is smaller than the bottom wall 5 is provided on the upper surface of the bottom wall 5, and the cover 11 is joined. Therefore, even if the cover 11 is displaced within the allowable error range, the seal path W is kept constant. Hereinafter, an embodiment of the present invention will be described.

【0010】[0010]

【実施例】第1図は本発明の一実施例を説明する水晶発
振器の断面図である。なお、前従来例図と同一部分には
同番号を付与してその説明は簡略又は省略する。水晶発
振器は前述同様にセラミックベース10にカバー11を
樹脂7によって接合して封止する。そして、この実施例
では、セラミックベース10は前述の底壁5(ab)に
加えて、枠壁12を積層した三層構造とする。枠壁12
は底壁5の外形より小さく、許容誤差分程度として内側
に積層される。ICチップ2は凹部底面に、水晶片3は
ICチップを覆って、両端部が枠壁12の表面に固着さ
れる。カバーは平板状とし、外周部に樹脂7を塗布す
る。そして、セラミックベース10の枠壁12上に位置
決めし、樹脂を加熱溶融して封止する。
FIG. 1 is a sectional view of a crystal oscillator for explaining an embodiment of the present invention. The same parts as those in the prior art are denoted by the same reference numerals, and description thereof will be simplified or omitted. The crystal oscillator is sealed by bonding a cover 11 to a ceramic base 10 with a resin 7 as described above. In this embodiment, the ceramic base 10 has a three-layer structure in which a frame wall 12 is laminated in addition to the bottom wall 5 (ab) described above. Frame wall 12
Are smaller than the outer shape of the bottom wall 5 and are laminated on the inner side with a tolerance. The IC chip 2 covers the bottom surface of the recess, and the crystal blank 3 covers the IC chip. Both ends are fixed to the surface of the frame wall 12. The cover is formed in a flat plate shape, and a resin 7 is applied to an outer peripheral portion. Then, the resin is positioned on the frame wall 12 of the ceramic base 10, and the resin is heated and melted for sealing.

【0011】このような構成であれば、カバー11が許
容誤差範囲内で位置ズレを生じたとしても、第2図に示
したように、シールパスWは枠壁12の壁幅として一定
値を維持する。したがって、接合強度及び耐湿性を良好
に維持して信頼性を高める。また、枠壁12は固定され
て位置ズレを生じないので、溶融した樹脂7が水晶片3
に付着することもない。したがって、設計自由度を損う
ことがなく、振動特性を良好に維持できる。
With this configuration, even if the cover 11 is displaced within the allowable error range, the seal path W maintains a constant value as the wall width of the frame wall 12, as shown in FIG. I do. Therefore, the bonding strength and the moisture resistance are maintained well, and the reliability is improved. In addition, since the frame wall 12 is fixed and does not displace, the molten resin 7 is
It does not adhere to Therefore, the vibration characteristics can be favorably maintained without impairing the degree of freedom in design.

【0012】[0012]

【他の事項】上記実施例では、第2底壁5bに孔を設け
て第1底壁5aとの間に凹部6を設けてICチップ2を
収容したが、第3図に示したように、これとは逆に第1
底壁5aに孔を設けて第2底壁5bを平板として凹部6
を設けてICチップ2を収容してもよい。この場合、樹
脂13を充填して(所謂ポッテング)ICチップ2を保
護する。
[Others] In the above embodiment, the second bottom wall 5b is provided with a hole and the recess 6 is provided between the second bottom wall 5a and the first bottom wall 5a to accommodate the IC chip 2, but as shown in FIG. , On the contrary, the first
A hole is formed in the bottom wall 5a to make the second bottom wall 5b a flat plate,
May be provided to accommodate the IC chip 2. In this case, the IC chip 2 is protected by filling with resin 13 (so-called potting).

【0013】また、凹部6には、ICチップ2のみなら
ずコンデンサ等の他の素子を収容してもよい。また、水
晶片3は両端を固着して保持したが、一端側に引出電極
を延出して一端部のみを保持してもよい。また、樹脂7
はカバー11側に塗布したがセラミックベース10側に
塗布されていてもよい。また、樹脂7による封止とした
が、ガラス及びその他の封止材を用いた場合であっても
同様に適用できる。また、カバー11はセラミック等の
絶縁体であっても金属でもよい。そして、平板状とした
が枠壁12との接合面が平板状であればよい。
The recess 6 may accommodate not only the IC chip 2 but also other elements such as a capacitor. Further, although both ends of the crystal blank 3 are fixedly held, an extraction electrode may be extended to one end side to hold only one end. In addition, resin 7
Is applied to the cover 11 side, but may be applied to the ceramic base 10 side. In addition, although the sealing is performed by the resin 7, the same applies to the case where glass and other sealing materials are used. The cover 11 may be an insulator such as a ceramic or a metal. And although it was flat-shaped, what is necessary is just to make the joint surface with the frame wall 12 flat.

【0014】また、第4図に示したように、カバー11
の外周に窪み14を形成して樹脂7を塗布し、枠壁12
を位置決めして位置ズレを防止するようにしてもよい。
また、水晶発振器として説明したが、第5図に示したよ
うに、底壁5と枠壁12とからセラミックベース15を
形成し、底壁5上に水晶片3のみを固着した水晶振動子
であっても、同様に適用できる。さらには、図示しない
多重モードを利用した所謂MCF(MONOLITHIC CRYSTA
L FILTER)や弾性表面波素子等の圧電装置にも同様に
適用でき、本発明ではこれらを技術的範囲から除外する
ものではない。
Further, as shown in FIG.
A recess 14 is formed on the outer periphery of the
May be positioned to prevent misalignment.
Although described as a crystal oscillator, as shown in FIG. 5, a ceramic resonator 15 in which a ceramic base 15 is formed from the bottom wall 5 and the frame wall 12 and only the crystal blank 3 is fixed on the bottom wall 5 is used. If so, the same applies. Furthermore, a so-called MCF (MONOLITHIC CRYSTAR) using a multiplex mode (not shown)
The present invention is similarly applicable to piezoelectric devices such as L FILTER) and surface acoustic wave elements, and the present invention does not exclude these from the technical scope.

【0015】[0015]

【発明の効果】
本発明は、底壁上に枠壁を積層して底壁よりも枠
壁の外形を小さくしてセラミックベースとし、これに圧
電片を収容してカバーを封止するので、位置ズレがあっ
てもシールパスを一定に確保して、信頼性及び振動特性
を良好に維持した圧電装置特に圧電発振器を提供でき
る。
【The invention's effect】
According to the present invention, since the frame wall is laminated on the bottom wall and the outer shape of the frame wall is made smaller than the bottom wall to form a ceramic base, the piezoelectric piece is accommodated in the ceramic base and the cover is sealed, so there is a misalignment. Also, it is possible to provide a piezoelectric device, in particular, a piezoelectric oscillator, in which the seal path is kept constant and the reliability and the vibration characteristics are well maintained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を説明する水晶発振器の断面
図である。
FIG. 1 is a cross-sectional view of a crystal oscillator illustrating one embodiment of the present invention.

【図2】本発明の作用を説明する水晶発振器の断面であ
る。
FIG. 2 is a cross-sectional view of a crystal oscillator illustrating the operation of the present invention.

【図3】本発明の他の実施例を説明する水晶発振器の断
面図である。
FIG. 3 is a sectional view of a crystal oscillator illustrating another embodiment of the present invention.

【図4】本発明の他の実施例を説明する水晶発振器の一
部断面図である。
FIG. 4 is a partial sectional view of a crystal oscillator illustrating another embodiment of the present invention.

【図5】本発明の他の実施例を説明する水晶振動子の断
面図である。
FIG. 5 is a cross-sectional view of a crystal unit for explaining another embodiment of the present invention.

【図6】従来例を説明する水晶発振器の断面図である。FIG. 6 is a cross-sectional view of a crystal oscillator illustrating a conventional example.

【図7】従来例の問題点を説明する水晶発振器の一部断
面図である。
FIG. 7 is a partial cross-sectional view of a crystal oscillator explaining a problem of a conventional example.

【符号の説明】[Explanation of symbols]

1、10、15 セラミックベース、2 ICチップ、
3 水晶片、4、11カバー、5 底壁、6 凹部、7
樹脂、8 バンプ、9 導電性接着剤、12 枠壁、
13 ポッティング剤、14 窪み.
1, 10, 15 ceramic base, 2 IC chips,
3 crystal blank, 4, 11 cover, 5 bottom wall, 6 recess, 7
Resin, 8 bumps, 9 conductive adhesive, 12 frame walls,
13 potting agent, 14 depression.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H03H 9/10 H01L 41/08 C ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H03H 9/10 H01L 41/08 C

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】底壁と枠壁とを積層してなり該底壁上に圧
電片を保持し、前記枠壁の上面とカバーとが封止材によ
って接合されるセラミックベースにおいて、前記底壁よ
りも前記枠壁の外形を小さくしたことを特徴とするセラ
ミックベース。
1. A ceramic base in which a bottom wall and a frame wall are laminated and a piezoelectric piece is held on the bottom wall, and an upper surface of the frame wall and a cover are joined by a sealing material. A ceramic base characterized in that the outer shape of the frame wall is smaller than that of the ceramic base.
【請求項2】底壁と枠壁とを積層してなるセラミックベ
ースと、前記底壁上に保持された圧電片と、前記枠壁の
上面を封止材によって接合されたカバーとからなる圧電
装置において、前記底壁よりも前記枠壁の外形を小さく
したことを特徴とする圧電装置。
2. A piezoelectric device comprising: a ceramic base formed by laminating a bottom wall and a frame wall; a piezoelectric piece held on the bottom wall; and a cover having an upper surface of the frame wall joined by a sealing material. A piezoelectric device, wherein the outer shape of the frame wall is smaller than the bottom wall.
【請求項3】底壁と枠壁とを積層してなるセラミックベ
ースと、前記底壁上に保持された圧電片と、前記底壁に
設けた凹部に収容したICチップと、前記枠壁の上面を
封止材によって接合されたカバーとからなる圧電発振器
において、前記底壁よりも前記枠壁の外形を小さくした
ことを特徴とする圧電発振器。
3. A ceramic base formed by laminating a bottom wall and a frame wall, a piezoelectric piece held on the bottom wall, an IC chip housed in a recess provided in the bottom wall, A piezoelectric oscillator comprising a cover having an upper surface joined by a sealing material, wherein an outer shape of the frame wall is smaller than that of the bottom wall.
JP26674099A 1999-09-21 1999-09-21 Ceramic base, piezoelectric device and piezoelectric oscillator Pending JP2001094379A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26674099A JP2001094379A (en) 1999-09-21 1999-09-21 Ceramic base, piezoelectric device and piezoelectric oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26674099A JP2001094379A (en) 1999-09-21 1999-09-21 Ceramic base, piezoelectric device and piezoelectric oscillator

Publications (1)

Publication Number Publication Date
JP2001094379A true JP2001094379A (en) 2001-04-06

Family

ID=17435055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26674099A Pending JP2001094379A (en) 1999-09-21 1999-09-21 Ceramic base, piezoelectric device and piezoelectric oscillator

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Cited By (2)

* Cited by examiner, † Cited by third party
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JP6281734B2 (en) * 2015-05-29 2018-02-21 株式会社村田製作所 Piezoelectric vibrator and manufacturing method thereof
JP2021061500A (en) * 2019-10-04 2021-04-15 日本電波工業株式会社 Pedestal, vibrator, and oscillator with blank

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6281734B2 (en) * 2015-05-29 2018-02-21 株式会社村田製作所 Piezoelectric vibrator and manufacturing method thereof
JPWO2016194562A1 (en) * 2015-05-29 2018-03-29 株式会社村田製作所 Piezoelectric vibrator and manufacturing method thereof
JP2021061500A (en) * 2019-10-04 2021-04-15 日本電波工業株式会社 Pedestal, vibrator, and oscillator with blank
JP7365182B2 (en) 2019-10-04 2023-10-19 日本電波工業株式会社 Oscillator and oscillator

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