JP2001094123A - Variable-capacitance diode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable-capacitance diode which has reduced series resistance by suppressing increase in capacitance. SOLUTION: This variable-capacitance diode comprises an N-type epitaxial layer 13, formed in the top face of an N+ type semiconductor substrate 12 and having a specific resistance higher than this substrate, a P+ type diffused layer 20 formed in a central specified region including a surface in this epitaxial layer 13, and an N+ type implanted diffused layer 17 provided immediately under this P+ type diffused layer 20, so as to form a P+/N+ junction 21 with a part of the bottom face of this diffused layer and having an impurity concentration higher than the epitaxial layer 13 and a depth which does not reach the top face of the semiconductor substrate 12, and is provided with a first electrode 22 making continuity with the top face of the P+ type diffused layer 20 and a second electrode 23, making continuity with the bottom face of the semiconductor substrate 12, where the bottom face area of the P+ type diffused layer 20 is 1.5 times or more as large as the top face area of the N+ type implanted diffused layer 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low voltage operating voltage of about 10 V or less and a capacity of 10 pF
The present invention relates to a variable-capacitance diode suitable for high-frequency use having a low capacity of the following order.

[0002]

2. Description of the Related Art The prior art will be described with reference to FIGS. FIG. 16 is a sectional view of a first conventional example, and FIG.
FIG. 7 is a sectional view of a second conventional example.

First, a first conventional example shown in FIG.
Variable capacitance diode formed so that the capacitance becomes 6 pF
In mode 1, this is N⁺A predetermined thickness on the semiconductor substrate 2
N-type epitaxial layer 3 is formed by vapor phase epitaxy
Including the surface in the N-type epitaxial layer 3.
P-type impurities are ion-implanted and diffused
P made⁺Type diffusion layer 4 is provided.⁺Type
P just below the diffusion layer 4⁺/ N⁺To form a bond
N⁺A mold implantation diffusion layer 5 is provided. N ⁺Type in
The plastic diffusion layer 5 is usually made of P to secure withstand voltage characteristics.
⁺Formed so as to have a smaller shape than the mold diffusion layer 4.
, P⁺Type diffusion layer 4 is N⁺Outermost circumference of mold implantation diffusion layer 5
It protrudes about 5 μm from the edge portion.

In such a variable capacitance diode 1,
Capacity C_TaIs P⁺Diffusion layer 4 and N ⁺Type implantable diffusion layer
Capacity C between 5_{P + a / N + a}And P⁺Diffusion layer
4 and the capacitance C between the N-type epitaxial layer 3
_{P + a / Na}And the combined capacity_{T a}= 6 pF.

The series resistance value r _sa is the value of the P ⁺ type diffusion layer 4.
Resistor _{r P + a} and the resistance of the ^{N +} -type implantation diffusion layer 5 r
_{From N + a} , the resistance r _Na of the N-type epitaxial layer 3, the resistance r _Sub of the semiconductor substrate 2, and the junction area s _ja ,
r _sa = (rP _{+ a} + rN _{+ a} + _rNa + _rSub ) ×
K × 1 / s _ja , and (r _{N + a} + r _Na ) fluctuates as the extension of the depletion layer changes due to the applied reverse bias voltage. In other words, the resistance of the depletion layer is zero and is not included in the series resistance value r _sa, and the higher the reverse bias voltage, the smaller the series resistance r _sa . Note that K is a constant.
For example, it is assumed that the series resistance r _sa when the reverse bias voltage is 1 V is 0.5Ω.

[0006] Further, in the case where the capacitance is to be reduced in the thus formed device, conventionally, a method of reducing the area of the P ⁺ / N ⁺ junction is generally used. In such a method, the capacity is reduced, for example, the capacity is reduced to half.
7 has a configuration similar to the second conventional example.

In FIG. 17, the variable capacitance diode 6
Is formed to have a capacitance of 3 pF, for example.
As in the first conventional example, N⁺Type semiconductor substrate 2
An N-type epitaxial layer 3 is formed.
P-type impurities are implanted into a predetermined central region including the surface in the metal layer 3.
P in the first conventional example formed by ON implantation and diffusion⁺
P, which is approximately の of the area of the diffusion layer 4⁺Mold diffusion layer 7
Have been killed. Further P ⁺Immediately below the type diffusion layer 7, the first
P in the conventional example of⁺/ N⁺1/2 of the bonding area
P⁺/ N⁺Form junctions and ensure withstand voltage characteristics
From the outermost edge⁺Mold diffusion layer 7 is about 5 μm
N to protrude⁺The mold implantation diffusion layer 8 is provided.
You.

In such a variable capacitance diode 6,
Capacity C_TbIs P⁺Type diffusion layer 7 and N ⁺Type implantable diffusion layer
Capacity between 8_{P + b / N + b}And P⁺Diffusion layer
7 and N-type epitaxial layer 3
_{P + b / Nb}And the combined capacity. The capacity C
_TbIs P⁺/ N⁺The bonding area is the same as in the first conventional example.
P⁺/ N⁺Since it is 1/2 of the area of the joint, 2C_Tb=
C_TaAnd C_Tb= 3 pF.

On the other hand, series resistance _{r sb} is, ^{P +} -type diffusion layer 7
Resistor _{r P + b} and the resistance r of the ^{N +} -type implantation diffusion layer 8
_{N + b} and resistance r _Na = r of N-type epitaxial layer 3
_Nb , the resistance r _Sub of the semiconductor substrate 2 and the junction area s
_{From jb} , r _sb = (r _{P + b} + r _{N + b} + r _Nb +
r _Sub ) × K × 1 / s _jb and (r _{N + b} + r
_Nb ) varies with the applied reverse bias voltage, but the junction area s _jb is _smaller than the junction area s in the first conventional example.
_Since it is 1/2 of _ja , the series resistance r _sb is twice the series resistance r _sa of the first conventional example. For example, when the reverse bias voltage is 1V, the series resistance r _sb becomes 1Ω.

As described above, the conventional P
^In the method of reducing the area of the ⁺ / N ⁺ junction to reduce the capacitance,
When the capacitance is reduced, the series resistance increases in inverse proportion. On the other hand, if an attempt is made to reduce the series resistance, the capacitance will increase. For this reason,
It is strongly desired to reduce the series resistance by suppressing an increase in capacitance.

Furthermore, by reducing the geometry of the P ⁺ -type diffusion layer 7, it is assumed small even electrode geometry comparable size and this provided to conduct the P ⁺ -type diffusion layer 7, the bonding to the electrode Therefore, the linearity of the lead wire to be fixed must be reduced, and the resistance of the lead wire increases. Further, if the lead wire cannot be made thin, the lead wire is fixed to the reduced electrode, so that it cannot be said to be good in workability and is difficult to handle.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to reduce the series resistance by suppressing an increase in capacitance.
An object of the present invention is to provide a variable capacitance diode which is easy to handle.

[0013]

A variable capacitance diode according to the present invention comprises: a first conductivity type epitaxial layer formed on one principal surface of a first conductivity type semiconductor substrate and having a higher specific resistance than the semiconductor substrate; A second conductivity type diffusion layer having a high impurity concentration of the second conductivity type formed in the epitaxial layer, and a junction formed with a part of the lower surface of the diffusion layer immediately below the second conductivity type diffusion layer. A first conductivity type implanted diffusion layer having a first conductivity type impurity concentration higher than that of the provided epitaxial layer and having a depth that does not reach one main surface of the semiconductor substrate; A first electrode conducting to the upper surface of the layer and a second electrode conducting to the other main surface of the semiconductor substrate.
In the variable capacitance diode provided with each electrode, the lower surface area of the second conductivity type diffusion layer is 1.5 times or more the upper surface area of the first conductivity type implanted diffusion layer. The second conductivity type diffusion layer is formed by forming the first conductivity type implanted diffusion layer on the epitaxial layer formed on the semiconductor substrate, and then forming the first conductivity type implanted diffusion layer and the epitaxial layer on the epitaxial layer formed by the first conductivity type implanted diffusion layer. It is characterized by being formed by diffusing a second conductive type high impurity so that the thickness becomes thin.
A first electrode conducting to the upper surface of the conductive type diffusion layer is formed to have substantially the same shape as the upper surface of the second conductive type diffusion layer. At least one shape of the one-conductivity-type implanted diffusion layer is a combined capacitance of a capacitance between the second-conductivity-type diffusion layer and the first-conductivity-type implanted diffusion layer and a capacitance between the second-conductivity-type diffusion layer and the epitaxial layer. Are formed so as to be constant within a range of a predetermined reverse bias voltage, and the second conductivity type diffusion layer is a layer just above the first conductivity type implanted diffusion layer. The thickness of a portion other than the portion directly above the portion is formed to be thicker than the thickness, and the second conductivity type diffusion layer further includes a first conductive type diffusion layer formed on the epitaxial layer formed on the semiconductor substrate. After the formation of the implanted diffusion layer, the first conductive Implantation diffusion layer second right above parts as layer thickness than the first conductivity type implantation diffusion layer becomes thinner for
It is formed by diffusing a high conductivity type impurity and further diffusing a second conductivity type high impurity so as to be thicker than a portion immediately above the first conductivity type implantable diffusion layer. It is characterized by the following.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment will be described with reference to FIGS. FIG. 1 is a cross-sectional view after the first manufacturing process, and FIG. 2 is a cross-sectional view after the second manufacturing process.
FIG. 4 is a cross-sectional view after the end of the third manufacturing step, FIG. 4 is a cross-sectional view after the end of the fourth manufacturing step, and FIG. 5 is a cross-sectional view for explaining a state in which a reverse bias voltage is not applied; FIG.
Is a sectional view for explaining a state of applying a reverse bias voltage 1V, 7 is a diagram for explaining the concentration profile of the depletion layer state in FIG. 6, FIG. 7 (a) P ⁺ -type diffusion FIG. 7B is a diagram showing a state between the P ⁺ -type implanted diffusion layer and the N-type epitaxial layer, FIG. 7B is a diagram showing a state between the P ⁺ -type diffusion layer and the N-type epitaxial layer, and FIG. FIG. 9 is a cross-sectional view for explaining a state in which a reverse bias voltage of 4 V is applied. FIG. 9 is a characteristic diagram showing a change in resistance of each part immediately below the P ⁺ type diffusion layer with respect to the reverse bias voltage. FIG. 11 is a characteristic diagram showing a change in capacitance at a junction portion with respect to the graph, and FIG. 11 is a characteristic diagram showing a change in capacitance with respect to a reverse bias voltage.
2 is a diagram showing a change in series resistance with respect to a ratio of the area of the N ⁺ type implanted diffusion layer to the area of the P ⁺ type diffusion layer.

In FIGS. 1 to 12, reference numeral 11 denotes a variable capacitance diode formed so as to have a capacitance of, for example, 3 pF, which is formed through the following manufacturing steps. That is, in the first manufacturing process shown in FIG. 1, a well-known vapor phase is formed on a low-resistivity silicon semiconductor substrate 12 having a first conductivity type, for example, an N ⁺ type resistivity of about 0.003 Ωcm. An N-type epitaxial layer 13 having a predetermined thickness in the range of 2 μm to 5 μm and a higher specific resistance than the semiconductor substrate 12 having a specific resistance of about 1 Ωcm is formed by a growth method.

Next, in a second manufacturing step shown in FIG. 2, a silicon dioxide (SiO ₂ ) film 14 serving as an insulating film for protecting the surface is formed on the upper surface of the N-type epitaxial layer 13.
Is formed to a thickness of about 1 μm to ₂ μm, and a predetermined range of the SiO ₂ film 14 is etched to form an opening 15.
The central region, which is a part of the upper surface of the N-type epitaxial layer 13, is exposed over a predetermined range. Subsequently, a thin SiO ₂ film 16 of about 0.1 μm is formed on the exposed upper surface of the N-type epitaxial layer 13.

Then, the SiO ₂ film 16 is passed through the opening 15.
The N-type epitaxial layer 13 is doped with phosphorus (P), which is an N-type impurity, by, for example, an acceleration voltage of 100 keV and a dose of 10 ¹³ cm ⁻² to 10 from above.
^Implant under conditions of ¹⁴ cm- ² . Thereafter, a heat treatment also serving as annealing or the like is performed to diffuse the impurities. At a higher impurity concentration than the N-type epitaxial layer 13, the diffusion length is 0.5 μm to 1 μm from the surface in a predetermined length, for example, 0.6 μm.
An N ⁺ type implantation diffusion layer 17 having a diameter of about 70 μm and a diameter of about 70 μm is formed.

Next, in a third manufacturing process shown in FIG. 3, an opening 18 is formed by etching a predetermined area of the SiO ₂ film 14, and the upper surface of the N ⁺ -type implanted diffusion layer 17 and the surrounding area are formed. A partial region of the upper surface of a certain N-type epitaxial layer 13 is exposed over a predetermined range. continue,
A thin SiO ₂ layer of about 0.1 μm is formed on the exposed upper surfaces of the N ⁺ type implanted diffusion layer 17 and the N type epitaxial layer 13.
A film 19 is formed.

Then, the SiO ₂ film 19 is passed through the opening 18.
Is implanted into the N ⁺ -type implanted diffusion layer 17 and the N-type epitaxial layer 13 by ion implantation, for example, boron (B) of a P-type impurity, for example, at an acceleration voltage of 40 keV and a dose of 10 ^1. Inject under conditions of ⁶ cm ^-2 . After that, heat treatment is performed to diffuse the impurities,
A diffusion length shallower than the N ⁺ type implanted diffusion layer 17 is a predetermined length in a range of 0.3 μm to 0.7 μm from the surface, for example, 0.4 μm.
A P ⁺ type diffusion layer 20 having a diameter of about 122 μm and a diameter of about 122 μm is formed. As a result, the P ⁺ / N ⁺ junction 21 is formed directly below the P ⁺ -type diffusion layer 20 so that the N ⁺ -type implantation diffusion layer 17 is formed.
Is provided, and the outer peripheral portion of the P ⁺ type diffusion layer 20 is in a state protruding 26 μm from the N ⁺ type implanted diffusion layer 17. Then, the area ratio of the P ⁺ -type diffusion layer 20 to the N ⁺ -type implantation diffusion layer 17 is 3.04.

Next, in a fourth manufacturing process shown in FIG. 4, the thin SiO ₂ film 19 in the opening 18 is removed, and aluminum (Al) is formed on the upper surface of the P ⁺ type diffusion layer 20 exposed in the opening 18. ), And further, an Al deposited film is formed to have the same diameter as that of the P ⁺ type diffusion layer 20 at 122 μm to form the first electrode 2.
Form 2 Similarly, Al is deposited on the lower surface of the semiconductor substrate 12 to form the second electrode 23. A lead wire 24 made of gold (Au) having a wire diameter of, for example, 20 μm is wire-bonded to the upper surface of the first electrode 22 of the variable capacitance diode 11 configured as described above. A bonding ball 25 having a diameter of about 4 to 5 times the wire diameter is formed at the bonding portion of the lead wire 24 by wire bonding.

[0022] Then, has been constructed as described above, the series resistance r _s0 in a state without application of a reverse bias voltage as shown in FIG. 5, the resistance r of the P ⁺ -type diffusion layer 20
_{P + 0} and resistance r of N ⁺ type implanted diffusion layer 17
_{N + 0} , the resistance r _N′0 of the N-type epitaxial layer 13 immediately below the N ⁺ -type implanted diffusion layer 17, the resistance r _N0 of the N-type epitaxial layer 13 directly below the P ⁺ -type diffusion layer 20, and the resistance r _N0 of the semiconductor substrate 12 in synthesized resistance and _{Sub, r s0 = r P +} 0 + {(r N + 0 + r N'0) × r N0
/ (R _{N + 0} + r _N′0 + r _N0 )｝ + r _Sub

Similarly, as shown in FIG.
Series resistance r with a voltage of 1 V applied_s1Is P⁺Mold expansion
Resistance r of the layer 20_{P + 1}And N⁺Mold implantation diffusion layer 17
Resistance r_{N + 1}And N⁺N just below the mold implantation diffusion layer 17
Of the epitaxial layer 13_N'1And N⁺Type in
P protruding from the plastic diffusion layer 17⁺Peripheral part of mold diffusion layer 20
Resistance r of N-type epitaxial layer 13 immediately below_N1And half
Resistance r of conductive substrate 12 _SubIs the combined resistance of_s1= R_{P + 1}+ ｛(R_{N + 1}+ R_N'1) × r_N1
/ (R_{N + 1}+ R_N'1+ R_N1)｝ + R_Sub Becomes And the resistance is r_{P + 1}= 0.005
Ω, (r_{N + 1}+ R_{N ' 1}) = 0.543Ω, r_N1=
0.093Ω, r_Sub= 0.13Ω
Series resistance r which is a resistance obtained by combining_s1Is 0.259
Ω.

When a reverse bias voltage of 1 V is applied,
Is P as shown by the dotted line.⁺Diffusion layer 20 and N⁺Mold imp
Between the diffusion layer 17 and the N-type epitaxial layer 13.
Mark X ₁, P⁺Diffusion layer 20 and N-type epitaxial layer 13
Double arrow Y between₁A depletion layer is formed in the range of. What
The figure shows the depletion layer formation state on the concentration profile.
As shown in FIG.

Further, as shown in FIG. 8, when a reverse bias voltage of 4 V is applied, the series resistance r _s4 is equal to the resistance r _{P + 4} of the P ⁺ type diffusion layer 20 and the N ⁺ type implantation diffusion layer 1.
7, the resistance r _N′4 of the N-type epitaxial layer 13 immediately below,
The resistance r of the N-type epitaxial layer 13 just below the outer periphery of the P ⁺ -type diffusion layer 20 protruding from the N ⁺ -type implantation diffusion layer 17
And _N4, with synthesized resistance and resistance _{r Sub} semiconductor substrate _{12, r s4 = r P +} 4 + {r N'4 × r N4 / (r N'4 +
r _N4 )｝ + r _Sub . This means that when a reverse bias voltage of 4 V is applied,
As indicated by the dotted line, a double arrow X is formed between the P ⁺ type diffusion layer 20, the N ⁺ type implanted diffusion layer 17, and the N type epitaxial layer 13.
₄ , a depletion layer is formed between the P ⁺ -type diffusion layer 20 and the N-type epitaxial layer 13 in the range of the double-headed arrow Y ₄ , and the resistance of the N ⁺ -type implantation diffusion layer 17 becomes zero.

Then, of the series resistance r _s of the variable capacitance diode 11 configured as described above, the P ⁺ type diffusion layer 2
0 immediately below the ^{N +} -type implantation diffusion layer 17 and the resistance in the N-type epitaxial layer _{13 (r N + + r N'} ), N + -type implantation N-type epitaxial layer immediately below ^{the P +} -type diffusion layer 20 outer peripheral portion protruding from the diffusion layer 17 The resistance r _N of the thirteen changes when the reverse bias voltage is changed, for example, as shown in FIG.

On the other hand, the capacitance _{C T} is, ^{P +} -type diffusion layer 20 and the N
⁺ -Type implantation capacity and _{C P + / N +} in ^P + / ^{N +} junction 21 portion between the diffusion layer 17, ^{N +} -type implantation diffusion layer 1
7, the capacitance C at the P ⁺ / N junction between the outer peripheral portion of the P ⁺ -type diffusion layer 20 and the N-type epitaxial layer 3.
_This is a combined capacitance with _{P + / N,} and each capacitance changes as shown in FIG. 10 when the reverse bias voltage is changed. The capacitance _{C T} of the variable capacitance diode 11,
The reverse bias voltage _V R (V) on the horizontal axis in FIG. 11, the vertical axis has become like the characteristic line _{P 1} shows taking capacitance _C T (pF), the reverse bias voltage _V R = 1 _(V) Capacity C _T = 3 (p
Has a F), the capacitance C _T with increasing reverse bias voltage V _R is gradually decreased.

Also, taking the area ratio on the horizontal axis and the series resistance r _s (Ω) on the vertical axis in FIG. 12, the ratio of the P ⁺ -type diffusion layer 20 to the N ⁺ -type implantation diffusion layer 17 in the variable capacitance diode 11 is described. area ratio 3.04, series resistance _{r s} is 0.
Point _{R 1} is plotted because it is 259Omu.

On the other hand, the above-mentioned second method for reducing the capacity is used.
And the capacitance value is set to 3 pF.
The comparative example, the second comparative example, and the third comparative example are compared with the above embodiment.

First, in the first comparative example, the outermost peripheral portion of the P ⁺ -type diffusion layer was formed so as to protrude from the N ⁺ -type implantation diffusion layer by 2 μm, and the other components were configured in the same manner as the second conventional example. The portions corresponding to those of the second conventional example are denoted by the same reference numerals and have the following configuration. In other words, the central predetermined region including the surface in the N-type epitaxial layer (3) formed on the N ⁺ -type semiconductor substrate (2) has a diameter of 103.
A μm P ⁺ -type diffusion layer (7) is provided. Further P
⁺ -Type Directly below the diffusion layer ^(7), P + / ^{N + P +} -type diffusion layer from the outermost peripheral portion to form a junction (7) ⁺ is a diameter so as to protrude 2μm of 99 .mu.m ^N -type implantation diffusion layer (8)
Is provided. The area ratio of the P ⁺ type diffusion layer (7) to the N ⁺ type implantation diffusion layer (8) is 1.0.
It becomes 8.

In the state where a reverse bias voltage of 1 V is applied in the first comparative example, the P ⁺ type diffusion layer (7)
The resistance of 0.005, ^{N +} -type implantation sum of the resistances of the resistor and ^{the N +} -type implantation diffusion layer (8) N-type epitaxial layer immediately below (3) of the diffusion layer (8) is 0.271Omu, ^{the N +} type implantation Since the resistance of the N-type epitaxial layer (3) immediately below the outer peripheral portion of the P ⁺ -type diffusion layer (7) protruding from the diffusion layer (8) is 1.149Ω and the resistance of the semiconductor substrate (2) is 0.16Ω, The series resistance of the first comparative example obtained by combining them is 0.430Ω.

Since the area ratio of the P ⁺ type diffusion layer (7) to the N ⁺ type implantation diffusion layer (8) is 1.08 and the series resistance is 0.430Ω, the first comparative example is shown in FIG.
At 2, the point _Sa is plotted. Furthermore, the capacitance _{C T} of the first comparative example is designed so as in FIG. 11, a characteristic line _{Q a,} capacitance _C T = 3 in the reverse bias voltage _V R = 1 _(V)
Has a (pF), the capacitance C _T with increasing of the embodiment similarly to the reverse bias voltage V _R is gradually decreased.

Next, in a second comparative example, the outermost peripheral portion of the P ⁺ -type diffusion layer is formed so as to protrude from the N ⁺ -type implantation diffusion layer by 5 μm, and the other parts are configured in the same manner as the second conventional example. The parts corresponding to those in the second conventional example are denoted by the same reference numerals and have the following configuration. In other words, the central predetermined region including the surface in the N type epitaxial layer (3) formed on the N ⁺ type semiconductor substrate (2) has a diameter of 106
A μm P ⁺ -type diffusion layer (7) is provided. Further P
⁺ -Type Directly below the diffusion layer ^(7), P + / ^{N + P +} -type diffusion layer from the outermost peripheral portion to form a junction (7) ⁺ is a diameter so as to protrude 5μm of 96 .mu.m ^N -type implantation diffusion layer (8)
Is provided. The area ratio of the P ⁺ type diffusion layer (7) to the N ⁺ type implantation diffusion layer (8) is 1.2.
It becomes 2.

In the state where the reverse bias voltage of 1 V is applied in the second comparative example, the P ⁺ type diffusion layer (7)
The resistance of 0.005, ^{N +} -type implantation sum of the resistances of the resistor and ^{the N +} -type implantation diffusion layer (8) N-type epitaxial layer immediately below (3) of the diffusion layer (8) is 0.289Omu, ^{the N +} type implantation The resistance of the N-type epitaxial layer (3) just below the outer peripheral portion of the P ⁺ -type diffusion layer (7) protruding from the diffusion layer (8) is about 0.
Since the resistance of the semiconductor substrate (2) is 460Ω and the resistance of the semiconductor substrate (2) is 0.15Ω, the series resistance of the second comparative example obtained by combining them is
0.377Ω.

Since the area ratio of the P ⁺ type diffusion layer (7) to the N ⁺ type implantation diffusion layer (8) is 1.22 and the series resistance is 0.377Ω, the second comparative example is shown in FIG.
At 2, the point _Sb is plotted.

Further, the third comparative example has the same diameter as the N ⁺ type implanted diffusion layer so that the P ⁺ type diffusion layer does not protrude, and the other components are configured in the same manner as the second conventional example. Parts corresponding to those in the second conventional example are denoted by the same reference numerals, and have a configuration described below. That is, a P ⁺ -type diffusion layer (7) having a diameter of 99 μm is provided in a central predetermined region including the surface in the N-type epitaxial layer (3) formed on the N ⁺ -type semiconductor substrate (2). . Further, immediately below the P ⁺ -type diffusion layer (7), an N ⁺ -type implantation diffusion layer (8) having the same diameter as that of the P ⁺ / N ⁺ junction is provided. Then, the area ratio of the P ⁺ type diffusion layer (7) to the N ⁺ type implantation diffusion layer (8) is 1.00.

In the state where the reverse bias voltage of 1 V is applied in the third comparative example, the P ⁺ type diffusion layer (7)
Is 0.005Ω, the sum of the resistance of the N ⁺ type implanted diffusion layer (8) and the resistance of the N type epitaxial layer (3) immediately below the N ⁺ type implanted diffusion layer (8) is 0.271Ω, and the semiconductor substrate (2) ) Is 0.16Ω, and the series resistance of the third comparative example obtained by combining them is 0.481Ω.

Since the area ratio of the P ⁺ type diffusion layer (7) to the N ⁺ type implantation diffusion layer (8) is 1.00 and the series resistance is 0.481Ω, the third comparative example is shown in FIG.
At 2, the point _Sc is plotted.

As a result, the dimension of the outermost peripheral portion of the P ⁺ -type diffusion layer (7) protruding from the N ⁺ -type implantation diffusion layer (8) is as follows:
In the first to third comparative examples having a capacitance of 3 pF, the series resistance is set to be substantially the same as that of the second conventional example so as to be from about zero to about 5 μm required to secure the withstand voltage characteristic. Is as high as 0.481Ω to 0.377Ω,
In the above embodiment, by increasing the area ratio of the P ⁺ -type diffusion layer 20 to the N ⁺ -type implantation diffusion layer 17 to 3.04, the series resistance can be made sufficiently low at 0.259Ω.

Further, in order to obtain a predetermined capacitance of 3 pF by lowering the series resistance, the N ⁺ -type implantation diffusion layer 1 is formed.
7 and the P ⁺ -type diffusion layer 2
Since the size (diameter) of 0 is increased, P ⁺
The size of the first electrode 22 usually formed on the upper surface of the mold diffusion layer 20 to the same size also becomes large. For this reason,
The wire diameter of the lead wire 24 fixed to the first electrode 22 can also be increased in proportion to the increase of the first electrode.
The resistance of the lead wire 24 can be reduced.
Further, even if the wire diameter of the lead wire 24 cannot be increased, the work of fixing the wire is facilitated by increasing the size of the first electrode 22.

Next, a second embodiment will be described with reference to FIG. 13 and the drawings of the first embodiment. FIG. 13 is a cross-sectional view after the end of the fourth manufacturing step in the first embodiment, which corresponds to the end of the fourth manufacturing step. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. The configuration of the present embodiment that is different from the first embodiment will be described.

In FIG. 13 and the drawings of the first embodiment, reference numeral 31 denotes a variable capacitance diode formed so as to have a capacitance of, for example, 3 pF.
It is formed through substantially the same steps as the above-described manufacturing steps to the fourth manufacturing step. That is, a predetermined range of 2 μm to 5 μm in a range from 2 μm to 5 μm is formed on a low-resistivity silicon semiconductor substrate 12 having a first conductivity type of, for example, N ⁺ type having a specific resistance of about 0.003 Ωcm. Thick, specific resistance is 1
An N-type epitaxial layer 13 having a higher specific resistance is formed from a semiconductor substrate 12 of about Ωcm.

Then, on the upper surface of the N-type epitaxial layer 13, an SiO ₂ film 14 is formed to a thickness of about 1 μm to protect the surface.
The SiO ₂ film 14 is formed to a thickness of 2 μm, and a predetermined range of the SiO ₂ film 14 is opened by etching (not shown), and a thin SiO ₂ film of about 0.1 μm is formed on the exposed upper surface of the N-type epitaxial layer 13. . After that, the thin S
N-type impurity P is implanted into a predetermined region at the center of the N-type epitaxial layer 13 through the iO ₂ film by an ion implantation method, and heat treatment is performed to diffuse the impurity. This allows
An N ⁺ type implanted diffusion layer 32 having a higher impurity concentration than the N type epitaxial layer 13 and a diffusion length of 0.5 μm to 1 μm from the surface, for example, about 0.6 μm and a diameter of 78 μm is formed.

Further, after forming the N ⁺ type implanted diffusion layer 32, the SiO ₂ film 14 is opened by etching, and about 0 nm is again formed on the exposed upper surfaces of the N ⁺ type implanted diffusion layer 32 and the N type epitaxial layer 13. SiO _{2 with a} thickness of about 1 μm
Form a film. Then, P-type impurity B is implanted into the N ⁺ -type implanted diffusion layer 32 and the N-type epitaxial layer 13 through the thin SiO ₂ film at the opening by ion implantation, and heat treatment is performed to diffuse the impurity. I do. Thereby, the diffusion length shallower than the N ⁺ type implantation diffusion layer 32 is a predetermined length in the range of 0.3 μm to 0.7 μm from the surface, for example, 0.1 μm.
A P ⁺ type diffusion layer 33 having a diameter of about 4 μm and a diameter of 106 μm is formed.

[0045] As a result ^P directly below the ^{P +} -type diffusion layer 33 ⁺
The N ⁺ -type implanted diffusion layer 32 is provided so as to form the / N ⁺ junction 34, and the outer periphery of the P ⁺ -type diffusion layer 33 is N
14 μm is protruded from the ⁺ type implantation diffusion layer 32. Then, P ^{+ with} respect to the N ⁺ type implantation diffusion layer 32 is formed.
The area ratio of the mold diffusion layer 33 is 1.85.

[0046] Thereafter, to remove the thin of the SiO ₂ film in the opening portion, by depositing Al on the exposed ^{P +} -type diffusion layer 33 top surface, an Al evaporated film having the same diameter as the ^{P +} -type diffusion layer 33 106
The first electrode 35 is formed by molding to a thickness of μm. Similarly, Al is deposited on the lower surface of the semiconductor substrate 12 to form the second electrode 23. The variable capacitance diode 31 thus configured
For example, on the upper surface of the first electrode 35, for example, A
The u-wire lead wire 24 is wire-bonded,
The diameter of the bonding portion of the lead wire 24 is 4
The bonding ball 25 is formed about twice to about five times.

In the above-described configuration,
A depletion layer is formed as in the first embodiment, and a reverse bias is formed.
Series resistance r with a voltage of 1 V applied_s11Is P⁺
Resistance of the diffusion layer 33_{P + 11}And N⁺Die implantation
Resistance r of layer 32_{N + 11}And N⁺Mold implantation diffusion layer 32
Resistance r of N-type epitaxial layer 13 immediately below_N'11When,
N⁺P protruding from the mold implantation diffusion layer 32⁺Diffusion layer
33, the resistance r of the N-type epitaxial layer 13 immediately below the outer peripheral portion
_N11And the resistance r of the semiconductor substrate 12_SubAnd synthesized
With resistance, r_s11= R_{P + 11}+ ｛(R_{N + 11}+ R_N'11)
× r_N11/ (R_{N + 1 1}+ R_N'11+ R_N11)｝
+ R_Sub Becomes And the resistance is r_{P + 11}= 0.00
5Ω, (r_{N + 11}+ R _N'11) = 0.437Ω, r
_N11= 0.018Ω, r_Sub= 0.15Ω
Then, a series resistance r, which is a resistance obtained by combining these,_s1Is
0.328Ω.

[0048] The capacitance _{C T} of the variable capacitance diode 31
An inverse bias voltage _V R (V) on the horizontal axis in FIG. 11, the vertical axis looks like a characteristic line _{P 11} shown by taking the capacitance _C T (pF), the reverse bias voltage _V R = 1 _(V ) And the capacitance C _T =
3 has a (pF), the capacitance _{C T} with increasing reverse bias voltage _{V R} is gradually decreased. FIG. 12 shows the area ratio on the horizontal axis and the series resistance r _s (Ω) on the vertical axis.
In the above-described variable capacitance diode 31, the area ratio of the P ⁺ type diffusion layer 33 to the N ⁺ type implantation diffusion layer 32 is 1.
85, since the series resistance r _s is 0.328Ω, the point R ₁₁
Is plotted.

As described above, also in the second embodiment,
N⁺P from the mold implantation diffusion layer 32 ⁺Type diffusion layer 33
Conventionally, the protrusion dimension is usually set to ensure withstand voltage characteristics.
It is more than twice the protruding dimension of about 5 μm provided
By setting the area ratio to 1.85 and the area ratio to 1.85,
With the series resistance of 0.328Ω
And lower than the series resistance of the first to third comparative examples.
Things.

Further, a third embodiment will be described with reference to FIG. FIG. 14 is a cross-sectional view. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 14, reference numeral 41 denotes, for example, a capacity of 3
A variable capacitance diode formed so as to have a pF, and first, for example, a specific resistance of the first conductivity type, for example, N ⁺ type is 0.003.
On a low specific resistance silicon semiconductor substrate 12 formed to about Ωcm, 2 μm to 5 μm
, And an N-type epitaxial layer 13 having a higher specific resistance than the semiconductor substrate 12 having a specific resistance of about 1 Ωcm.

Then, on the upper surface of the N-type epitaxial layer 13, an SiO ₂ film of about 1 μm to ₂ μm is provided for surface protection.
m, and a predetermined range of the SiO ₂ film is etched and opened to expose the exposed N-type epitaxial layer 13.
A thin SiO ₂ film of about 0.1 μm is formed on the upper surface of the substrate. After that, N-type impurity P is implanted into a predetermined region at the center of the N-type epitaxial layer 13 through the thin SiO ₂ film at the opening by ion implantation, and heat treatment is performed to diffuse the impurity. Thereby, the N-type epitaxial layer 1
The diffusion length from the surface at an impurity concentration higher than 3, e.g.
N ⁺ -type implantation diffusion layer 17 having a diameter of about 6 μm and a diameter of 70 μm
To form

Further, after forming the N ⁺ type implanted diffusion layer 17, an SiO ₂ film 42 is formed again on the entire upper surface. Then, a predetermined range of the SiO ₂ film 42 is etched to form an annular opening so as to cover the upper surface of the N ⁺ type implanted diffusion layer 17.
A thin SiO ₂ film of about 1 μm is formed. Thereafter, P-type impurity B is implanted into a predetermined annular region of the N-type epitaxial layer 13 through the thin SiO ₂ film at the opening by ion implantation, and heat treatment is performed to diffuse the impurity. As a result, the diffusion length shallower than the N ⁺ type implanted diffusion layer 17 from the surface is, for example, about 0.5 μm and the outer diameter 122
A μm-shaped annular P ⁺ -type diffusion layer 43a is formed.

Subsequently, after the SiO ₂ film 42 covering the upper surface of the N ⁺ type implanted diffusion layer 17 is removed by etching,
P is implanted on the upper surface of the ⁺ type implanted diffusion layer 17 by ion implantation.
The impurity of the type is implanted, and heat treatment is performed to diffuse the impurity. Accordingly, ^{N +} -type implantation shallower than the diffusion layer 17, also ^{P +} -type diffusion layer 43a than shallow diffusion length surface, for example, ^{P +} -type diffusion layer 43b continuous with the ^{P +} -type diffusion layer 43a in 0.4μm about To form This allows N ⁺
P ⁺ /
A P ⁺ type diffusion layer 43 forming an N ⁺ junction 44 is formed. Then, the outer peripheral portion of the P ⁺ type diffusion layer 43 is in a state of protruding 26 μm from the N ⁺ type implanted diffusion layer 17.

Thereafter, P in the opening portion⁺On the diffusion layer 43
Al is vapor-deposited on the ⁺Same as the mold diffusion layer 43
The first electrode 22 is formed by molding to the same diameter of 122 μm.
You. Similarly, Al is deposited on the lower surface of the semiconductor
An electrode 23 is formed. Variable volume constructed in this way
The diode 41 has a line, for example, on the upper surface of the first electrode 22.
An Au wire lead wire 24 having a diameter of 20 μm
And the bonding portion of the lead wire 24
A bonding ball 2 whose diameter is about 4 to 5 times the wire diameter
5 are formed.

In the structure configured as described above, the upper surface and the upper portion of the N ⁺ type implanted diffusion layer 17 have P ⁺
/ N ⁺ junction 44 so as to form a P ⁺ type diffusion layer 43.
Is formed, and the diffusion depth of the P ⁺ -type diffusion layer 43 a forming the P ⁺ / N junction in the outer peripheral portion protruding from the N ⁺ -type implantation diffusion layer 17 is set to the P ⁺ / N ⁺ just above the P ⁺ / N ⁺ junction 44. ⁺
It is possible to realize a series resistance value which is deeper than the mold diffusion layer 43b and lower than that of the first embodiment. First
The same effect as that of the embodiment can be obtained.

As described above, according to the first to third embodiments in which the area ratio of the P ⁺ -type diffusion layers 20, 33, 43 to the N ⁺ -type implantation diffusion layers 17, 32 is 1.5 or more, P ⁺ type diffusion layer (7) without increasing the capacitance
Of the N ⁺ -type implanted diffusion layer (8)
Compared with the first to third comparative examples according to the prior art in which the voltage is reduced from zero to about 5 μm required to secure the withstand voltage characteristic,
A further reduced series resistance can be obtained.

In order to obtain a predetermined capacitance value and reduce the series resistance, the size of the P ⁺ -type diffusion layer must be increased. As a result, the first electrode provided to conduct to the P ⁺ -type diffusion layer is also large. Thus, the resistance of the lead wire can be reduced at the same time as the series resistance of the variable capacitance diode is reduced. Even if it is not possible to increase the wire diameter of the lead wire, the work of fixing the lead wire is facilitated by increasing the size of the first electrode.

The relationship between the area resistance and the series resistance in the first embodiment, the second embodiment, and the first to third comparative examples in which the capacitance is 3 pF is plotted in FIG. On the curve Z, according to the relationship curve Z, when the area ratio becomes 3.5 or more, the series resistance becomes substantially constant. Further, the capacitance C _{P + / N +} and capacitor C _{P + / N} as shown in FIG. 10 changes with the change of the reverse bias voltage, Although these synthetic capacity is the capacity C _T of the variable capacitance diode, P ⁺ the configuration of the diffusion layer and the ^{N +} -type implantation diffusion layer, the capacitance _{C 0P + / N +} in ^P + / ^{N +} junction with the change of the reverse bias ^voltage, the capacitance _{C 0P + / N} in ^P + / N junction is As shown in FIG. 15, a variable capacitance diode in which the capacitance is changed as shown in FIG. 15 and the amount of change in the capacitance _COT takes a constant value T within a predetermined reverse bias voltage range is also used as described above. In this case, the series resistance can be reduced.

[0060]

As is apparent from the above description, according to the present invention, it is possible to reduce the series resistance while suppressing an increase in the capacitance.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view after a first manufacturing step according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view after a second manufacturing process according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view after a third manufacturing step according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view after a fourth manufacturing step according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a state in which a reverse bias voltage is not applied according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a state in which a reverse bias voltage of 1 V is applied in the first embodiment of the present invention.

7A and 7B are diagrams for explaining the state of a depletion layer in FIG. 6 by a concentration profile, and FIG. 7A shows a state between a P ⁺ type diffusion layer, an N ⁺ type implantation diffusion layer, and an N type epitaxial layer. FIG. 7B is a diagram showing a state between the P ⁺ type diffusion layer and the N type epitaxial layer.

FIG. 8 is a cross-sectional view for explaining a state where a reverse bias voltage of 4 V is applied in the first embodiment of the present invention.

FIG. 9 is a characteristic diagram showing a change in resistance of each part immediately below a P ⁺ type diffusion layer with respect to a reverse bias voltage according to the first embodiment of the present invention.

FIG. 10 is a characteristic diagram showing a change in capacitance at a junction with respect to a reverse bias voltage according to the first embodiment of the present invention.

FIG. 11 is a characteristic diagram showing a change in capacitance with respect to a reverse bias voltage in the first embodiment and the second embodiment of the present invention.

FIG. 12 is a diagram showing a change in series resistance with respect to a ratio of an area of an N ⁺ type implanted diffusion layer to an area of a P ⁺ type diffusion layer in the first embodiment and the second embodiment of the present invention.

FIG. 13 is a sectional view of a second embodiment of the present invention.

FIG. 14 is a sectional view of a third embodiment of the present invention.

FIG. 15 is a characteristic diagram showing a change in capacitance at a junction with respect to a reverse bias voltage according to the embodiment of the present invention.

FIG. 16 is a sectional view of a first conventional example.

FIG. 17 is a sectional view of a second conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 12 ... Semiconductor substrate 13 ... Epitaxial layer 17, 32 ... N ⁺ type implanted diffusion layer 20, 33, 43, 43a, 43b ... P ⁺ type diffusion layer 21, 34 ... P ⁺ / N ⁺ junction 22 ... 1st electrode 23 ... 2nd electrode

Claims (6)

[Claims] 1. An epitaxial layer of a first conductivity type formed on one main surface of a semiconductor substrate of a first conductivity type and having a higher specific resistance than the semiconductor substrate, and a high conductivity layer of a second conductivity type formed on the epitaxial layer. A second conductivity type diffusion layer having an impurity concentration; and a second conductivity type diffusion layer having an impurity concentration higher than that of the epitaxial layer provided immediately below the second conductivity type diffusion layer so as to form a junction with a part of the lower surface of the diffusion layer. A first conductivity type implanted diffusion layer having an impurity concentration of one conductivity type and having a depth not reaching one main surface of the semiconductor substrate, and a first electrode electrically connected to an upper surface of the second conductivity type diffusion layer; And a variable capacitance diode provided with a second electrode that is electrically connected to the other main surface of the semiconductor substrate, wherein the lower surface area of the second conductivity type diffusion layer is equal to 1.1 of the upper surface area of the first conductivity type implanted diffusion layer.
A variable capacitance diode characterized by being at least five times. 2. A second conductivity type diffusion layer, comprising: a first conductivity type implanted diffusion layer formed on an epitaxial layer formed on a semiconductor substrate; and a second conductivity type diffusion layer formed on the epitaxial layer. 2. The variable capacitance diode according to claim 1, wherein the variable capacitance diode is formed by diffusing a second conductive type high impurity such that the layer thickness is smaller than the conductive type implanted diffusion layer. 3. A first conductive type conductive layer which is electrically connected to the upper surface of the second conductive type diffusion layer.
2. The variable capacitance diode according to claim 1, wherein the electrode is formed in substantially the same shape as the upper surface of the second conductivity type diffusion layer. 4. A configuration in which at least one of the second conductivity type diffusion layer and the first conductivity type implanted diffusion layer has a capacity between the second conductivity type diffusion layer and the first conductivity type implanted diffusion layer and the second conductivity type implanted diffusion layer. 2. The variable capacitance diode according to claim 1, wherein a combined capacitance of the capacitance between the conductivity type diffusion layer and the epitaxial layer is formed to be constant within a predetermined reverse bias voltage range. 5. The second conductivity type diffusion layer is characterized in that a portion other than the portion immediately above the first conductivity type implanted diffusion layer has a greater thickness than a portion immediately above the first conductivity type implanted diffusion layer. Claim 1
The variable capacitance diode as described. 6. A second conductivity type diffusion layer, comprising: a first conductivity type implanted diffusion layer formed on an epitaxial layer formed on a semiconductor substrate; and a first conductivity type implanted diffusion layer formed directly above the first conductivity type implanted diffusion layer. The high impurity of the second conductivity type is diffused so that the layer thickness is smaller than the conductivity type implanted diffusion layer, and further, the portion other than the portion directly above the first conductivity type implantation diffusion layer is thicker than the portion directly above the first conductivity type implantation diffusion layer. 6. The variable capacitance diode according to claim 1, wherein the variable capacitance diode is formed by diffusing a second conductive type high impurity.