JP2001086404A - Digital phase information generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital phase information generator capable of generating phase information without necessitating thinning processing when expanding/ reducing the video signal of sequential scan and converting it to skip scan. SOLUTION: An adder 1 adds phase advancing information and the output of a selector 4. A holder 2 holds the output of the adder 1. An initial value selector 6 selects first and second initial values. A holder 3 holds the initial values. One of holders 2 and 3 is selected, inputted to the adder and outputted as phase information by the selector 4. The first initial value is made into '0', the second initial value is made into 1/2 of phase advancing information and these values are switched corresponding to field information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a digital phase information generating apparatus for generating digitalized digital phase information.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a conventional digital phase information generator. This digital phase information generation device is based on the hardware of modulo (method), and embodies the following expression (1). Y = X mod K (1) In this equation (1), mod is a function, and K
Means to output the remainder divided by Y as Y.

In FIG. 2, the digital phase information generating device includes an adder 1, a holding device 2, and an AND circuit 9. The adder 1 adds the input phase advance information and the output of the holding device 2 and inputs the result to the holding device 2. AND circuit 9
, A clock and a horizontal period update pulse are input, and the logical product of them is input to the holding device 2. The clock is a pulse that alternates between high and low alternately, and the horizontal cycle update pulse is a pulse that goes high once per horizontal cycle. Therefore, the output of the AND circuit 9 becomes high only once in one horizontal cycle. The holding device 2 outputs one signal in one horizontal cycle in which high is input.
Outputs the value held only once. The output of the holding device 2 is input to the adder 1 and output as phase information.
Here, the number of propagation bits is 5 bits.

In this case, the input phase advance information corresponds to X in the above equation (1), and the output phase information corresponds to Y in the above equation (1). Further, the number of bits 5 of this device, that is, 2 ⁵ = 32, corresponds to K in the above equation (1). As an example, assuming that the initial value of the holding device 2 is 0 and the phase advance information is 20, the phase information output from the holding device 2 is 0 in the first horizontal cycle. 20 as the phase advance information
Is input, the phase advance information 20 is added to the phase information 0 by the adder 1 in the second horizontal cycle, and 20 is output as the phase information. In the third horizontal period, 20 is further added as phase progress information by the adder 1, but since it exceeds 32, 8 is output as phase information from 40-32. As a result of repeating this operation every horizontal cycle, the phase information becomes 0, 20, 8, 28, 16, 4, 4,
24, 12, 0... It should be noted that adding 20 to 12 results in 32, but since 32 is 0 as phase information, it is 0 next to 12.

Here, the case where the digital phase information generator shown in FIG. 2 is used will be described.
FIG. 3 shows a general configuration of an interpolation filter used to enlarge or reduce a video signal. Here, a four-tap filter is shown. In the following description, an operation in the case of enlargement will be described. In FIG. 3, input video signals are sequentially input to cascaded delay units 11 to 13,
Delayed by one horizontal period. Line memories can be used as the delay units 11 to 13.

The input video signal is input to the multiplier 14, and the delay units 11 to 17 are respectively input to the multipliers 15 to 17.
Thirteen outputs are input. Coefficients 0 to 3 are input to the multipliers 14 to 17 from the interpolation coefficient generation unit 10, respectively.
The multipliers 14 to 17 multiply the input signal by coefficients 0 to 3 and input the result to the adder 18. The interpolation coefficient generation unit 10 is constituted by a RAM as an example, and the phase information generated as shown in FIG. 2 is input to the interpolation coefficient generation unit 10. The interpolation coefficient generator 10 generates coefficients 0 to 3 according to the input phase information. This is because, when the video signal is interpolated and enlarged, the set of coefficients 0 to 3 needs to be different depending on the position where the enlarged interpolation signal is to be generated. The adder 18 adds the outputs of the multipliers 14 to 17 and outputs an enlarged and interpolated video signal.

The operation in the case where the progressive scanning video signal is enlarged by the interpolation filter shown in FIG. 3 and converted into interlaced scanning will be described. 4A to 4C, ○ indicates a pixel, and the vertical direction is the vertical direction of the screen. For convenience, pixel numbers 0, 1, 2,... Are assigned in the vicinity of the pixels indicated by に in FIGS. FIG.
4A shows an original signal (a progressively scanned video signal), and FIG. 4B shows a video signal (a magnified interpolation signal) which is magnified by 1.6 times, for example, by the interpolation filter shown in FIG. Is shown. In order to perform interlaced scanning of the enlarged interpolation signal shown in FIG. 4B, as shown in FIG.
In the first field and the second field, pixels are thinned out at different vertical phases. As described above, in order to enlarge an image in accordance with the conversion from the sequential scanning to the interlaced scanning, it is general to perform the enlarging process with the sequential scanning as it is, and then to perform the thinning process to convert the image into the interlaced scanning.

The operation for obtaining the enlarged interpolation signal shown in FIG. 4B will be described in more detail with reference to FIGS. The original signal shown in FIGS. 5 to 13 is either the first field or the second field of the original signal shown in FIG. Since the interpolation filter shown in FIG. 3 has four taps, it generates one enlarged interpolation signal pixel (interpolated pixel) from four consecutive pixels of the original signal. The interpolation filter generates an interpolation pixel using an interpolation function as shown in the figure as an example.

FIGS. 5 to 13 show a case where the interval between pixels of the original signal is divided into 32 as an example. The number of divisions between pixels is set to a power of two, because the calculation of the interpolation phase does not require division and simplifies the processing.

First, FIG. 5 shows a case where the pixel 0 of the original signal is set as the interpolation start position and the interpolation pixel 0 in the enlarged interpolation signal is generated at the same position. Since the interpolation pixel of the enlarged interpolation signal is generated at the position of the vertex P of the interpolation function, it is necessary to position the interpolation function as shown in FIG. The four pixels of the original signal are arranged on the interpolation function, each pixel is multiplied by an interpolation coefficient determined by the position of the interpolation function, and the result is added to generate the hatched interpolation pixel 0. In this case, since the interpolation pixel 0 is generated at the position of the pixel 0 of the original signal, the coefficient for the pixel 0 of the original signal is 1 and the coefficient for the other pixels is 0.

Next, in order to generate the interpolation pixel 1 in the enlarged interpolation signal, the vertex P of the interpolation function is positioned so as to be the position of the interpolation pixel 1 as shown in FIG. 4 of original signal
One pixel is generated by arranging two pixels on the interpolation function, multiplying each pixel by an interpolation coefficient determined by the position of the interpolation function, and adding the results.
The position at which the interpolation pixel is generated from the interpolation start position is determined by the enlargement ratio. In this example, the position is 20 out of 32 divisions. The phase advance information indicates how far the interpolation pixel is generated from the initial value 0, which is the interpolation start position, and the phase advance information 20 is input to the adder 1 in FIG. 2 as an added value. Will be.

By sequentially inputting the phase advance information (addition value) 20 to the adder 1 in FIG. 2 every one horizontal cycle, the position for generating the interpolation pixel is sequentially changed from the state of FIG. 5 to the state of FIG. It is equivalent to proceeding. Note that FIG. 13 is substantially the same as FIG. 5, and FIG.
The same state as FIG. 12 is repeated. The set of coefficients 0 to 3 to be input to the multipliers 14 to 17 in FIG. 3 necessary to generate the interpolation pixels 0, 1, 2,... Is output from the holding device 2 in FIG. This is phase information.
In the above example, eight pieces of phase information are generated corresponding to the eight states shown in FIGS. The eight pieces of phase information are input to the interpolation coefficient generator 10 shown in FIG. 3, and eight sets of coefficients 0 to 3 are generated corresponding to the eight pieces of phase information.

[0013]

The phase information is generated by using the conventional digital phase information generating apparatus shown in FIG. 2 described above, and the interpolation filter shown in FIG.
In the case where an enlarged interpolation signal as shown in (1) is generated and is converted into interlaced scanning, it is necessary to thin out pixels in the first field and the second field with different vertical phases as described above. When an enlarged interpolation signal for progressive scanning is generated and converted to interlaced scanning, the clock rate to be handled at that time must be doubled, which is inconvenient in hardware configuration. To avoid doubling the clock rate, hardware must be provided in two parallel phases,
This leads to a significant cost increase. Furthermore, when converting to interlaced scanning, the thinning process itself also complicates the conversion process.

In the above example, the case where the sequential scanning is converted into the interlaced scanning has been described. However, the same applies to the case where the sequential scanning is converted into the sequential scanning, the interlaced scanning is converted into the interlaced scanning, and the interlaced scanning is converted into the sequential scanning. The digital phase information generating apparatus has a problem that it is not possible to generate optimal phase information corresponding to the case where the video signal is scaled or converted. In other words, the conventional digital phase information generating apparatus can generate only fixed phase information (in the above example, fixed as eight phase information), and needs various phase information. There was a problem that it could not be handled.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is an object of the present invention to generate phase information that does not require thinning-out processing when converting a progressively scanned video signal into an interlaced scan. It is an object of the present invention to provide a digital phase information generating device capable of performing the following. It is another object of the present invention to provide a digital phase information generating apparatus which can generate a plurality of types of arbitrary phase information and is excellent in versatility.

[0016]

SUMMARY OF THE INVENTION The present invention provides a digital phase information generator for generating digitalized digital phase information in order to solve the above-mentioned problems of the prior art.
An adder (1) for adding a first input that is an input of the phase advance information and a second input, a first holding device (2) for holding an output of the adder, and at least two initial values. An initial value selecting device (6) for selecting and outputting a value, a second holding device (3) for holding an initial value selected by the initial value selecting device, an output of the first holding device, And selecting one of the outputs of the holding device and inputting the selected output to the adder as the second input.
And a selector (4) for outputting the digitalized phase information as digitized digital phase information.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital phase information generator according to the present invention will be described below with reference to the accompanying drawings. FIG.
FIG. 1 is a block diagram showing an embodiment of a digital phase information generating device of the present invention. In FIG. 1, the same parts as those in FIG.

The digital phase information generating device of the present invention includes an adder 1, holding devices 2 and 3, a selecting device 4, an initial value selecting device 6, and AND circuits 7 and 8. The adder 1 adds the input phase advance information and the output of the selection device 4 and inputs the result to the holding device 2. The output of the holding device 2 is input to the selection device 4 as one input signal of the selection device 4. Either the first initial value or the second initial value selected by the initial value selecting device 6 is given to the holding device 3. The output of the holding device 3 is input to the selection device 4 as the other input signal of the selection device 4. The field information is input to the initial value selection device 6, and the initial value selection device 6
Selects one of the first and second initial values according to this field information.

A clock and a horizontal period update pulse are input to the AND circuits 7 and 8, and the logical product of these is input to the holding devices 2 and 3. The clock is a pulse that alternates between high and low alternately, and the horizontal cycle update pulse is a pulse that goes high once per horizontal cycle. Therefore, the AND circuit 7,
The output of 8 goes high only once per horizontal cycle. The holding devices 2 and 3 output a value held only once in one horizontal cycle in which a high is input. Outputs of the holding devices 2 and 3 are input to the selection device 4 as described above. The selection device 4 selects one of the holding devices 2 and 3. The selection output of the selection device 4 is input to the adder 1 and output as phase information. Here, the number of propagation bits is 5 bits.

A selection signal, which is a pulse that goes high once in one vertical cycle, is input to the clear terminal of the holding device 2 and to the selection device 4. This selection signal is a clear signal for the holding device 2. The selection device 4 selects one of the holding devices 2 and 3 according to the input selection signal.
When the selection signal is high, the selection device 4 selects the output of the holding device 3, and when the selection signal is low, the selection device 4 selects the output of the holding device 2. That is, the selecting device 4 selects the output of the holding device 3 only once in one vertical cycle when the holding device 2 is cleared by the clear signal, but selects the output of the holding device 2 in other normal states.

In the digital phase information generating apparatus of the present invention configured as described above, first, the initial value selecting device 6 fixedly selects the first initial value 0 regardless of the first and second fields. The operation when it is assumed that 20 is input as the phase advance information will be described. When the selection signal goes high and the holding device 2 is cleared, and the selection device 4 selects the initial value 0 held by the holding device 3, 0 is output as phase information in the first horizontal cycle. When 20 is input as the phase advance information, in the second horizontal cycle, the adder 1
As a result, the phase advance information 20 is added to the phase information 0, and 20 is output as the phase information. Since the above operation is repeated, the operation of FIG. 1 is completely the same as that of FIG.
The output phase information is 0, 20, 8, 28, 1
6, 4, 24, 12, 0...

When this phase information is input to the interpolation coefficient generator 10 shown in FIG. 3, the interpolation filter shown in FIG.
The interpolation operation described with reference to FIG. 13 is performed. By the way, in the case where the progressive scan video signal shown in FIG. 4 is scaled and converted into interlaced scan, the first field of the expanded interpolation signal shown in FIG. Are thinned out and unnecessary, and in the second field, the interpolated pixels 2, 4, 6,... Are unnecessary. That is, in the first field, FIGS.
In FIG. 13, interpolation pixels 1, 3, 5, and 7, which are decimated as shown in FIGS. 6, 8, 10, and 12, are also generated.
In the second field, of FIGS.
This means that the interpolated pixels 0, 2, 4, 6, and 8 shown in FIGS. 9, 11, and 13 that are thinned out are also generated.

In the present invention, attention is paid to this point, and phase information is generated so as not to generate unnecessary interpolation pixels which are thinned out by the subsequent thinning-out processing even if they are generated by the interpolation filter shown in FIG. In other words, the feature is that phase information is output separately for the first and second fields so that only the interpolation pixels originally required in the first and second fields generate interpolation pixels. In the digital phase information generating apparatus of the present invention shown in FIG. 1, the initial value selecting device 6 allows the first and second initial values to be selected according to the field information, so that the first and second fields can be selected. Phase information corresponding to each is generated. At this time, the phase advance information input to the adder 1 is made different from the conventional one.

If the phase advance information (addition value) input to the adder 1 is 20, the digital phase information generating apparatus shown in FIG. 1 sequentially interpolates the interpolation pixels 0, 1, 2,. Phase information will be generated to generate a pixel. The phase advance information input to the adder 1 is doubled by 40.
Then, it can be understood that the digital phase information generating apparatus shown in FIG. 1 generates phase information so as to generate every other interpolated pixel such as interpolated pixels 0, 2, 4,. Also, it can be seen that the initial values in the first and second fields may be different from each other in order to generate the phase information corresponding to each of the first and second fields. In the second field, since the interpolation pixel has only to be generated from the position shown in FIG. 6, the initial value may be set to 20.

As described above, in FIG. 1, 40 is input to the adder 1 as the phase advance information, and the initial value selection device 6 sets 0 as the first initial value and 20 as the second initial value. , May be selected based on field information. The field information may alternately repeat high and low in the first and second fields. For example, if high is set in the first field and low is set in the second field, the initial value selection device 6 sets the field information as field information. When high is entered,
After selecting 0 as the first initial value and inputting a row as field information, 20 as the second initial value may be selected. It should be noted that 1 of the phase advance information input to the adder 1
/ 2 is the initial value in the second field.

As described above, when the phase advance information is set to 40 and the initial value selecting device 6 selects 0 as the first initial value in the first field, the phase information output from the selecting device 4 is 0. , 8, 16, 24, 0... this is,
This is phase information necessary for generating the interpolated pixels 0, 2, 4, 6, 8,... In the first field in FIG. When the initial value selecting device 6 selects the first initial value of 20 in the second field, the phase information output from the selecting device 4 is 20, 28, 4, 12, 20,. This is phase information necessary to generate the interpolated pixels 1, 3, 5, 7,... In the second field in FIG.

As described above, by using the digital phase information generator of the present invention, the interpolation filter shown in FIG. 3 can directly obtain the enlarged interpolation signal in the thinned state shown in FIG. 4C. Therefore, it is not necessary to perform the thinning process when converting the progressively scanned video signal into interlaced scanning by scaling. Therefore, the clock rate does not need to be doubled, and the thinning-out process itself is unnecessary, so that the hardware configuration for scan conversion can be simplified.

Further, the digital phase information generating device of the present invention can generate various phase information by providing the initial value selecting device 6. In the present embodiment, the case where one of the two initial values is selected has been described. However, if three or more initial values are selected, more types of phase information can be generated. Therefore, the digital phase information generating device of the present invention is extremely excellent in versatility. Therefore, the present invention is not limited to the case where the sequential scanning is converted to the interlaced scanning, but may be used for the case where the sequential scanning is sequentially scanned, the interlaced scanning is converted to the interlaced scanning, and the interlaced scanning is converted to the sequential scanning.

In this embodiment, as described with reference to FIGS. 5 to 13, a case where the interval between pixels of the original signal is divided into 32 has been described. However, the present invention is not limited to this. If finer phase information is required, the number of divisions may be more than 32 (64, 128, 256, 512...). The addition value, which is the phase advance information input to the adder 1, naturally takes a value according to the number of divisions. Also,
In the present embodiment, the phase information is used as a reference value (address) of the interpolation coefficient generation unit 10 which is a table for generating an interpolation coefficient. However, the present invention is also applicable to a case where the value of the phase information itself is used. Can be used.

[0030]

As described above in detail, the digital phase information generating apparatus according to the present invention comprises an adder for adding a first input, which is an input of phase advance information, and a second input, and an adder for adding the first input. A first holding device for holding the output of the container, an initial value selecting device for selecting and outputting at least two initial values, and a second holding device for holding the initial value selected by the initial value selecting device. , One of the output of the first holding device and the output of the second holding device is selected, and the selected output is input to the adder as the second input, and is output as digitalized digital phase information. And a selection device that generates a plurality of types of arbitrary phase information. Therefore, it is extremely versatile and can be widely applied to image interpolation processing, enlargement / reduction processing, and the like. It can also be used for filtering where the phase is intentionally shifted, and by using it as a part of an image processing apparatus, many beneficial effects can be brought about.

Further, the initial value selecting device selects and outputs two initial values consisting of the first and second initial values. One of the first and second initial values is selected according to the field information. , It is possible to generate optimal phase information to be used in scan conversion.
In particular, by setting the first initial value to 0 and setting the second initial value to の of the phase advance information, the thinning required when the video signal of the progressive scanning is scaled and converted to the interlaced scanning. The processing can be omitted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a block diagram illustrating a configuration example of an interpolation filter.

FIG. 4 is a diagram for explaining an operation in a case where a progressive scan video signal is enlarged and converted into interlaced scan.

FIG. 5 is a diagram for explaining an operation when an enlarged interpolation signal is generated.

FIG. 6 is a diagram for explaining an operation when an enlarged interpolation signal is generated.

FIG. 7 is a diagram for explaining an operation when an enlarged interpolation signal is generated.

FIG. 8 is a diagram for explaining an operation when an enlarged interpolation signal is generated.

FIG. 9 is a diagram for explaining an operation when an enlarged interpolation signal is generated.

FIG. 10 is a diagram for explaining an operation when an enlarged interpolation signal is generated.

FIG. 11 is a diagram for explaining an operation when an enlarged interpolation signal is generated.

FIG. 12 is a diagram for explaining an operation when an enlarged interpolation signal is generated.

FIG. 13 is a diagram for explaining an operation when an enlarged interpolation signal is generated.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Adder 2, 3 Holding device 4 Selection device 6 Initial value selection device 7, 8 AND circuit

Claims (4)

[Claims] 1. A digital phase information generation device for generating digitalized digital phase information, comprising: an adder for adding a first input, which is an input of phase advance information, and a second input; A first holding device for holding an output of the first value, an initial value selecting device for selecting and outputting at least two initial values, a second holding device for holding an initial value selected by the initial value selecting device, Selecting one of the output of the first holding device and the output of the second holding device, and inputting the selected output to the adder as the second input; A digital phase information generating device comprising: a selecting device that outputs the information as information. 2. The apparatus according to claim 1, wherein the first holding device has a clear terminal, and when no clear signal is input to the clear terminal, holds the output of the adder and receives a clear signal to the clear terminal. The selection device selects the output of the second holding device only when the first holding device is cleared, and selects the output of the first holding device in another normal state. 2. The digital phase information generator according to claim 1, wherein an output is selected. 3. The initial value selecting device selects and outputs two initial values consisting of first and second initial values, and outputs the first and second initial values in accordance with field information. 2. The digital phase information generating device according to claim 1, wherein one of the following is selected. 4. The digital phase information generating apparatus according to claim 3, wherein said first initial value is 0, and said second initial value is の of said phase advance information.