JP2001084708A - Digital-signal reproducing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital-signal reproducing apparatus, in which the value of a digital information signal is discriminated so as to be reproduced by a small constitution, without being influenced by the gain of a noise which is superposed on the digital information signal. SOLUTION: A resampling DPLL, which is composed of an interpolator, a phase detector, a loop filter, and a timing generator is installed on the input sidle of an equalizer. The phase detector, which outputs a phase error signal, is constituted in such a way that a temporary discrimination circuit 224, which receives resampling data from the interpolator and which temporarily discriminates a surest data value by a maximum likelihood detection, is contained, that a computing circuit 223 which computes and calculates the level difference in respective data between resampling points adjacent on both sides of the resampling data which is discriminated temporarily by the temporary discrimination circuit 224 is contained and that a switching circuit 227 which selects either the level difference, its inverted output or the output of a '0'-generator 229 is contained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal reproducing apparatus, and more particularly, to a digital signal reproducing apparatus having a phase synchronization control circuit for controlling phase synchronization of a digital signal reproduced from a recording medium such as a magnetic tape.

[0002]

2. Description of the Related Art A transmitted digital signal, particularly a digital signal reproduced from a recording medium, has a waveform that becomes dull due to a lack of a high-frequency component of the signal, or a fluctuation component such as jitter due to passing through a recording / reproducing mechanism. Or the original signal level cannot be obtained due to the influence of noise, etc.
Due to these various factors, the phase of the sampling clock and the phase of the reproduced digital signal may be shifted. Since the digital signal reproducing apparatus is configured to perform the signal sampling at the data existence time of the reproduced digital signal based on the sampling clock to obtain the reproduced data, if the phase shift between the sampling clock and the reproduced digital signal occurs, the digital signal reproducing apparatus is originally required. Cannot be obtained, and correct signal detection cannot be performed.

Therefore, the present applicant has previously disclosed in Japanese Patent Application Laid-open No. Hei 10-1
Japanese Patent No. 72250 discloses a digital signal reproducing apparatus provided with a phase synchronization control circuit including a temporary discriminating means for temporarily discriminating a likely information signal value from a supplied digital information signal. The digital signal reproducing apparatus proposed by the present applicant comprises an A / D converter for converting reproduced digital information supplied as an analog signal waveform into a digital signal, and a controller for controlling a sampling frequency of the A / D converter. Means, and temporary discriminating means for temporarily discriminating the most probable digital signal value by maximum likelihood detection using the correlation of the signal components of the digital signal transmitted with respect to the Digil signal output from the A / D conversion means, Error calculating means for outputting a value corresponding to the amplitude error based on the temporary determining result of the temporary determining means, wherein the control means controls the sampling frequency of the A / D converting means based on the error signal from the error calculating means. For outputting a control signal for the operation.

According to the digital signal reproducing apparatus proposed by the present applicant, the provision of the phase synchronization control circuit including the temporary discriminating means allows the digital information reproduction apparatus not to be affected by the noise / gain superimposed on the digital information signal. There is an effect that the value of the signal can be determined.

[0005]

However, in the digital signal reproducing apparatus proposed by the present applicant, the control means includes a D / A converter for D / A converting the error signal, and a D / A converter. A filter that integrates an analog signal from the A converter and outputs a low-frequency component, and a voltage-controlled oscillator (VC) that oscillates and outputs a signal having a frequency corresponding to the output voltage value of the filter.
O), and the output signal of the VCO is A / D
Since the conversion unit uses a sampling clock, a separate analog VCO is required in addition to digital signal processing, which is not suitable for miniaturization of the apparatus.

[0006] The present invention has been made in view of the above points,
It is an object of the present invention to provide a digital signal reproducing apparatus capable of discriminating and reproducing a value of a digital information signal by a small configuration without being affected by a noise gain superimposed on the digital information signal.

It is another object of the present invention to provide a digital signal reproducing apparatus that completely eliminates the dependence of analog temperature characteristics and parameters on variations.

Another object of the present invention is to provide a digital signal reproducing apparatus capable of accurately reproducing information recorded on a high-density recording medium by using partial response equalization.

[0009]

According to the present invention, there is provided a digital signal reproducing apparatus for decoding a transmitted digital information signal after performing phase synchronization control and waveform equalization on the transmitted digital information signal. A / D signal
An input digital signal obtained by the conversion is resampled at a desired bit rate to generate resampling data, a bit clock is extracted, and a resampling DPLL is provided to a subsequent block. An interpolator that estimates the data value of the phase point data of the input digital signal by interpolation and outputs resampling data, and a temporary interpolator that receives the resampling data from the interpolator and tentatively determines the most likely data value by maximum likelihood detection. Determining means, calculating means for calculating and calculating the level difference of each data of resampling points adjacent to both sides of the resampling data temporarily determined by the temporary determining means, and according to the value temporarily determined by the temporary determining means, Select an output signal from the arithmetic means, a signal whose polarity is inverted, or a preset value Phase error signal generating means for outputting as an error signal, a loop filter for integrating the phase error signal, and estimation of the next data point phase of the output signal of the loop filter and extraction of a bit clock, thereby obtaining data phase information And a timing generator for inputting the bit clock to the interpolator.

According to the present invention, the resampling data obtained from the reproduced digital signal by the resampling DPLL is supplied to the decoder through the equalizer, and the resampling DPLL phase detector detects the resampling data from the resampling data as a phase error algorithm. The most probable data value is provisionally determined by likelihood detection, and the level difference of each data of resampling points adjacent on both sides of the provisionally determined resampling data is calculated, and the calculated level is calculated according to the provisionally determined value. Since a difference or a value obtained by inverting the polarity or a preset value is selected and output as a phase error signal, A / D conversion is performed using an analog VCO whose output signal frequency is varied according to the phase error signal. Without changing the sampling frequency of the reproduced digital signal It is possible to obtain a more reliable phase error signal.

Here, the above-mentioned provisional judgment means dynamically sets the threshold value used for the maximum likelihood detection, so that the resampling point indicating "+1" or "-1" as the most probable data value. Or more likely "+
A resampling point indicating "1" or "-1" may be detected. In this case, it is possible to efficiently obtain a phase error signal with a minimum delay.

[0012] Further, the above-mentioned arithmetic means in the present invention comprises:
Until the provisional determination means determines a resampling point indicating the most likely "+1" or "-1" as a data value, or detects a resampling point indicating a more likely "+1" or "-1", The level difference of each data of the resampling points adjacent on both sides of the resampling point is held, and the level difference or the value obtained by inverting the polarity thereof or the value corresponding to the tentative judgment result 0 is selected according to the result of the tentative judgment. It is characterized by doing.

[0013] Further, the above-mentioned arithmetic means in the present invention includes:
Until the provisional determination means determines a resampling point indicating the most likely "+1" or "-1" as a data value, or detects a resampling point indicating a more likely "+1" or "-1", The level difference of each data of the resampling points adjacent on both sides of the resampling point and the value obtained by inverting the polarity are held, and the value obtained by inverting the level difference or the polarity or the value obtained by the provisional determination is obtained according to the result of the provisional determination. A value corresponding to the determination result 0 may be selected.

[0014] The provisional determination means may adaptively vary the magnitude of the threshold value used for maximum likelihood detection in accordance with the characteristics of the transmitted information signal.

[0015]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital signal reproducing apparatus according to the present invention. In the figure, a digital signal is recorded at a high density on a magnetic tape 10 as an example of a recording medium, and the recorded digital signal is supplied to a rotating head 11 attached to a rotating surface of a rotating drum in the same manner as during recording. Played by
After being pre-amplified by the pre-amplifier 12, the low-pass filter (L
Unnecessary high frequency components are removed through the PF) 13. LPF
The reproduced signal extracted from the sampling circuit 13 is sampled by a master clock in an A / D converter (not shown), further supplied to a DC blocking circuit 14 to block a DC component (DC component), and then supplied to a resampling DPLL 15. Is done.

The resampling DPLL 15 is a digital PL whose loop is completed in its own block.
An L (phase locked loop) circuit outputs resampling data generated by performing resampling (decimation interpolation) of the input signal at a desired bit rate to the equalizer 16.

The resampling DPLL 15
As described later, the maximum likelihood detection using the correlation of the input digital signal is used to temporarily determine the most probable resampling data value, and at the resampling points on both sides of the resampling point according to the provisional determination result. It includes a phase detector that calculates an amplitude error (balance) and outputs the result as a phase error.

The equalizer 16 performs waveform equalization by giving, for example, a partial response (PR) characteristic to the input signal. The output signal of the equalizer 16 is supplied to a decoding circuit 17.
Where, for example, after known Viterbi decoding,
It is supplied to the ECC circuit 18. The ECC circuit 18 uses the error correction code in the input decoded data sequence to correct a code error of a generation element of the error correction code, and outputs decoded data with reduced errors.

Next, the resampling DPLL 15 which is an essential part of the present invention will be described in more detail. FIG. 2 is a block diagram showing one embodiment of the resampling DPLL 15. As shown in FIG.
5 is an interpolator 21, a phase detector 22, a loop filter 2
1 and a timing generator 24. The interpolator 21 receives the reproduced digital signal from the DC blocking circuit 14 of FIG. 1, the data point phase information and the bit clock from the timing generator 24. Then, the data value of the phase point data of the reproduced digital signal is estimated by interpolation and output.

The output data value of the interpolator 21 is output to the equalizer 16 of FIG. 1 via the output terminal 25 as resampling data, while being supplied to the phase detector 22. The phase detector 22 generates a phase error signal as described later, supplies the phase error signal to the loop filter 23, integrates the signal, and supplies the integrated signal to the timing generator 24. The timing generator 24 estimates the phase of the next data point based on the input data of the loop filter 23, and uses the generated bit clock in the same way as the data point phase information in the interpolator 21.
Output to

Next, the configuration and operation of the phase detector 22 will be described in more detail. FIG. 3 shows a block diagram of one embodiment of the phase detector 22. The phase detector 22 is shown in FIG.
As shown in (2), two-stage cascaded delay elements 221 and 222 for delaying the resampling data output from the interpolator 21 by one resampling clock cycle (bit clock cycle), respectively, and an input signal of the delay element 221. An arithmetic circuit 223 for calculating the level difference from the delay signal from the delay element 222, a provisional determination circuit 224, a latch circuit 225, an inverting circuit 226 for inverting the signal from the latch circuit 225, and a switch circuit 227; The latch circuit 228 latches a signal output from the switch circuit 227 with the bit clock BLK, and a 0 generator 229 generates an error signal having a value corresponding to the provisional determination result 0.

The provisional decision circuit 224 is a digital multi-valued (eg, [+]) signal of the delay signal output from the delay element 221.
1], [0], and [-1]) are provisionally determined. The arithmetic circuit 223 calculates and outputs the resampling data on both sides of the resampling data input to the temporary determination circuit 224, that is, the level difference between the input resampling data of the delay element 221 and the output resampling data of the delay element 222. . The latch circuit 225 is "+1", which is the most probable data value of the temporary determination circuit 224.
Alternatively, the output signal of the arithmetic circuit 223 is held until a resampling point indicating “−1” is determined or a more probable resampling point indicating “+1” or “−1” is detected.

The switch circuit 227 includes a provisional determination circuit 224.
And outputs a signal from the inverting circuit 226 and the latch circuit 225, or a signal output from the 0 generator 229, based on the control signal. That is, the digital signal value of the delay signal output from the delay element 221 is provisionally determined in the provisional determination circuit 224, and the digital information signal value provisionally determined at that time is compared with the digital information signal value provisionally determined at that time by one resampling clock. A level difference is obtained.

For example, if a digital information signal waveform as indicated by I in FIG. 4A is obtained, "+1" is detected at the resampling timing a. In an ideal situation, "0" is detected as the value of the information signal before and after (adjacent on both sides) resampling timings a-1 and a + 1. As described above, the timing a-
The signal level difference at 1, a + 1 is 0 _a-1 −0 _{a + 1} =
It becomes "0" (at this time, the signal levels at each resampling timing are set to _0a-1 and _{0a + 1} ). 4A to 4C, the horizontal axis t indicates time, and the black circles indicate resampling data output from the interpolator 21.

This information signal is indicated by II in FIG.
Thus, a certain phase difference from the original digital signal waveform I
Assuming that it is delayed by θ, timings a-1, a
The values detected by +1 are shifted. As described below
Assuming that the value of the information signal at timing a is “+1”,
If it is determined, the signals at timings a-1 and a + 1
Level difference is 0_a-1-X_{a + 1}= "-X_{a + 1}". As well
In addition, as shown by III in FIG.
The digital signal waveform I by a certain phase difference θ
It is assumed that the timings a-1 and a + 1
Signal level difference is Y _a-1−0_a-1= "Y_{a + 1}".

The value of the signal level difference "-Xa _{+ 1} " or "Ya _-1 " is supplied as a phase error signal to the timing generator 24 through the loop filter 23 shown in FIG. Can be performed. When a is "-1", the polarity of the phase error may be inverted. However, in this case, it is necessary that “+1” or “−1” be correctly detected at the timing a.

Next, the operation of the temporary determination circuit 224 will be described. As shown in FIG.
Assume that a digital information signal 10001... Has been recorded by a magnetic recording system. Since a magnetic recording system and a transversal filter for waveform equalization, which will not be described in detail here, have a transfer characteristic of 1-D (D: delay operator of a bit period), 10 (-1) 001 (- 1) 0100
0 (-1) 001... Should be obtained.

Here, the transfer function of the magnetic recording encoding of the digital information signal by the partial response system is 1
/ (1-D) 2, which is 1 / ｛(1-D) (1+
D) It can be expressed as｝. Among them, 1-D can be substituted by the differential characteristic at the time of reproduction. That is, the signal to be reproduced is obtained by the processing of 1-D described above.
001 (-1) 01000 (-1) 001... Although not described in detail here, the information signal after the waveform equalization is processed and decoded by 1 + D (one-bit delay and addition). At this time, if (-1) is treated as 1, the original data is restored.

In the case of a digital information signal, especially in magnetic recording, since the transmission path has a differential characteristic such as 1-D, peaks in the same direction are not continuously detected.
For example, a digital information signal input as .00100... Is detected as... 001-10..., And intersymbol interference having a value of −1 occurs following an isolated pulse of +1.
Therefore, when the level of “+1” is determined twice by a certain resampling, the same “+1” is not detected before “−1” is resampled, so that any “+1” is not detected. Is noise.

Whether one of these "+1" is noise or true (or likely) "+1" is determined by using a maximum likelihood detection algorithm. This is a detection method for obtaining a probable value, and is based on the assumption that the signal component has a correlation and the noise component has no correlation. For example, if a resampling detects a level of "+1" and a resampling detects a higher level "+1" in the next resampling, the higher level is the more likely "+1" in this case. However, when something like "-1" is detected instead of the even higher level "+1", "+1" immediately before that is determined as a likely value.

Further, even if "+1" is detected at a certain resampling timing, and the next resampling timing is "-1", the lower resampling timing is likely to be "-1". If it is detected, the immediately preceding "-1" is regarded as noise and determined to be "0". The provisional determination circuit 224 detects the most probable levels “+1” and “−1” as described above. In other words, the level “+1” or “−1”
Is determined, the other values are processed as "0".

Therefore, noise is added to a value that should be "0" due to intersymbol interference between values before and after having a steep waveform, thereby increasing "+" from the conventional threshold level.
Even when erroneously determined as "1" or "-1", "0" can be determined. The provisional determination circuit 224 performs such provisional determination and outputs a phase error as follows.

It is assumed that the reproduced signal waveform is obtained as shown in FIG. In FIG. 5B, white circles indicate detection points (resampling data) by resampling.
As shown in FIG. 5B, when the reproduction signal is provisionally determined at predetermined timings in the order shown by circled alphanumeric characters, for example, the past resampling result for the timing is “−1”. Is determined, a certain level of comparison data (threshold) is set at the timing, as indicated by the dotted arrow in FIG. At this time, while detecting the next “−1” from the temporary judgment value “+1”, “+1”
Is set in the negative direction as indicated by the dotted arrow in the figure.

At the next resampling timing, since the detected level exceeds the comparison data of the timing, the level difference between the resampling data located on both sides of the timing, which is held by the latch circuit 225, is retained. Is output as phase error data corresponding to “+1”, and the level difference between the data at the resampling points located on both sides of the timing resampling point is the resampling value “−1” which will be determined next. "
Are stored for output of the phase error data corresponding to. That is, in order to update the value, the provisional determination circuit 2 of FIG.
24 outputs “H” to the latch circuit 225 as a control (CTL) signal.

At this time, the switch circuit 227 of FIG.
According to the control signal from the temporary determination circuit 224, the latch circuit 2
The data value (level difference between the resampling data located on both sides of the timing) output from 25 is selected and supplied to the latch circuit 228 for latching, and the output data of the latch circuit 228 is sent to the loop filter 23 in FIG. Output as phase error data.

At the next timing, the detected level is closer to "-1" than the timing value as shown in FIGS. 5B and 5C. The level difference of each data at the resampling point to be stored is stored for outputting the phase error data corresponding to the resampling value "-1" which will be determined next. That is, in order to update the value, the temporary determination circuit 224 sets “H” as the CTL signal to the latch circuit 22.
Output to 5 At this time, the switch circuit 227 of FIG.
Is a 0 generator 22 that outputs an error signal having a value corresponding to the temporary determination result 0 according to a control signal from the temporary determination circuit 224.
9 is selected and supplied to the latch circuit 228 for latching, and the output data of the latch circuit 228 is output to the loop filter 23 of FIG. 2 as a phase error signal.

At the next timing, the detected level is closer to "0" as compared with the timing level and does not exceed the timing comparison data.
Since the phase error data corresponding to the resampling value “−1” that will be determined next is still the level difference between the data at the resampling points located on both sides of the resampling point of the timing, the latch circuit 225 Is not updated, and the temporary determination circuit 224 outputs “L” as the CTL signal.
Is output. At this time, the switch circuit 227 selects an error signal having a value corresponding to the tentative judgment result 0 from the 0 generator 229 according to the control signal from the tentative judgment circuit 224 and supplies it to the latch circuit 228 to be latched. The output data of the latch circuit 228 is output to the loop filter 23 of FIG. 2 as a phase error signal.

At the next resampling timing, the detected level has exceeded the comparison data of the timing, so that the resampling points of the resampling points located on both sides of the resampling point of the timing, which are held by the latch circuit 225, are held. The level difference of each data is output as phase error data corresponding to "-1", and the level difference of each data of the resampling points located on both sides of the timing resampling point will be determined next. It is stored for outputting data corresponding to “+1”. That is, in order to update the value, the provisional determination circuit 2 of FIG.
24 outputs “H” to the latch circuit 225 as a CTL signal.

At this time, the switch circuit 227 selects the data value output from the inverting circuit 226 (the inverted value of the level difference between the resampling data located on both sides of the timing) according to the control signal from the temporary determination circuit 224. The data is supplied to the latch circuit 228 and latched, and the output data of the latch circuit 228 is output to the loop filter 23 of FIG. 2 as a phase error signal. As described above, a highly reliable phase error signal can be obtained with a minimum delay by performing sophisticated control using a temporary determination circuit using dynamic threshold setting (comparison data).

A resampling DPLL having such a configuration
FIG. 6 shows an eye pattern of a digital signal obtained by supplying the resampling data shown in FIG. 5D output from 15 to the equalizer 16 of FIG. 1 and performing waveform equalization processing. In the eye pattern shown in FIG. 6, the vertical axis represents level, and the horizontal axis represents time. As can be seen from FIG.
A digital signal without DC fluctuation due to accurate phase detection can be obtained.

As described above, in this embodiment, by using the resampling DPLL 15, a digital signal can be reproduced with a full digital configuration, and the analog VCO required in the conventional device can be eliminated.

Next, another embodiment of the phase detector 22 will be described. FIG. 7 shows a block diagram of another embodiment of the phase detector 22. 3, the same components as those of FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted. The phase detector 22 shown in FIG. 7 is characterized in that the output error signal of the arithmetic circuit 223 is branched into two and latch circuits 230 and 231 are provided on respective transmission paths leading to the switch circuit 227.

In this embodiment, the latch circuits 230 and 231 perform a latch operation based on the CTL signal from the provisional determination circuit 224 under the same control as in FIG. As a result, the provisional determination circuit 224 determines the resampling point indicating “+1” or “−1” as the most likely data value, or sets the resampling point indicating “+1” or “−1” as the more likely value. Until the detection, the amplitude errors at the resampling points adjacent to both sides of the determined resampling point and their inverted values are held in the latch circuits 231 and 230, and the latch circuits 231 and 230 are controlled according to the control of the temporary determination circuit 224. The switch circuit 227 selects an optimum value from the output of the 230 or 0 generator 229 and outputs it as a phase error signal.

Next, the threshold value used in the temporary determination circuit 224 will be described. In the above description of the embodiment, the dynamically set threshold value used in the provisional determination circuit 224, that is, the comparison data is assumed to be fixed at a certain value, but the level of the supplied signal or Of course, the magnitude may be adaptively varied according to the frequency characteristics. The details will be described below.

When the threshold value is increased, "+1" or "-"
Although it becomes difficult to detect “1” and becomes strong against noise, if the signal level of “+1” or “−1” of the supplied signal is too small (too dull), it cannot be detected and an error occurs. There is a possibility that it will be done. Conversely, if the threshold value is reduced, it becomes easier to detect "+1" or "-1", and even when the signal level of "+1" or "-1" of the supplied signal is too small (when it is too dull). , Can be detected correctly,
On the other hand, it is weak against noise, and there is a possibility that an error may also occur due to erroneous determination.

That is, the threshold value must be a value appropriate to some extent with respect to the amount of noise included in the signal and the signal level of "+1" and "-1" of the supplied signal. The signal level of "+1" or "-1" of the supplied signal is proportional to the level of the entire signal and also depends on the frequency characteristic. Since the frequency is high near the signal level of "+1" or "-1", it tends to be small when the high-frequency component of the signal is attenuated, and to be large when raised.

Basically, an automatic gain control circuit (AG
By supplying a signal whose level is controlled to some extent by C) to the phase detector 22 in the resampling DPLL, the setting of the threshold value does not need to be so strictly selected, but the magnitude of the signal reproduced from the recording medium is large. If the sheath frequency characteristics are clearly different, the following methods are conceivable in order to take more reliable measures.

(1) Means for detecting the magnitude (level) of the entire supplied signal is provided (for example, it can be realized by a peak hold circuit or the like). When the signal level is low, the threshold value is low, and when the signal level is high, the threshold value is low. Also increase the threshold.

(2) Means for detecting the frequency characteristic of the supplied signal (for example, by detecting two high and low frequency components,
This can be realized by comparing the level difference with a preset value, extracting high-frequency components and low-frequency components by filtering, and comparing the level difference with a preset value. ), The threshold is small when the high band of the signal is attenuated, and the threshold is increased when the signal is raised. With such a sophisticated control, a more reliable phase error signal can be obtained.

In each of the above embodiments, for example,
Although the present invention has been described as applied to a recording / reproducing apparatus for recording / reproducing a digital information signal such as a digital VTR, the present invention is not limited to the medium as long as it uses a transmission path for the digital information signal. Of course, it may be used for a signal transmitting / receiving device such as a disk recording / reproducing device, a communication modem, a ghost canceller, and the like. Further, it is a matter of course that the provisional determination circuit 224 may be used together with a Viterbi decoding circuit, for example, to obtain a more reliable reproduced digital information signal.

[0051]

As described above, according to the present invention,
The resampling data obtained from the reproduced digital signal by the resampling DPLL is supplied to the decoder through the equalizer, and the resampling data value most likely by the maximum likelihood detection is obtained as the phase error algorithm of the phase detector of the resampling DPLL. Provisionally determined,
Calculates the level difference of each data of the resampling points adjacent to both sides of the temporarily determined resampling data, and according to the temporarily determined value, the calculated level difference or a value obtained by inverting the polarity or a preset value. Is selected and output as a phase error signal, thereby using an analog VCO in which the output signal frequency is varied according to the phase error signal.
Even if the sampling frequency of the reproduced digital signal to be D-converted is not changed, a more accurate phase error signal can be obtained. This eliminates the need for an external analog VCO, which has been required in the past. It can be constituted by a digital circuit, so that the device can be downsized and the reliability for operation at a high frequency can be increased.

Further, according to the present invention, since the reliability of the phase error signal can be improved, the recorded information recorded at high density can be accurately reproduced using the partial response characteristic.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of an example of a resampling DPLL of a main part of FIG. 1;

FIG. 3 is a block diagram of an embodiment of the phase detector of FIG. 2;

FIG. 4 is a signal waveform diagram for explaining the operation principle of FIG. 4;

FIG. 5 is a signal waveform diagram for explaining the operation principle of FIG.

FIG. 6 is a diagram illustrating an example of an eye pattern of an output signal of the equalizer in FIG. 1;

FIG. 7 is a block diagram of another embodiment of the phase detector of FIG. 2;

[Explanation of symbols]

 Reference Signs List 15 resampling DPLL 16 equalizer 17 decoding circuit 21 interpolator 22 phase detector 23 loop filter 24 timing generator 221, 222 delay element 223 arithmetic circuit 224 temporary discriminating circuit 225, 228, 230, 231 latch circuit 226 inverting circuit 227 switch circuit 2290 generator

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (6)

[Claims] 1. A digital signal reproducing apparatus for decoding a transmitted digital information signal after performing phase synchronization control and waveform equalization, and decoding the transmitted digital information signal by A / D converting the input digital signal. A resampling DPLL is generated at a desired bit rate to generate resampling data, and a bit clock is extracted and supplied to a subsequent block. The resampling DPLL is provided with phase point data of the input digital signal. An interpolator that estimates resampling data by estimating the data value of the interpolated data, and temporarily determines the most probable data value by receiving the resampling data from the interpolator; The resampling data adjacent to both sides of the resampling data temporarily determined by the determination means Calculating means for calculating and calculating the level difference of each data of the ring point, and according to the value provisionally determined by the provisional determination means, an output signal from the calculation means or a signal whose polarity is inverted or a preset value. A phase error signal generating means for selecting and outputting as a phase error signal; a loop filter for integrating the phase error signal; and estimating a next data point phase of the output signal of the loop filter and extracting a bit clock; A digital signal reproducing apparatus comprising: a timing generator that inputs the obtained data phase information and the bit clock to the interpolator. 2. The digital processing device according to claim 1, wherein said provisional determination means provisionally determines a most probable data value by dynamically setting a threshold value used for said maximum likelihood detection. Signal playback device. 3. The calculating means determines the resampling point at which the provisional discriminating means indicates “+1” or “−1” as the most likely data value, or “+1” or “−1” more likely. Until the resampling point indicating `` is detected, the level difference of each data of the resampling point adjacent on both sides of the resampling point is held, and the level difference or its polarity is inverted according to the result of the tentative determination. 2. The digital signal reproducing apparatus according to claim 1, wherein a value according to a value or a provisional determination result 0 is selected. 4. The arithmetic means determines the resampling point indicating "+1" or "-1" as the most probable data value by the temporary discriminating means, or "+1" or "-1" more likely. Until a resampling point indicating `` is detected, a level difference between data at resampling points adjacent to both sides of the resampling point and a value obtained by inverting the polarity of the resampling point are held. 2. The digital signal reproducing apparatus according to claim 1, wherein a value obtained by inverting the level difference or its polarity or a value according to the provisional determination result 0 is selected. 5. The digital signal reproducing apparatus according to claim 2, wherein said temporary discriminating means adaptively changes the magnitude of said threshold value according to characteristics of said transmitted digital information signal. apparatus. 6. The digital signal reproducing apparatus according to claim 1, wherein said digital information signal is a digital information signal transmitted by a partial response system using intersymbol interference.