JP2001077116A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reliable groove wiring technology, wherein erosion or dishing in a polishing process is suppressed, related to such groove wiring technology as Ta or W material is used for a barrier layer, using copper (Cu) for wiring material. SOLUTION: A process where an interlayer insulating film 15 is formed, a process where a recessed part 17 of the inter-layer insulating film 15 in which a wiring material layer 22 (conductor) is embedded is formed of, for example, a wiring channel 18 and connection hole 19, and a process where a barrier layer 21 is formed on the internal surface of the recessed part 17 as well as on the surface of the interlayer insulating film 15 and then the wiring material layer 22 is formed on the barrier layer 21 so as to fill the recessed part 17, are provided. Here, before the barrier layer 21 is formed, a plurality of channels 16 are formed on the surface of the interlayer insulating film 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a trench wiring is formed.

[0002]

2. Description of the Related Art As demands for higher speed and finer LSI have been increasing, trench wiring technology using copper has been actively studied.
Some have been put to practical use. Copper wiring has lower resistance and better electromigration resistance than conventional aluminum-based wiring. Further, by forming the trench wiring, the surface of the interlayer insulating film can be flattened and the fine wiring can be formed relatively easily.

[0003] The trench wiring is formed by the following process. That is, as shown in FIG. 4A, the groove 112 is formed in the interlayer insulating film 111 made of an oxide film. Next, as shown in FIG. 4B, after forming a barrier layer 113 on the inner surface of the groove 112, the groove 1 is formed via the barrier layer 113.
The copper of the wiring material layer 114 is buried in the inside of the substrate 12. In this step, since the barrier layer 113 is formed by, for example, sputtering or a CVD method, the barrier layer 113 is also formed on the surface of the interlayer insulating film 111 due to its film formation characteristics. After that, chemical mechanical polishing (hereinafter simply called polishing)
Wiring material layer 1 deposited on portions other than groove 112 by, for example,
14, the barrier layer 113 is removed, and as shown in FIG. 4C, the wiring 115 is formed only in the groove 112 while leaving the wiring material layer 114 via the barrier layer 113.

[0004] By the way, copper has a property that it is easily diffused into an interlayer insulating film (oxide film) by heat treatment. Therefore, it is necessary to provide a barrier layer for preventing the diffusion of copper between the copper and the oxide film. As a material of the barrier layer,
Titanium nitride, which has been used in conventional aluminum-based wiring, is generally used because it is easy to introduce and easy to polish (polishing rate is almost equal to copper). On the other hand, as the barrier properties, tantalum-based materials such as tantalum (Ta), tantalum nitride (TaN), and tantalum nitride silicide (TaSiN);
Tungsten-based materials such as tungsten (W), tungsten nitride (WN), and tungsten nitride silicide (WSiN) are superior.

[0005]

However, when a tantalum-based material or a tungsten-based material is used for the barrier layer, the polishing rate of copper is higher by about one order of magnitude than those materials, and therefore, when the trench wiring is formed. In the copper polishing step, copper polishing also proceeds during polishing of the barrier layer. As a result, as shown in FIG. 5A, erosion occurs in a region where the area of the wiring 115 is large, particularly in a region where the line width of the wiring 115 is large. In addition, as shown in FIG.
In the region where the density is high, dishing occurs. As a result, there arises a problem that the wiring resistance is increased and the variation is deteriorated, and the reliability of the wiring is significantly reduced.

To solve the above problem, a two-step polishing method in which the slurry is changed and the barrier layer is polished when the polishing of copper is completed has been studied. However, in the two-step polishing, the end point of copper polishing is determined. It is difficult to use such a slurry, and the use of a plurality of slurries increases the process cost.

[0007]

SUMMARY OF THE INVENTION The present invention is directed to a method of manufacturing a semiconductor device which has been made to solve the above-mentioned problems, that is, a step of forming an interlayer insulating film, and a step of embedding a conductor in the interlayer insulating film. Forming a conductive layer on the barrier layer so as to fill the recess after forming a barrier layer on the inner surface of the recess and the surface of the interlayer insulating film. In the manufacturing method, a step of forming a plurality of grooves in a surface of the interlayer insulating film before forming the barrier layer is provided.

In the above method of manufacturing a semiconductor device, a plurality of grooves are formed on the surface of the interlayer insulating film before forming the barrier layer. Therefore, the barrier layer is formed on the interlayer insulating film in a region where the plurality of grooves are formed. Will be formed. Then, after depositing a wiring material layer, an extra wiring material layer on the interlayer insulating film,
When performing the step of removing the barrier layer by polishing, the barrier layer formed in the place with unevenness due to the groove formed on the surface of the interlayer insulating film is easily polished, and the polishing layer with copper is selected. The ratio does not change. Therefore, erosion hardly occurs in a region having a large wiring area,
In a region where the wiring density is high, dishing hardly occurs.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One example of an embodiment according to the present invention will be described with reference to FIG.

[0010] As shown in FIG.
After a semiconductor element (not shown) such as a transistor and a capacitor is formed on a semiconductor substrate (not shown) by processing, an insulating film (not shown) covering them is formed to constitute the substrate 10. Next, a first wiring 11 is formed on the substrate 10 by an existing wiring forming technique, and then an interlayer insulating film 12 covering the first wiring 11 is formed. The interlayer insulating film 12 is formed by depositing silicon oxide to a thickness of, for example, 600 nm by a plasma CVD method, for example. Subsequently, an inorganic mask 13 is formed on the interlayer insulating film 12 by depositing silicon nitride to a thickness of 50 nm by, for example, a plasma enhancement CVD method. By forming the inorganic mask 13 from silicon nitride, it also has an effect of preventing copper from being oxidized and diffused in a subsequent heat process.

Next, by a normal resist coating technique,
After forming a resist film (not shown), a hole pattern for opening a connection hole in the resist film is formed by a normal lithography technique to form a resist mask (not shown). Using the resist mask, the inorganic mask 13
Is etched to form an opening 14. The opening 14 has a diameter of, for example, 0.3 μm. After that, the resist mask is removed.

Next, as shown in FIG. 1B, an interlayer insulating film 15 between wirings is formed on the inorganic mask 13 and the opening 14 to a thickness of, for example, 450 nm. The thickness of the interlayer insulating film 15 is set in consideration of the erosion amount in the polishing step. Here, the erosion including a polishing margin of a wiring thickness of 400 nm and a 20 nm was 50 nm.

Next, as shown in FIG. 1C, after forming a resist film (not shown) by a normal resist coating technique, a groove pattern is formed in the resist film by a normal lithography technique. Resist mask (not shown)
To form By using the resist mask, the upper layer of the interlayer insulating film 15 between the wirings is etched to form a plurality of grooves 16 in, for example, a stripe shape. The groove 16 has, for example, a depth of 0.
It is formed by 1 μm 0.1 μm line and space.
After that, the resist mask is removed. The groove 16 may be formed in a surface area of the interlayer insulating film 15 excluding the portion where the wiring groove is formed as shown in the figure, or may be formed over the entire surface of the interlayer insulating film 15.

Next, as shown in FIG. 1D, after a resist film (not shown) is formed by a normal resist coating technique, a wiring groove is formed in the resist film by a normal lithography technique. A resist mask (not shown) having the wiring groove pattern formed thereon is formed. Using the resist mask, the interlayer insulating film 15 between the wirings is etched to form a wiring groove 18 which becomes a part of the concave portion 17. The wiring groove 18 is formed to have a width of, for example, 0.5 μm.
In this etching, the inorganic mask 13 serves as an etching stopper, and determines the bottom of the wiring groove 18.

Next, the above etching is advanced by using the inorganic mask 13 as an etching mask, and the interlayer insulating film 12 is etched to form a connection hole 19 reaching the first wiring. In this way, a connection hole 19 which is a lower portion of the concave portion 17 is formed at the bottom of the wiring groove 18. After that, the resist mask is removed. As described above, the recess 17 includes the wiring groove 18 and the connection hole 19 formed at the bottom thereof.

Next, after performing a pre-heating process, a sputter etching process is performed. In this preheating treatment, for example, heating was performed from the back side of the substrate 10 using a gas heating method. As an example, the heat treatment was performed by blowing argon gas at 500 ° C. at a pressure of 1 kPa onto the back surface of the substrate for 1 minute. In the sputter etching process, as shown in FIG. 1 (5), the convex portions 15c formed on both sides of the groove 16 formed on the interlayer insulating film 15 are etched to sharpen the cross-sectional shape. . The sputter etching conditions are, for example, a DC power of 1.0 kW,
Argon (for example, a supply flow rate of 50 scc)
m), the pressure of the sputter etching atmosphere was 0.2 Pa, the temperature was 200 ° C., and the processing time was 30 seconds. Such sharpening of the cross-sectional shape facilitates polishing of the barrier layer formed on the surface.

Next, the wiring groove 18 and the connection hole 19 are formed.
The barrier layer 21 is formed on each of the inner surfaces. At this time, the barrier layer 21 is also formed on the surface of the interlayer insulating film 15, that is, on the inner surface of the groove 16.
Is formed. The barrier layer 21 is formed by depositing tantalum nitride to a thickness of 50 nm by, for example, DC magnetron sputtering. This film formation condition is, for example,
Argon (for example, a supply flow rate of 50 scc)
m) and nitrogen (for example, the supply flow rate is 35 sccm), the pressure of the film formation atmosphere was set to 0.4 Pa, the film formation temperature was set to 200 ° C., and the DC power was set to 12 kW.

The barrier layer 21 is made of tantalum nitride (T
aN), but other materials such as tantalum (Ta), tantalum-based materials such as tantalum nitride silicide (TaSiN), tungsten (W), tungsten nitride (WN), and tungsten nitride silicide ( WSi
It is also possible to use a tungsten-based material such as N). Alternatively, the barrier layer 21 can be formed of a laminated film in which these materials are appropriately combined.

Subsequently, as shown in FIG. 1 (6), following the formation of the barrier layer 21, a wiring material layer (conductor) 22 is formed by, for example, DC magnetron sputtering.
For example, it is formed by depositing copper to a thickness of 1.0 μm. As an example of the film forming conditions, as a process gas, argon (for example, a supply flow rate is set to 100 sccm) is used as the process gas, the pressure of the film forming atmosphere is set to 0.4 Pa, the film forming temperature is set to 200 ° C., and the DC power is set to 15 kW. Here, the wiring material layer 22
Is formed by depositing copper, but may be formed by a copper alloy such as a copper-zirconium alloy.

When copper is formed under the above-described film forming conditions, the cavity 2 is formed inside the wiring groove 18 and the connection hole 19.
3 results. Therefore, as shown in FIG. 1 (7), for example, the substrate 10 is heated in a high vacuum atmosphere, and the wiring material layer 2 is formed inside each of the wiring groove 18 and the connection hole 19 by the reflow method.
2 copper is embedded. The reflow condition is 500
This is performed by blowing argon gas at a temperature of 1.0 ° C. from the back surface of the substrate 10 at a pressure of 1.0 kPa for 1 minute.

In the above-described embodiment, the wiring material layer 22 is formed in the wiring groove 18 and the connection hole 19 by using the film formation by the DC magnetron sputtering method and the embedding by the reflow method. Alternatively, a high-pressure reflow method can be used. The wiring groove 18
The embedding of the wiring material layer 22 in the connection holes 19 can also be performed by an electrolytic plating method.

For example, the high-pressure reflow conditions are as follows.
The substrate temperature was set to 450 ° C and the high-pressure reflow atmosphere was set to 7
The atmosphere was set to an argon atmosphere of 0 MPa, and the reflow time was set to 1 minute. Thus, the wiring material layer 22 is pressed into the wiring groove 18 and the connection hole 19 by applying a high voltage to the wiring material layer 22.

In order to bury copper by the electrolytic plating method, the barrier layer 21 is first formed, and then the adhesion layer is formed by DC magnetron sputtering.
For example, copper is formed to a thickness of 200 nm. As an example of the film formation conditions, as an example, argon (a supply flow rate is set to 100 sccm) as a process gas, a pressure of a film formation atmosphere is 0.4 Pa, a film formation temperature is 200 ° C., and a DC power is 1
It was set to 5 kW.

Thereafter, the wiring material layer 2 is formed by electrolytic plating.
2 is formed to a thickness of, for example, 1.0 μm. The electroplating conditions are, for example, as follows.
O ₄ ) [67 g / dm ³ ] and sulfuric acid (H ₂ SO ₄ ) [17
0 g / dm ³ ] and hydrochloric acid (HCl) [70 ppm], a surfactant as an additive, and a plating solution temperature of 20 g / dm ³ ].
° C and the applied current were set to + 9A.

After that, the extra wiring material layer 22 and the barrier layer 21 on the interlayer insulating film 15 are removed by polishing (for example, chemical mechanical polishing), and the wiring groove 18 is formed as shown in FIG. A second wiring 24 made of a wiring material layer 22 is formed inside the semiconductor device via a barrier layer 21, and a plug 25 made of the wiring material layer 22 is formed inside the connection hole 17 via the barrier layer 21. At the time of the above polishing, the barrier layer 21 is formed on the surface of the interlayer insulating film 15 on which fine irregularities are provided, so that it is in a state of being easily polished. As a result, the polishing selectivity of tantalum nitride to copper is reduced, and the wiring material layer 22 and the barrier layer 21 are polished uniformly.

The polishing conditions are, for example, a slurry containing alumina to which hydrogen peroxide solution is added, a polishing pad having a laminated structure of a nonwoven fabric and an independent foam, and a polishing pressure of 100 g / cm. ² , the rotation speed of the polishing platen is 30 rpm, the rotation speed of the polishing head is 30 rpm,
The flow rate of the polishing liquid was set at 100 cm ³ / min, and the temperature of the polishing atmosphere was set at 25 ° C. to 30 ° C.

In order to form a multilayer wiring, the steps from the step of forming the interlayer insulating film 12 to the step of polishing the wiring material layer 22 and the barrier layer 21 described in the above (1) to (8) are repeated. Good. As a result, as shown in FIG. 2, the second wiring 24 is formed in the interlayer insulating film 12 and the interlayer insulating film 15 through the plug 25 connected to the first wiring 11.
Is formed, and a third wiring 54 is formed in the interlayer insulating film 42 and the interlayer insulating film 45 via a plug 55 connected to the second wiring 24.

In the method of manufacturing a semiconductor device, a plurality of grooves 1 are formed on the surface of the interlayer insulating film 15 before the barrier layer 21 is formed.
By forming 6, the barrier layer 21 is formed on the interlayer insulating film 15 in the region where the plurality of grooves 16 are formed. After that, after the wiring material layer 22 is deposited, a step of removing the excess wiring material layer 22 and the barrier layer 21 on the interlayer insulating film 15 by polishing is performed.
The barrier layer 21 formed in a place having irregularities by the groove 16 formed on the surface of the surface 5 is easily polished,
The polishing selection ratio of the wiring material layer 22 to copper hardly changes. Therefore, erosion hardly occurs in a region having a large wiring area, and dishing hardly occurs in a region having a high wiring density.

In the above embodiment, as shown in FIG. 3A, a plurality of grooves 16 are formed in the surface of the interlayer insulating film 15 in a stripe pattern. For example, as shown in FIG. Alternatively, a plurality of, for example, 0.1 μm square island-shaped patterns 32 may be formed in the surface of the interlayer insulating film 15 by forming grooves 31 having a width of, for example, 0.1 μm vertically and horizontally.

Although not shown, a region where the grooves 16 are formed in a stripe pattern and a region where the grooves 31 are formed in a lattice pattern may be formed.

In the above embodiment, the case where the trench wiring and the connection hole are formed by the dual damascene method has been described.
The method of forming a plurality of grooves on the surface of the interlayer insulating film before forming the barrier layer 21 of the present invention can be applied to the following cases.

The present invention can be applied to a manufacturing method in which a barrier layer and a conductive layer are buried in connection holes formed in an interlayer insulating film, and thereafter, unnecessary conductive layers and barrier layers on the interlayer insulating film are removed by polishing.

The present invention can be applied to a manufacturing method in which a barrier layer and a conductive layer are buried in a wiring groove formed in an interlayer insulating film, and then the unnecessary conductive layer and the barrier layer on the interlayer insulating film are removed by polishing.

The groove 1 occupying the surface of the interlayer insulating film 15
If the area ratio of No. 6 is referred to as an area ratio, it is preferable that the area ratio be formed to be about 40% to 60%. On the other hand, if the area ratio is out of the above range, a sufficient polishing effect of the barrier layer 21 cannot be obtained.

[0035]

As described above, according to the present invention,
Since a plurality of grooves are formed on the interlayer insulating film and a barrier layer is formed on the surface thereof, the removal of the barrier layer is facilitated in the step of polishing the barrier layer. Thereby, the polishing selectivity between the wiring material layer and the barrier layer is substantially reduced, and the wiring material layer and the barrier layer can be polished more uniformly. As a result, erosion hardly occurs in a region where the wiring area is large, and dishing hardly occurs in a region where the wiring density is high. Therefore, a wiring having a desired wiring cross section can be formed, and the wiring resistance increases. Therefore, it is possible to form a trench wiring having a small variation in wiring resistance.

[Brief description of the drawings]

FIG. 1 is a manufacturing process sectional view showing an embodiment according to the present invention.

FIG. 2 is a schematic configuration sectional view showing a multilayer wiring structure.

FIG. 3 is a schematic perspective sectional view illustrating a groove shape formed on the surface of an interlayer insulating film.

FIG. 4 is a cross-sectional view of a manufacturing process showing a conventional manufacturing method.

FIG. 5 is an explanatory diagram of a problem.

[Explanation of symbols]

Reference numeral 15: interlayer insulating film, 16: groove, 17: concave portion, 21: barrier layer, 22: wiring material layer (conductor)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/90 C F term (Reference) 4M104 BB17 BB18 BB27 BB28 BB32 BB33 CC01 DD37 DD61 DD75 FF17 FF18 FF22 HH12 5F033 HH11 HH12 HH19 HH21 HH28 HH30 HH32 HH33 HH34 JJ11 JJ12 JJ19 JJ21 JJ28 JJ30 JJ32 JJ33 JJ34 KK11 KK12 KK19 KK21 KK28 KK30 KK32 KK33 KK34 MM02 MM12 MM13 NN06 Q08 Q14 Q07 Q48

Claims (4)

[Claims] A step of forming a recess in which a conductor is embedded in the interlayer insulating film; and a step of forming a barrier layer on an inner surface of the recess and a surface of the interlayer insulating film. Forming a conductor on the barrier layer so as to fill the barrier layer. Forming a plurality of grooves in the surface of the interlayer insulating film before forming the barrier layer A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein a side wall of the groove is formed on an inclined surface. 3. The method according to claim 1, wherein the recess comprises a wiring groove, a connection hole, or a wiring groove and a connection hole. 4. A groove formed on a surface of the interlayer insulating film,
2. The device according to claim 1, wherein the device is formed in a stripe shape, a grid shape, or a stripe shape and a grid shape.
The manufacturing method of the semiconductor device described in the above.