JP2001057434A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fabricate an active matrix circuit without increasing the number of steps by forming a source line, a line on the extension thereof or an electrode covering a channel forming region thereby shielding the channel forming region from light. SOLUTION: A silicon oxide film 203 or a silicon nitride film is formed as an underlying film on the surface of a glass substrate 200 and a thin film semiconductor 201 is formed as an active layer 202 of crystallized semiconductor of a thin film transistor. A crystallized silicon semiconductor thin film is patterned with the size of the active layer of the thin film transistor. Subsequently, polysilicon doped with a metal, e.g. aluminum, or phosphorus is deposited and patterned to form a gate electrode 107. Source and drain regions 104, 106 are then implanted with phosphorus ions using the gate electrode 107 as a mask in order to convert then into N type. Thereafter, a silicon oxide film 107 is formed as an interlayer insulation film and patterned for boring and contact parts 108, 109 are formed by metallization. Finally, a source electrode line 112 is provided to cover a channel forming region 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used for an electro-optical device such as a liquid crystal display device.

[0002]

2. Description of the Related Art In an electro-optical device represented by an active matrix type liquid crystal display device, a thin film transistor (referred to as a TFT) is used as a driving element or a switching element.
Is known. A thin film transistor is formed by forming a thin film of a semiconductor (generally a silicon semiconductor) on a glass substrate or the like by a gas phase method and using the thin film semiconductor. This thin film transistor is also used for an image sensor and the like.

FIG. 4 shows a top view and a cross-sectional view of one pixel portion of an active matrix circuit using a thin film transistor according to the prior art. FIG. 4A is a cross-sectional view, and shows a cross-section indicated by AA ′ in the top view shown in FIG. 4B. A thin film transistor whose cross section is shown in FIG.
01, a semiconductor active layer made of amorphous silicon or crystalline silicon provided with a source region 402, a channel formation region 403, and a drain region 404 provided on
Gate insulating film 40 made of silicon oxide or silicon nitride
5, an interlayer insulating layer 407 made of silicon oxide, a drain contact portion 412, a source contact portion 411, a drain electrode 410, and a transparent conductive film (ITO or the like) 408 connected to the drain electrode 410 to form a pixel electrode. (In the operation of the TFT, the above-mentioned source / drain relationship may be reversed.)

[0006] The source region 402 of the thin film transistor shown in FIG. 4A is connected to a source line 409 via a source contact portion 411. Gate electrode 406 is connected to gate line 413. Generally, the source line and the gate line are perpendicular to each other, but may not be so. Gate electrode 406 and gate line 413 are generally formed of a metal such as aluminum or a semiconductor such as polycrystalline silicon to which phosphorus is added.

FIG. 4 shows a single pixel,
Actually, an active matrix circuit is formed by arranging at least one pixel as shown in FIG. 4 at an intersection of a source line and a gate line, and an active matrix substrate on which the active matrix circuit is formed, a counter substrate, and A liquid crystal panel is formed by enclosing a liquid crystal material between the two. As a liquid crystal display device using a liquid crystal panel having such a configuration, (1) a light (backlight) is applied to the liquid crystal panel to perform liquid crystal display. (2) A strong light source is applied to the liquid crystal display panel, and light transmitted through the liquid crystal panel is projected on a screen to capture an image. (Liquid crystal projector) (3) A reflection plate is disposed on the back side of the liquid crystal display panel, and display is performed by reflected light of external light. There is such a method.

[0006] When the method (1) or (2) is employed among the above methods and light is irradiated from the glass substrate side, it is necessary to shield the active layer, particularly the channel forming region, from the irradiated light. This is because the active layer (semiconductor layers indicated by 402 to 404 in FIG. 4) is formed of crystalline silicon such as amorphous silicon or polycrystalline silicon. Generally, when a silicon semiconductor is irradiated with light, its resistance changes. In particular, when amorphous silicon or crystalline silicon is used, dangling bonds exist in the film, and the electric characteristics thereof are significantly changed by the irradiation of strong light. In addition, although an intrinsic semiconductor is used for a channel formation region, the channel formation region is irradiated with light because the resistance change due to light is larger than that of an N-type or P-type semiconductor used for a source / drain. That was something we had to avoid.

A thin film transistor (top gate type T) having a structure in which the gate electrode shown in FIG.
FT), as shown at 414, the gate electrode 4
When light irradiation is performed from above the gate electrode 406,
May be considered as a mask, so that light does not enter the channel formation region 403. However,
Actually, the irradiated light 414 goes around the gate electrode 406, and a part of the light enters the channel formation region 403.
The conductivity of the channel formation region changes due to light irradiation,
Its characteristics will change.

That is, it is impossible to completely prevent light from entering the channel forming region by using only the gate electrode. This was remarkable when the channel formation region and the gate electrode were formed in a self-aligned (self-aligned) manner. In order to solve this problem, it is useful to provide a light-shielding layer or a light-shielding film separately. However, in this case, there is a problem that the number of manufacturing steps increases.

[0009]

SUMMARY OF THE INVENTION The present invention relates to a thin film transistor as shown in FIG.
In particular, an object is to realize a structure in which light is not irradiated to a channel formation region or light does not enter without increasing the number of manufacturing steps. In particular, the present invention is effective for an active matrix circuit having a thin film transistor in which a source / drain is formed by a self-alignment process in which an overlap between a gate electrode and a source / drain is extremely small.

[0010]

According to the present invention, in an active matrix circuit, a source line or a wiring or an electrode extending from the source line or the source line (the two lines are not clearly distinguishable) is used to shield a channel formation region from light. A source line or a wiring or an electrode extending from the source line is formed so as to cover the channel formation region. Since the channel formation region is included in the portion where the gate electrode and the semiconductor active layer overlap, it is almost synonymous to form a source line or an extension wire / electrode over such a region. In the above structure, examples of the substrate having an insulating surface include a glass substrate, a plastic substrate, and a metal substrate or a semiconductor substrate on which an insulating film is formed.

FIG. 2D shows an example of a structure in which the source line of the thin film transistor or the wiring / electrode on the extension thereof is formed so as to cover at least the channel forming region of the thin film transistor. be able to. FIG. 2D shows the source region 1 of the thin film transistor.
A configuration is shown in which an electrode / wiring 112 of a source line connected to the contact portion 104 by a contact portion 108 covers the channel formation region 105. That is, in FIG. 2D, the electrode wiring 112 is shown.
Shows a configuration functioning together with the gate electrode 107 as a light-shielding film of the channel formation region 105 provided thereunder.

Incidentally, it may be considered that a similar configuration can be realized by using a wiring / electrode connecting the pixel electrode 103 and the drain 103. However, in this case, the parasitic capacitance between the pixel electrode and the gate electrode increases, and a change in the potential of the gate line affects the pixel electrode, causing a significant obstacle in the operation of the active matrix.
(For example, Norihisa Ono et al., Flat Panel Display '91, p109) On the other hand, although the capacitive coupling due to the parasitic capacitance between the source line and the gate line hinders the operation speed of the thin film transistor as in the present invention, it is difficult to reduce the pixel speed. Since there is no effect on the potential, there is no problem in displaying images. In addition, according to the present invention, the parasitic capacitance caused by the overlap of the source wiring on the gate electrode is originally 10 times or less the parasitic capacitance at the intersection of the source line and the gate line of the active matrix. No.

FIG. 1A shows a specific top view of the above-described structure whose cross section is shown in FIG. FIG. 1 (B)
FIG. 2 is a circuit diagram of FIG. As is clear from FIG. 1A, the pixel electrode 103 is connected to the drain region 10
6, the wiring is not structured to cover the channel formation region. On the other hand, the extension 112 of the source line connected to the source region 104 of the thin film transistor via the contact 108 is formed to cover the channel formation region (that is, the portion where the gate electrode 107 and the semiconductor active layer overlap). Channel formation region 105
Function as a light shielding layer.

[0014]

[Function] The source (or drain) of a thin film transistor
The configuration in which the wiring / electrode connected to the electrode functions as a light-blocking layer in the channel formation region solves the problem that the characteristics of the thin film transistor are changed or deteriorated by light irradiation from the electrode side. can do. Further, the wiring / electrode connected to the other drain (or source) is connected to the pixel electrode.

When a liquid crystal display panel is constructed according to the present invention, light is irradiated from above the active matrix substrate, that is, from the light source, the counter substrate and the active matrix substrate are arranged. is necessary. When light is irradiated from below the active matrix substrate (the back side of the thin film transistor), the light-shielding effect of the present invention is completely lost.

[0016]

[Embodiment 1] A schematic top view of this embodiment is shown in FIG.
It is shown in (A). FIG. 1B is a circuit diagram thereof. FIG. 1 shows one pixel electrode portion of an active matrix type liquid crystal display device. FIG. 1A shows a pixel electrode 103 provided in a pixel, a source region 104, a channel formation region 105, and a drain region 10 which constitute a switching thin film transistor connected to the pixel electrode.
6, a source line 102 connected to a source region 108 via a contact portion 108, a gate electrode 107 provided on a channel region 105 via a gate insulating film (not shown), An extended gate line 101 is shown.

FIG. 1B shows a thin film transistor 110 and a drain region 10 of the thin film transistor 110.
6 (actually connected via a contact 109 as shown in FIG. 7A), and a liquid crystal 111 to which an electric field is applied from the pixel electrode 103 is shown.

FIG. 2 is a sectional view taken along the line BB 'in FIG.
It is shown in (D). In the configuration shown in this embodiment, FIG.
2A and 2D, the source electrode wiring 10
2 is configured to cover more than half of the thin film transistor. The source line and the gate line are made of aluminum or other metal, a semiconductor, or a laminate thereof.

When the structure shown in FIG. 1 or FIG. 2 is adopted, light irradiated from the gate electrode side is shielded by the extended source electrode wiring 112, so that light is irradiated to a region more than half of the thin film transistor. It is possible to adopt a configuration that does not cause any problem. In particular, the gate electrode 1 is formed in the channel formation region 105.
07 can be blocked.

The steps for manufacturing the thin film transistor shown in FIGS. 1 and 2D are shown in FIGS. Hereinafter, a manufacturing process of a TFT arranged in one pixel included in a matrix will be described. Of course, it goes without saying that many other pixels arranged in a matrix have the same configuration.

First, a glass substrate 200 is prepared. As the substrate, any substrate having an insulating surface can be used. For example, a semiconductor substrate or a metal substrate having an insulating film formed on its surface can be used.

On the surface of the glass substrate 200, although not shown, a silicon oxide film or a silicon nitride film is formed as a base film. This is to prevent diffusion of impurities from the glass substrate and to relieve stress during heat treatment.

Then, a thin film semiconductor 201 constituting an active layer of the thin film transistor is formed. Here, the plasma C
An amorphous silicon thin film is formed to a thickness of 1000 ° by a VD method or a low pressure thermal CVD method. (FIG. 2 (A)

In this embodiment, since a crystallized semiconductor layer is used as the active layer, the amorphous silicon thin film 201 is crystallized here. The crystallization is 60
The heat treatment (thermal annealing) at 0 ° C. for 12 hours is performed in an inert atmosphere. A small amount of an element that promotes crystallization, such as nickel, may be added to promote crystallization.

The crystallization step may be performed by irradiating a laser beam or an equivalent strong light. further,
The silicon film crystallized once by thermal annealing may be irradiated with laser light or strong light equivalent thereto. In addition, as long as the characteristics of the thin film transistor are low, amorphous silicon may be used.

Next, the silicon semiconductor thin film crystallized to the size of the active layer of the thin film transistor is patterned. Thus, an active layer 202 of the thin film transistor is formed. Then, a silicon oxide film 203 serving as a gate insulating film is
Is formed by plasma CVD or sputtering.

Next, a gate electrode 107 is formed by forming polycrystalline silicon doped with a metal such as aluminum or phosphorus or phosphorus, and performing patterning. At this time, the gate wiring 101 (see FIG. 1A) is also formed at the same time.

Then, phosphorus ions are implanted, and the source 1
04 and the drain 106 are formed. At this time, the gate electrode 107 serves as a mask, and phosphorus ions are implanted into the regions 104 and 106, and no phosphorus ions are implanted into the region 105. Thus, the channel formation region 105 is also formed at the same time. The source and the drain become N-type due to the implantation of phosphorus. To make the source / drain P-type, for example,
Boron may be implanted. (Fig. 2 (C))

Next, annealing is performed by irradiating a laser beam for annealing the portion damaged in the previous ion implantation and activating the implanted impurity ions. Here, Kr
An F excimer laser is used. This step may be performed by thermal annealing at a low temperature of about 600 ° C. (Figure 2
(C))

Next, contact portions 108 and 109 are formed by forming a silicon oxide film 107 as an interlayer insulating layer, further performing drilling patterning, and forming a metal wiring. As shown in FIG. 1A, the wiring pattern has a structure in which a source wiring portion indicated by 112 extending from the source line 102 covers at least half of the thin film transistor.

It is particularly important that the source wiring 112 is provided so as to cover the upper part of the channel formation region 105. By adopting such a configuration, a configuration can be employed in which light irradiated from the gate electrode side is not irradiated to the channel formation region 105, and there is no change or deterioration in characteristics of the thin film transistor due to light irradiation. Can be.

[Embodiment 2] This embodiment relates to a thin film transistor having a structure in which aluminum is used as a gate electrode, and an oxide layer formed by an anodic oxidation process is formed on the side surface and the upper surface of the gate electrode to increase the breakdown voltage. FIG.
Next, a manufacturing process of this embodiment will be described. First, the glass substrate 30
A silicon oxide film as a base film (not shown)
The film is formed to a thickness of Å. Next, the amorphous silicon thin film 3
01 is formed by a plasma CVD method or a low pressure thermal CVD method. (FIG. 3 (A))

Next, the amorphous silicon film 301 is crystallized by performing a heat treatment at 600 ° C. for 12 hours. Then, the size of the active layer of the thin film transistor is patterned to form an active layer 302 made of a crystalline silicon thin film. Then, a silicon oxide film 303 functioning as a gate insulating film is formed to a thickness of 1000 ° by a plasma CVD method or a sputtering method. (FIG. 3
(B))

Next, a film containing aluminum as a main component and serving as a gate electrode is formed to a thickness of 5000 °. When 0.1 to 0.5% by weight, for example, 0.2% by weight, of scandium (Sc) was mixed with aluminum, generation of hillocks in a subsequent anodic oxidation step or the like could be prevented.

Thereafter, the aluminum film is etched to form a gate electrode 304. Then, the oxide layer 306 is subjected to anodic oxidation in a substantially neutral electrolytic solution using the gate electrode 304 as an anode, so that
Å, for example, a thickness of about 2000Å. At that time, the voltage applied to the gate electrode is about 120 V at the maximum. This oxide layer preferably has a sufficient withstand voltage. Therefore, a sufficiently dense oxide film is desired. The anodic oxide film produced under the above conditions is called a barrier type anodic oxide, and has a withstand voltage of about 90% of the maximum applied voltage (in this case, 120 V). (FIG. 3
(C))

Next, phosphorus ions are implanted into the region 306 and the region 307 to form a source 306 and a drain 3.
07 is formed. At this time, 308 is formed as a channel forming region in a self-aligned manner. Unlike the case of the first embodiment, the thickness of the anodic oxide film 305 is
The source / drain is in a so-called offset state in which the source / drain has moved away from the gate electrode. Such an offset state is effective in reducing a remarkable leak current in the thin film transistor. Next, by irradiating a KrF excimer laser, the region where the ion implantation is performed is annealed and the implanted ions are activated. (FIG. 3 (C))

Next, a silicon oxide film 309 is formed as an interlayer insulating layer to a thickness of about 7000 ° by a plasma CVD method.
This interlayer insulating layer may be formed of a laminate of silicon oxide and an organic resin or an organic resin.

Further, a pixel electrode 310 is formed of ITO and a hole is etched to form a metal electrode wiring. The metal wiring / electrode 313 is a wiring / electrode extending to the source line, and is contacted at 312. The drain electrode / wiring extending from the contact 311 is connected to the pixel electrode 310.

Also in this embodiment, since the electrode 313 extending to the source wiring is formed so as to cover the source 306 of the thin film transistor and the channel forming region 308, light is not irradiated to the channel forming region. In addition, it is possible to realize a configuration in which characteristics of the thin film transistor are not changed or deteriorated by light irradiation.

In particular, when a structure in which an oxide layer is provided around an electrode containing aluminum as a main component as in this embodiment is employed, a structure in which a channel / region is covered with a wiring / electrode connected to a source. Useful. Since the aluminum oxide layer has a light-transmitting property, when there is no light-blocking layer, light irradiated from the gate electrode side may cover the offset gate region (the gate electrode 304 covers the channel formation region 308). Not through) or
The light is refracted and is applied to the channel formation region. Therefore, by forming the electrode wiring 313 as in this embodiment, it is possible to provide a configuration in which light is not irradiated to the offset gate region and the channel formation region.

In addition, in the case of Example 1, only an interlayer insulator was present between the gate electrode and the source line. However, the thin film transistor part has a complicated structure and many steps, and a single interlayer insulator may cause a problem in step coverage, and the insulating property may be insufficient. However, in this embodiment, in addition to the interlayer insulator, the top and side surfaces of the gate electrode are coated with anodic oxide having a sufficient withstand voltage, and the leakage current between the source line and the gate electrode is reduced as much as possible. It was possible.

In this embodiment, an N-channel type TFT is obtained because phosphorus is used as an impurity. However, since an N-channel TFT generally has a large leak current, a P-channel TFT is used as an active matrix pixel.
FT is preferred. In that case, boron may be doped in place of phosphorus in the step of FIG.

Embodiment 3 FIG. 5 shows this embodiment. In the first and second embodiments, the pixel and the drain of the TFT are connected by a metal wiring. However, as shown in FIG.
May be connected directly. In this embodiment, the IT
The layer where O was present and the layer where the source line was present were designed to be different. In this case, the electrolytic corrosion reaction at the time of patterning the ITO can be suppressed. The manufacturing method up to the formation of the source line is almost the same as in the second embodiment.

In FIG. 5, a source 506, a channel forming region 508, and a drain 5 are formed on a substrate / base oxide film 500.
In addition, a polycrystalline silicon active layer having a thickness of 07 is formed, and a gate insulating film 503 of silicon oxide is further formed.
The source / drain was P-type. A gate electrode 504 is provided on the channel formation region, and an anodic oxide film 505 exists around the gate electrode. An interlayer insulator 509 is formed to cover the TFT. And first,
A contact hole 512 is formed for the source 506, and a source line 513 is provided here. Also in this case, the metal wiring / electrode 513 extending from the source line covers the channel formation region.

Next, a second interlayer insulator 514 is formed, and a contact hole 511 is formed for the drain 507. As a material of the second interlayer insulator, silicon nitride, aluminum oxide, or aluminum nitride used as a passivation film is more preferable than silicon oxide. Then, the pixel electrode 51 of the ITO film is directly connected to the drain 507.
0 is connected.

Embodiment 4 FIG. 6 shows this embodiment. In the first to third embodiments, the channel forming region of the TFT is protected against the incidence of light from above the TFT. However, as shown in FIG. They may be combined. This embodiment is characterized in that a light shielding film 614 is provided below the TFT. It is made of metal such as spider and grounded. In FIG. 6, a light-blocking film 614 is formed over a substrate 500, and a base film 602 of silicon oxide is provided thereover. In addition, source 60
6, a polycrystalline silicon active layer having a channel formation region 608 and a drain 607 is formed, and a gate insulating film 603 of silicon oxide is further formed.

A gate electrode 604 is provided on the channel forming region, and an anodic oxide film 605 exists around the gate electrode. An interlayer insulator 6 covering the TFT
09 is formed, and contact holes 611 and 612 are formed.
Drain and source are provided for each.
A metal electrode / wiring 613 is connected to the source 606, and a pixel electrode 610 of an ITO film is connected to the drain 607. Also in this case, the metal wiring / electrode 6 extending from the source line is used.
Reference numeral 13 covers the channel formation region. Although the source line and the pixel electrode are in the same layer in FIG. 6, they may be in different layers as in the third embodiment.

[0048]

According to the present invention, by forming the source wiring of the thin film transistor so as to cover the channel forming region of the thin film transistor, light emitted from the upper surface of the thin film transistor can be prevented from irradiating the channel forming region. It is possible to prevent a change in characteristics and deterioration of the thin film transistor due to light irradiation.

[Brief description of the drawings]

FIG. 1 shows a top view and a circuit diagram of a pixel portion of an embodiment, a thin film transistor formed thereon.

FIG. 2 shows a manufacturing process of a thin film transistor of an example.

FIG. 3 shows a manufacturing process of a thin film transistor of an example.

FIG. 4 shows a configuration of a thin film transistor according to the related art formed in a pixel portion.

FIG. 5 shows a structure of a thin film transistor of an example.

FIG. 6 shows a structure of a thin film transistor of an example.

[Explanation of symbols]

 101, a gate line 102, a source line 103, a pixel electrode 104, a source 105, a channel forming region 106, a drain 107, a gate electrode 108, ··· Contact section 109 ··· Contact section 110 ··· Thin film transistor 111 ··· Liquid crystal 112 ··· Source electrode wiring 200 ··· Glass substrate 201 ··· Amorphous silicon semiconductor layer 202 · ... Active layer (crystalline silicon layer) 203 ... Gate insulating film (silicon oxide film)

Claims (4)

[Claims] A semiconductor film formed on an insulating surface and having a source region, a drain region and a channel forming region; a gate insulating film formed on the semiconductor film; and a gate formed on the gate insulating film. An electrode; a first interlayer insulating film formed of an organic resin film or a multilayer film including a silicon oxide film and an organic resin film formed above the gate electrode; and the first interlayer insulating film connected to the source region. A source electrode formed on the film; and a second interlayer insulating film formed on the first interlayer insulating film and sandwiching the source electrode therebetween, wherein the source electrode is irradiated to a channel formation region. A semiconductor device, which shields light, and wherein the second interlayer insulating film is any one of silicon nitride, aluminum nitride, and aluminum oxide. 2. The semiconductor device according to claim 1, further comprising a light-shielding film below the semiconductor film. 3. The semiconductor device according to claim 2, wherein said light shielding film is grounded. 4. The semiconductor device according to claim 1, wherein said pixel electrode is connected to said drain region through a contact hole formed in first and second interlayer insulating films.