JP2001053082A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor device where a base layer is lessened in film thickness, and a base is lessened in contact width preventing increase in parasitic capacitance between the collector and the base. SOLUTION: An outer base electrode 3 of a polycrystalline silicon layer is formed on an SiO2 film 2 on an N-type epitaxial layer 1, an outer base electrode 3 and the epitaxial layer 1 are connected together at the perimeter of an opening 4 provided to the surface of the epitaxial layer 1, a side wall of SiO2 5 is formed on a part of the side wall of an outer base electrode 3 in an opening 4, a P-type base layer 6 connected to both a part of the side wall of the outer base electrode 3 which is not covered with the side wall 5 and the lower epitaxial layer 1 respectively is formed, an N-type emitter layer 7 connected to the base layer 6 in the opening 4 is formed, and furthermore the emitter layer 7 is separated from the outer base electrode 3 by the side wall 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly to an ultra-high-speed bipolar transistor using a molecular beam epitaxy (MBE) selective growth method for forming a base.

[0002]

2. Description of the Related Art In recent years, bipolar transistors have been used in the central part of equipment requiring high speed, such as supercomputers and optical communication devices. Have been. In order to increase the speed, it is necessary to form an extremely thin high-concentration base layer, and to form a parasitic capacitance (emitter-base capacitance, base-collector capacitance, collector-substrate capacitance) and a parasitic resistance (base resistance, emitter resistance). , Collector saturation resistance)
Must be reduced.

Therefore, conventionally, a molecular beam epitaxy selective growth method (hereinafter simply referred to as MBE) has been used for forming the base of a bipolar transistor instead of the ion implantation method or the diffusion method. A so-called SS in which an external base electrode and an emitter region are formed in a self-aligned manner by a high concentration base layer and polycrystalline silicon layer on a substrate.
SB (super self-aligned sel)
An example in which an active ground base structure is adopted has been proposed (Monthly SemiconductorWorld 199).
1.2 See p66).

FIG. 8 shows a typical example. In this figure, 31 is a P-type silicon substrate, 32 is an N-type (high concentration)
, A collector region 33, an N-type (low-concentration) epitaxial layer, 35, an element isolation region by a trench, and 36, M
The base layer made of BE, 37, 38 and 39 are an emitter layer, an external base layer and a collector layer made of a polycrystalline silicon layer, respectively. 40, 41 and 42 are respectively PtSi
, A base electrode, and a collector electrode composed of a tungsten layer and a tungsten layer.

Another example of forming a base layer by using MBE is a method of manufacturing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 1-173642. This method first,
As shown in FIG. 9A, for example, after an N-type buried layer 52 is formed on a P-type silicon substrate 51, an N-type epitaxial layer 53 is stacked thereon.

Next, as shown in FIG. 9B, a field insulating layer 54, a P-type base extraction polycrystalline silicon layer 55 and a SiO ₂ film 56 are sequentially laminated on the entire surface, and a portion serving as an emitter region is etched. N-type epitaxial layer 5
Expose 3

[0009] Next, as shown in FIG. 9 C, silicon (Si) is deposited on the entire surface, and then a portion of the Si is removed by RIE (reactive ion etching) to form a polysilicon step 57. Thereafter, Si is selectively epitaxially grown on the N-type epitaxial layer 53 in a portion to be an emitter region, thereby forming a P-type epitaxial base layer 58.

[0010] Next, as shown in FIG.
O ₂ is deposited, and then SiO ₂ is partially removed by RIE to form an insulating step 59 of SiO ₂ . Thereafter, the emitter polysilicon layer 60 is attached to the emitter portion, and then N-type impurities are diffused from the emitter polysilicon layer 60 to form an emitter diffusion region 61 in the base layer.

Next, as shown in FIG. 10B, after opening a base contact hole 62, an emitter electrode 63 and a base electrode 64 are formed by Al evaporation to obtain an ultrahigh-speed bipolar transistor.

[0010]

However, in the transistor shown in FIG. 8, when the base contact width dc (see FIG. 12) etches the lowermost dielectric film 71, as shown in the enlarged view of FIG. Is determined by the undercut amount du. Therefore, if the thickness t of the dielectric film 71 is increased to reduce the collector-base capacitance, there is a disadvantage that the contact width dc increases.

Further, as shown in FIG. 12, since the undercut portion 72 is buried in the base layer 36 and the polycrystalline silicon layer (external base layer) 38 grown at the time of MBE, the lowermost dielectric film 71 is formed. Thickness t is almost equal to base width tb
Must be set to twice as large as Accordingly, as the thickness of the base layer 36 becomes thinner, the dielectric film 71 becomes thinner, which causes an increase in the collector-base capacitance.

In the case of the manufacturing process shown in FIGS. 9 and 10, when the polysilicon step 57 is formed by etching and removing it by RIE, it is formed on the underlying silicon substrate (N-type epitaxial layer 53). Do the damage,
There is a disadvantage that the characteristics of the bipolar transistor are significantly deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to reduce the thickness of a base layer and reduce the contact of a base while preventing an increase in the parasitic capacitance between the collector and the base. An object of the present invention is to provide a semiconductor device capable of realizing a reduction in width.

[0014]

According to the present invention, there is provided a semiconductor device comprising:
The extraction electrode 3 formed on the first insulating film 2 on the surface of the base 1 of the first conductivity type is connected to the base 1 through a portion of the opening 4 formed on the surface of the base 1, and in the opening 4. A second insulating film (sidewall) 5 is formed on a part of the side wall of the extraction electrode 3, and the second electrode 5 is connected to the side wall of the part of the extraction electrode 3 not covered with the second insulating film 5 and the base 1, respectively. A first semiconductor layer (base layer) 6 of the second conductivity type is formed, and a second semiconductor layer (emitter layer) 7 of the first conductivity type connected to the first semiconductor layer 6 is formed. The second semiconductor layer 7 is separated from the extraction electrode 3 by a second insulating film 5.

Further, the semiconductor device of the second invention of the present application is:
The extraction electrode 3 formed on the first insulating film 2 on the surface of the base 1 of the first conductivity type is connected to the base 1 at a portion of the opening 4 formed on the surface of the base 1, and in the opening 4,
A second insulating film 5 is provided on a part of the side wall of the extraction electrode 3, and the second epitaxially grown second layer is connected to the side wall of the extraction electrode 3 not covered with the second insulating film 5 and the base 1, respectively. It has a first semiconductor layer (base layer) 6 of conductivity type, and further forms a second semiconductor layer (emitter layer) 7 of epitaxially grown first conductivity type connected to the first semiconductor layer 6. The second semiconductor layer 7 is separated from the extraction electrode 3 by a second insulating film 5. Semiconductor device.

A semiconductor device according to a third aspect of the present invention is:
The extraction electrode 3 formed on the first insulating film 2 on the surface of the base 1 of the first conductivity type is connected to the base 1 at a portion of the opening 4 formed on the surface of the base 1, and in the opening 4,
A second insulating film 5 is provided on a part of the side wall of the extraction electrode 3, and the second epitaxially grown second layer is connected to the side wall of the extraction electrode 3 that is not covered by the second insulating film 5 and the substrate 1. It has a first semiconductor layer (base layer) 6 of a conductivity type, and is further connected to the first semiconductor layer 6 and epitaxially grown of a second semiconductor of a material different from the first semiconductor layer. A layer (emitter layer) 7 is formed, and the second semiconductor layer 7 is separated from the extraction electrode 3 by a second insulating film 5.

Further, a semiconductor device according to a fourth invention of the present application is:
The extraction electrode 3 formed on the first insulating film 2 on the surface of the first conductivity type substrate 1 having a plane orientation of <111> is connected to the substrate 1 at the portion of the opening 4 formed on the surface of the substrate 1. In addition, in the opening 4, a second insulating film 5 is provided on a part of the side wall of the extraction electrode 3, and the second insulation film 5 is formed in the extraction electrode 3.
A first semiconductor layer (base layer) 6 of the second conductivity type connected to the side wall of the portion not covered with the base 1 and the first conductivity type connected to the first semiconductor layer, respectively. Of the second semiconductor layer (emitter layer) 7 is formed.
Are separated from the extraction electrode 3 by a second insulating film 5.

According to the configuration of the present invention described above, the external base electrode 3 and the base 1 can be connected to each other in a fine region below the second insulating film (sidewall) 5, and the lowermost layer Since no undercut due to etching is provided for one insulating layer 2, the contact width dc between the external base electrode 3 and the base 1 does not depend on the thickness of the first insulating film 2. Therefore, the contact width dc can be reduced without reducing the thickness of the lowermost first insulating film 2, and the element area of the bipolar transistor itself can be reduced. This leads to a reduction in the thickness of the base layer 6 and a reduction in the contact width dc of the base while preventing an increase in the parasitic capacitance between the collector and the base. Further, since the emitter layer 7 can be continuously formed following the formation of the thin base layer 6, the manufacturing process can be simplified efficiently.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a configuration diagram of a main part showing an ultrahigh-speed bipolar transistor according to the present invention.

This transistor is, for example, an N-type
SiO formed on the axial layer 1 _TwoPolycrystalline silicon on film 2
An external base electrode 3 is formed by a recon layer,
The opening formed on the surface of the epitaxial layer 1
When connected to the epitaxial layer 1 at the periphery of the opening 4
In both cases, the side wall of the external base electrode 3 is formed in the opening 4.
Part of SiO_TwoSidewall 5 is formed,
In the external base electrode 3, covered with the sidewall 5
On the side wall and the lower epitaxial layer 1 respectively.
A P-type base layer 6 to be connected is formed.
6 and an N-type emitter layer 7 connected in the opening 4
And the emitter layer 7 is
And is separated from the external base electrode 3 by the
Have been. 8 is SiO_Two3 shows a membrane.

Next, a manufacturing process of the bipolar transistor according to the present embodiment will be described with reference to FIGS. still,
Components corresponding to those in FIG. 1 are denoted by the same reference numerals.

First, as shown in FIG. 2A, an SiO ₂ film 2, a P-type polycrystalline silicon layer 9 and a SiO ₂ film 8 are sequentially laminated on an N-type epitaxial layer 1. Then, the Si region is formed in a portion where the emitter region (or the base region) is formed.
An opening 4 penetrating the O ₂ film 2, the polycrystalline silicon layer 9 and the SiO ₂ film 8 is formed. In the formation of the epitaxial layer 1, in this example, the epitaxial layer 1 is formed such that the surface orientation of the surface of the epitaxial layer 1 becomes <111>.

Next, as shown in FIG. 2B, an opening 4 is included.
P-type thin film polycrystalline silicon layer 1 having a thickness of about 200 ° on the entire surface 1
0 is formed by, for example, a CVD method. Then, S
iO _TwoAfter the film 5 is formed by, for example, the CVD method, RIE
Etch back by SiO_TwoFilm 5 is made of polycrystalline silicon
A part is left on the side wall of the recon layer 10. That is, SiO_TwoBy membrane
The side wall 5 is formed. At this time,
The diameter d of the opening 11 constituted by the rule 5 is about 0.2 μm.
It is.

Next, as shown in FIG.
After the resist film 12 is embedded therein, the polycrystalline silicon layer 10 on the surface is removed by wet etching using an aqueous solution of ammonia, an aqueous KOH solution or the like. At this time, a groove 13 is formed between the sidewall 5 and the SiO ₂ film 8 due to the etching removal of the polycrystalline silicon layer 10.

Next, as shown in FIG.
After the film 12 is peeled off, SiO _TwoForm the film 14
You. Then, for example, etch back by RIE
In the groove 13, SiO_TwoThe film 14 is left. By this
And the sidewall 5 and SiO_TwoThe film 8 is embedded as described above.
SiO_TwoIt is integrated by the film 14. Then expose
Polycrystalline silicon layer 10 with aqueous ammonia and KOH
It is removed by wet etching using a liquid or the like.

Here, the remaining polycrystalline silicon layer 10 and S
The external base electrode 3 is constituted by the polycrystalline silicon layer 9 on the iO ₂ film 2. In this case, since the plane orientation of the surface of the epitaxial layer 1 is <111>, when the polycrystalline silicon layer 10 is removed by using a KOH aqueous solution, the epitaxial layer 1 is not damaged and the polycrystalline layer under the sidewall 5 is not damaged. Since the silicon layer 10 is side-etched, the contact width dc between the external base electrode 3 and the epitaxial layer 1 becomes very small.

Next, as shown in FIG. 3B, a P-type base layer 6 of SiGe having a thickness of about 500 ° is formed in the opening 11 by using a molecular beam epitaxy selective growth method (hereinafter simply referred to as MBE). In this case, the thickness tb of the base layer 6
Is preferably larger than the thickness tp of the polycrystalline silicon layer 10. After that, MB is also formed on the base layer 6.
E is used to form an N-type emitter layer 7 of about 500.degree.

At this time, the concentration gradient of the base layer 6 or the emitter layer 7 is controlled to narrow the band gap of the base or widen the band gap of the emitter so that the junction between the base and the emitter is made a hetero junction. You may. In this case, a high current amplification factor and excellent high-frequency characteristics can be obtained. After that, the MBE temperature is lowered and the N-type polycrystalline silicon layer 15 is formed on the emitter layer.
To form Then, the crystallinity is recovered by performing RTA (short annealing) at 1050 ° C. to obtain the ultra-high-speed bipolar transistor according to the present example.

As described above, according to the present embodiment, the external base electrode 3 and the epitaxial layer 1 can be connected in a fine region below the sidewall 5. Further, since the undercut by etching is not provided for the lowermost SiO ₂ film 2, the contact width dc between the external base electrode 3 and the epitaxial layer 1 does not depend on the thickness of the SiO ₂ film 2. . Therefore, the contact width dc can be reduced without reducing the thickness of the lowermost SiO ₂ film 2, and the element area of the bipolar transistor itself can be reduced. This means
While preventing an increase in the parasitic capacitance between the collector and base,
This leads to a reduction in the thickness of the base layer 6 and a reduction in the contact width dc of the base.

Further, since the emitter layer 7 can be continuously formed following the formation of the thin base layer 6, the manufacturing process can be simplified efficiently. Further, the base layer 6 is made of 500 ° SiGe, and the emitter layer 7 is made of
It is possible to adopt a SiC of 00%, etc.
A switching speed of psec can be obtained.

Next, two examples of a process for manufacturing an ultra-high-speed bipolar transistor in which the damage to the epitaxial layer 1 is eliminated will be described with reference to FIGS.

FIGS. 4 and 5 are process diagrams showing the first embodiment. Hereinafter, the steps will be sequentially described.

First, as shown in FIG. 4A, a SiO ₂ film 2, a P-type polycrystalline silicon layer 9 and a SiO ₂ film 8 are sequentially laminated on an N-type epitaxial layer 1. Then, the Si region is formed in a portion where the emitter region (or the base region) is formed.
An opening 4 penetrating the O ₂ film 2, the polycrystalline silicon layer 9 and the SiO ₂ film 8 is formed. In the formation of the epitaxial layer 1, in this example, the epitaxial layer 1 is formed such that the surface orientation of the surface of the epitaxial layer 1 becomes <111>.

Next, as shown in FIG. 4B, a P-type thin film polycrystalline silicon layer 10 having a thickness of about 200 ° is formed on the entire surface including the opening 4 by, for example, a CVD method. Thereafter, an SiO ₂ film 5 is formed on the entire surface by, for example, a CVD method.
Etchback by IE is performed to leave a part of the SiO ₂ film 5 on the side wall of the polycrystalline silicon layer 10. That is, the sidewall 5 is formed by the SiO ₂ film. At this time, the diameter d of the opening 11 formed by the sidewall 5 is about 0.2 μm.
It is about.

Next, as shown in FIG. 4C, using the sidewalls 5 as a mask, the polycrystalline silicon layer 10 on the surface is removed by wet etching using an ammonia peroxide solution, a KOH aqueous solution or the like. At this time, the side wall 5 and the SiO ₂ film 8
A groove 13 is formed during the etching of the polycrystalline silicon layer 10 therebetween, and the polycrystalline silicon layer 10 below the sidewall 5 is side-etched. here,
An external base electrode 3 is constituted by the remaining polycrystalline silicon layer 10 and the polycrystalline silicon layer 9 on the SiO ₂ film 2, and the external base electrode 3 and the epitaxial layer 1 Contact width dc
Becomes very fine.

Since the polycrystalline silicon layer 10 is removed by etching using selective isotropic etching (wet etching) for the underlying epitaxial layer 1, the epitaxial layer 1 is not damaged. . The plane orientation of the surface of the epitaxial layer 1 is <111.
>, The crystallinity is good even if the above etching is performed.

Next, as shown in FIG. 5A, a P-type base layer 6 of Si single crystal thinner than the polycrystalline silicon layer 10 is formed in the opening 11 using MBE. At this time, the polysilicon layer 10 exposed in the opening 11 is exposed.
Are grown laterally by the MBE and the grooves 13
The polycrystalline silicon layer 10 exposed from the trench grows above the groove 13.

Next, as shown in FIG.
_{After the second} film 16 is formed by, for example, the CVD method, the SiO ₂ film 16 is buried in the groove 13 by etching back by RIE, and the side wall 17 of the SiO ₂ film 16 is formed in the opening 11. Then, the opening 11
An N-type polycrystalline silicon layer constituting the emitter layer 7 is formed therein by, for example, a CVD method and then RTA at 1050 ° C.
By performing (short-time annealing), the crystallinity is recovered, and the ultra-high-speed bipolar transistor according to the first embodiment is obtained.

According to the first embodiment, a polycrystalline silicon layer 10 is formed on the entire surface including the opening 4, and the polycrystalline silicon layer is formed on the side wall of the opening 4 in a self-aligned manner by the sidewall 5 formed thereafter. 10, the remaining polycrystalline silicon layer 10 is used as the external base electrode 3 and the polycrystalline silicon layer 10 is connected to the base layer 6 formed by MBE. It is possible to simultaneously reduce the size and the contact width dc of the base. Further, since the lowermost SiO ₂ film 2 can be made thick regardless of the thickness of the base layer 6, the parasitic capacitance between the collector and the base can be reduced. Further, since the isotropic etching (wet etching) having a selective property with respect to the epitaxial layer is used as a method for removing the polycrystalline silicon layer 10, the epitaxial layer 1 is not damaged.

Next, FIGS. 6 and 7 are process diagrams showing a second embodiment of the ultrahigh-speed bipolar transistor. Hereinafter, the steps will be sequentially described.

First, as shown in FIG. 6A, after forming the SiO ₂ film 21 having a thickness of about 1000Å on the epitaxial layer 1 of N-type, to the SiO ₂ film, different from the SiO ₂ film and the etching characteristics For example, a SiN film 22 is formed, and the P-type polycrystalline silicon layer 9 and the S
The iO ₂ films 8 are sequentially stacked. Thereafter, the SiO ₂ film 8 is formed in a portion where the emitter region (or the base region) is formed.
Opening 4 penetrating polycrystalline silicon layer 9 and SiN film 22
To form In forming the opening 4, the opening is formed under RIE conditions having a selectivity of 10 or more with respect to Si. In the formation of the epitaxial layer 1, in this example, the epitaxial layer 1 is formed such that the surface orientation of the surface of the epitaxial layer 1 becomes <111>.

Next, as shown in FIG. 6B, the SiN film 22 is side-etched by wet etching using hot phosphoric acid. Thereafter, a polycrystalline silicon layer 10 is formed on the entire surface by, for example, a CVD method. At this time, the SiN film 2
The polycrystalline silicon layer 10 is also filled in the undercut portion 23 formed by the side etching of No. 2.

Next, as shown in FIG. 6C, the polycrystalline silicon layer 10 is etched back by RIE,
Polycrystalline silicon layer 1 only in undercut portion 23
Leave 0. After that, for example, an SiN film 24 having an etching characteristic different from that of the SiO ₂ film 21 is formed on the entire surface, and then an RI film is formed.
Etchback by E is performed to leave the SiN film 24 on the side wall of the opening 4. That is, the side wall 24 of the SiN film
To form

Next, as shown in FIG.
The O ₂ film 21 is removed by wet etching. Since this wet etching is isotropic, the SiO ₂ film 21
Is laterally etched down to below the polycrystalline silicon layer 10.

Next, as shown in FIG. 7B, a P-type base layer 6 of a Si single crystal thinner than the SiO ₂ film 21 is formed in the opening 4 using MBE. At this time, Si
In the undercut portion 25 of the O ₂ film 21, S
The portion of the polycrystalline silicon layer 10 where there is no iO ₂ film 21 grows downward and is connected to the base layer 6 which grows upward. At this time, the base width tb is about 500 °. The external base electrode 3 is composed of the polycrystalline silicon layer 10 and the polycrystalline silicon layer 9 on the SiO ₂ film 21.

Next, as shown in FIG.
After forming the _second film 26 by, for example, a low pressure CVD method,
Etchback by E is performed, and a sidewall 26 of SiO ₂ film is formed in the opening 11 by the sidewall 24.
To form After that, an N-type polycrystalline silicon layer constituting the emitter layer 7 is formed in the opening 11 by, for example, a CVD method, and then the crystallinity is restored by performing RTA (short annealing) at 1050 ° C. to perform the second embodiment. An ultrafast bipolar transistor according to the example is obtained.

[0047] The According to the second embodiment, an insulating film formed on the lower layer of the polycrystalline silicon layer 9 and the SiO ₂ film 21 Si
Since the N film 22 has a two-layer structure, the polycrystalline silicon layer 10 is buried in the undercut portion 23 of the SiN film 22 in advance, and the undercut portion 25 of the SiO ₂ film 21 is buried in MBE. -It is possible to simultaneously reduce the base width and the contact width of the base while preventing an increase in parasitic capacitance between the bases. In addition, since the isotropic etching (wet etching) having selectivity with respect to the epitaxial layer 1 is used as a method for removing the SiO ₂ film 21, the epitaxial layer 1 is not damaged.

In the first and second embodiments, an N-type polycrystalline silicon layer is used as the emitter layer 7. However, as shown in FIG. 1, the emitter layer 7 is formed using MBE. You may. In this case, if the concentration gradient of the base layer 6 or the emitter layer 7 is controlled to narrow the band gap of the base or widen the band gap of the emitter to make the junction system between the base and the emitter a heterojunction, the above effect can be obtained. In addition, a high current amplification factor and excellent high-frequency characteristics can be obtained.

[0049]

According to the semiconductor device of the present invention, the base layer can be made thinner and the contact width of the base can be reduced while preventing an increase in the parasitic capacitance between the collector and the base. At the formation stage, the characteristics of the ultra-high-speed bipolar transistor could be improved because no damage was given to the silicon substrate and the like.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a main part of an ultrahigh-speed bipolar transistor according to an embodiment.

FIG. 2 is a manufacturing process diagram of the ultrahigh-speed bipolar transistor according to the present embodiment.

FIG. 3 is a manufacturing process diagram of the ultra-high-speed bipolar transistor according to the present embodiment.

FIG. 4 is a manufacturing process diagram of the ultrafast bipolar transistor according to the first embodiment.

FIG. 5 is a manufacturing process diagram of the ultra-high-speed bipolar transistor according to the first embodiment.

FIG. 6 is a manufacturing process diagram of the ultra-high-speed bipolar transistor according to the second embodiment.

FIG. 7 is a manufacturing process diagram of the ultrahigh-speed bipolar transistor according to the second embodiment.

FIG. 8 is a configuration diagram showing a main part of an ultra-high-speed bipolar transistor according to a conventional example.

FIG. 9 is a manufacturing process diagram of an ultra-high-speed bipolar transistor according to a conventional example.

FIG. 10 is a manufacturing process diagram of an ultra-high-speed bipolar transistor according to a conventional example.

FIG. 11 is an explanatory view showing the operation of an ultra-high-speed bipolar transistor according to a conventional example.

FIG. 12 is an explanatory diagram showing the operation of an ultra-high-speed bipolar transistor according to a conventional example.

[Explanation of symbols]

1 ... N-type epitaxial layer, 2, 8, 21 ...
SiO ₂ film, 3 ... external base electrode, 4, 11 ...
Opening, 5, 24 side wall, 6 base layer, 7 emitter layer, 9, 10 polycrystalline silicon layer, 22 SiN film

Claims (4)

[Claims] An extraction electrode formed on a first insulating film on a surface of a substrate of a first conductivity type is connected to the substrate at an opening formed on the surface of the substrate, and is connected to the inside of the opening. A second insulating film on a part of a side wall of the extraction electrode, and a second conductive type second electrode connected to the side wall and the base of a part of the extraction electrode that is not covered with the second insulating film. A second semiconductor layer of a first conductivity type connected to the first semiconductor layer, wherein the second semiconductor layer is separated from the extraction electrode by the second insulating film. A semiconductor device characterized in that: 2. An extraction electrode formed on a first insulating film on a surface of a substrate of a first conductivity type is connected to the substrate at a portion of an opening formed on the surface of the substrate. A second insulating film on a part of a side wall of the extraction electrode, and a second conductive film epitaxially grown connected to the side wall of the extraction electrode not covered by the second insulating film and the base, respectively. A first semiconductor layer of a first conductivity type connected to the first semiconductor layer, and a second semiconductor layer of a first conductivity type epitaxially grown, the second semiconductor layer being formed by the second insulating film. A semiconductor device, which is separated from the extraction electrode. 3. An extraction electrode formed on a first insulating film on a surface of a substrate of a first conductivity type is connected to the substrate at a portion of an opening formed on the surface of the substrate. A second insulating film on a part of a side wall of the extraction electrode, and a second conductive film epitaxially grown connected to the side wall of the extraction electrode not covered by the second insulating film and the base, respectively. A first semiconductor layer of a first conductivity type, which is connected to the first semiconductor layer and is made of a material different from that of the first semiconductor layer. The two semiconductor layers correspond to the second
A semiconductor device, which is separated from the extraction electrode by an insulating film. 4. An extraction electrode formed on a first insulating film on a surface of a substrate of a first conductivity type having a plane orientation of <111>,
At the portion of the opening formed on the surface of the base, the base is connected to the base, and inside the opening, a second insulating film is provided on a part of a side wall of the extraction electrode.
A first semiconductor layer of a second conductivity type connected to the side wall of the portion not covered by the second insulating film and the base, respectively;
A second semiconductor layer of a first conductivity type connected to the first semiconductor layer; and the second semiconductor layer is separated from the extraction electrode by the second insulating film. Semiconductor device.