JP2001053017A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a source and drain diffusion layer of a shallow junction and low resistance which can increase a large current driving capability and suppress a short channel effect at the same time, and also provide a method for manufacturing the device. SOLUTION: A mixed crystal compound semiconductor layer 2 of silicon and germanium is formed on a semiconductor substrate 10. Then, impurities are added by ion implantation into the mixed crystal compound semiconductor layer in a density of 1020/cm3 or above. Next, a heat treatment is conducted to form a diffusion layer 5 of low resistance and a shallow junction by solid phase diffusion from the mixed crystal compound semiconductor layer 4 containing the impurities. Thereafter, the mixed crystal compound semiconductor layer 4 containing the impurities is removed by an etchant to leave only the diffusion layer 5. This process is applied to the formation of a source and a drain region to manufacture a MOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
A semiconductor device including an OS transistor or a bipolar transistor, or a semiconductor device including a capacitor;
More particularly, the present invention relates to a semiconductor device used for a logic system LSI, a DRAM / CMOS mixed system LSI, and a flash / CMOS mixed system LSI.

[0002]

2. Description of the Related Art High speed and high integration of MOS transistors have been achieved by miniaturization in accordance with the scaling rule. However, with the miniaturization of devices, various phenomena that degrade device characteristics such as a short channel effect have become apparent. The short channel effect can be improved by forming a shallow junction. As one of the techniques, a stacked source / drain structure in which the source and drain junction surfaces are raised using a selective epitaxial growth technique of a semiconductor has been devised.

[0003] For example, the International Electronic Device Conference (199)
2) Proceedings, pages 885 to 888 (IEDM Technical
Digest, pp. 885-888 (1992))
Diffusion depth of source and drain in drain structure (xj)
It has been reported that the shallowness of the metal layer improves the short channel effect and the hot carrier effect. But,
In the current selective epitaxial growth technique, since the thickness of the stacked layers varies, it is difficult to control xj, and there is a problem that the transistor characteristics vary. In addition, the gate electrode is stacked via the insulating film on the gate side wall and comes into contact with the source / drain layer, so that there is a problem that the gate capacitance increases.

As a method for solving the above-mentioned problem, Japanese Patent Application Laid-Open No. 8-213605 discloses a method for forming a shallow junction as described below.

A silicon germanium layer containing boron is formed on a silicon substrate, and the silicon
Solid phase diffusion of boron in the germanium layer is performed to form a shallow junction source / drain. After that, the silicon-germanium layer containing boron is removed with a mixed solution of hydrofluoric acid and nitric acid.

However, the above-mentioned Japanese Patent Application Laid-Open No. Hei 8-213
In the method of manufacturing a semiconductor device described in Japanese Patent No. 605, although a shallow diffusion layer can be formed, silicon
Since a diffusion layer is formed by solid-phase diffusion from a germanium layer, an n-type diffusion layer cannot be formed, which makes it difficult to form a CMOS transistor. Further, when the silicon-germanium layer containing impurities is removed with a mixed solution of hydrofluoric acid and nitric acid, there is a problem that an etching selectivity cannot be obtained with a polycrystalline silicon gate electrode containing impurities at a high concentration.

Another prior art is disclosed in Japanese Patent Application Laid-Open No. 9-1621.
No. 74 discloses the following shallow junction forming method.

FIG. 3B is a cross-sectional view of a semiconductor device manufactured by the manufacturing method disclosed in the above publication. First, a gate electrode 8 and a silicon nitride film side wall 19 are formed on a semiconductor substrate 10 with a gate oxide film 7 interposed therebetween. Next, a silicon-germanium layer is formed on the entire surface, and BF2
Ion is implanted. Next, the silicon germanium layer is etched back to form a side wall 51 of the silicon germanium layer containing boron, and after implanting BF2 ions, a shallow diffusion layer 5 and a deep diffusion layer 12 are formed by heat treatment. .

The method of manufacturing a semiconductor device described in Japanese Patent Application Laid-Open No. Hei 9-162174 has a problem that the gate capacitance increases due to the presence of the silicon germanium layer on the side wall of the gate electrode via the silicon nitride film side wall 19. is there. Also, as shown in FIG.
9, the lateral diffusion distance d just below the gate electrode
There is a problem that L becomes small and the current driving capability decreases. Furthermore, there is no mention of the formation of a CMOS transistor.

[0010] Still another prior art is disclosed in Japanese Patent Laid-Open No. 3-1.
No. 01220 discloses the following shallow junction forming method.

Polycrystalline Ge or Si on a silicon substrate
A thin film of a mixed crystal of Ge and Ge is formed, and after ion implantation of boron, an internal base layer is formed by heating and then an emitter layer is formed by ion implantation of phosphorus to form an emitter layer. Polycrystalline G
e or a thin film of a mixed crystal of Si and Ge is removed.

However, the above-mentioned publication discloses that a thin film of polycrystalline Ge or a mixed crystal of Si and Ge can be selectively removed from a single crystal Si substrate in concentrated sulfuric acid, nitric acid or the like. It has been found that nitric acid cannot achieve a high selectivity with highly doped silicon or silicon oxide. Further, there is no mention of the formation of a MOS transistor.

[0013]

FIGS. 3 (a) to 3 (c) show the differences between the techniques for forming the junction of the source / drain diffusion layers.
FIG. 3A is a cross-sectional view of a semiconductor device in which a shallow junction 5 is formed using conventional ion implantation. 3 by ion implantation
When a shallow junction of 0 nm or less is formed, there is a problem in that the activation rate of impurities is reduced, and the resistance of the source / drain diffusion layer is increased, so that the current driving capability is reduced. Furthermore, in ion implantation, the lateral diffusion distance is smaller than the doping depth. Therefore, when a shallow junction of 30 nm or less is formed, the lateral diffusion distance dL immediately below the gate electrode is reduced to 10 nm or less, and the current driving capability is reduced. There's a problem.

FIG. 3B is a view showing the above-mentioned Japanese Patent Application Laid-Open No. 9-162174.
3 is a cross-sectional view of a semiconductor device manufactured by the manufacturing method disclosed in Japanese Patent Application Laid-Open No. H10-26095. As described above, FIG. 3B shows a problem that the gate capacitance increases due to the presence of the silicon-germanium layer 51 containing boron on the gate electrode side wall via the silicon nitride film side wall 19, thereby deteriorating the circuit performance. is there. Furthermore, since the silicon nitride film side wall 19 exists, the lateral diffusion distance dL immediately below the gate electrode becomes small, and there is a problem that the current driving capability is reduced.

An object of the present invention is to solve the above-mentioned problems, to provide a semiconductor device having a shallow junction and a low-resistance source / drain diffusion layer, capable of simultaneously achieving a large current driving capability and a suppression of a short channel effect, and its manufacture. It is to provide a method.

Another object of the present invention is to provide a method of manufacturing a semiconductor device having a CMOS transistor provided with a source / drain diffusion layer having a low resistance and a shallow junction.

[0017]

The object of the present invention is to dope impurities into a mixed crystal semiconductor 2 of silicon and germanium formed on a semiconductor substrate 1 at a high concentration by ion implantation as shown in FIG. After forming a shallow junction diffusion layer 5 by solid phase diffusion from a mixed crystal semiconductor layer 4 of silicon and germanium doped with this impurity by a heat treatment, a mixed solution of ammonia, hydrogen peroxide and water (FIG. 2) is used. This is achieved by a semiconductor device having a low resistance and shallow junction diffusion layer 5 formed by removing the mixed crystal semiconductor layer 4 of silicon and germanium doped with the impurity.

In the above-described semiconductor manufacturing method, since the diffusion layer 5 is isotropically formed by solid-phase diffusion, the lateral diffusion distance and the diffusion layer depth are equal, and as shown in FIG. The lateral diffusion distance dL immediately below is smaller than that of the conventional ion implantation, and high current driving capability can be obtained.

Another object of the present invention is to implant n-type impurities and p-type impurities separately using a photomask when ion-implanting into a mixed crystal semiconductor layer 4 of silicon and germanium, so that the shallow junction source and the This is achieved by forming a drain.

According to the present invention, the thermal diffusion rate of impurities in the silicon-germanium mixed crystal semiconductor layer 4 serving as a solid-phase diffusion source is about 100 times faster than that in silicon. Even if the thickness of the semiconductor layer 4 varies, a diffusion layer having a uniform depth in silicon can be manufactured.

Further, when the mixed crystal semiconductor layer 4 of silicon and germanium is formed of amorphous or polycrystalline, impurities can be doped by ion implantation without channeling, so that a shallower junction layer can be formed. .

Further, since the mixed crystal semiconductor layer 4 of silicon and germanium doped with impurities is removed by a mixed solution of ammonia, hydrogen peroxide water and water, the silicon and the silicon oxide film doped with high concentration impurities are not etched. With high selectivity.

Further, by selectively growing the mixed crystal semiconductor layer 4 of silicon and germanium, a shallow junction and a deep junction can be simultaneously formed by one ion implantation. This deep diffusion layer can be used for a high breakdown voltage semiconductor device.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings.

The first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (d). First, as shown in FIG.
A mixed crystal semiconductor layer 2 of silicon and germanium is formed on a semiconductor substrate 1. The mixed crystal semiconductor layer 2 of silicon and germanium can be formed of any of single crystal, polycrystal, and amorphous. As shown in FIG. 2, a germanium composition ratio x is selected so that an etching selectivity with the silicon layer can be obtained. 20% <
It is formed so that x <100%. Next, as shown in FIG. 1B, impurity ions 3 are implanted into the mixed crystal semiconductor layer 2 of silicon and germanium, and the mixed crystal semiconductor layer 4 of silicon and germanium doped with an impurity of 10 ²⁰ / cm ³ or more is formed. Form. Next, as shown in FIG. 1C, a heat treatment is performed at 900 ° C. for 30 seconds in a nitrogen atmosphere using a lamp heating device, so that the mixed-crystal semiconductor layer 4 of silicon and germanium of the second conductivity type is formed. To form a diffusion layer 5 of a second conductivity type having a low resistance and a shallow junction. In this heat treatment, the melting point of germanium is 937 ° C. and the melting point of silicon is 1
Since the temperature is 415 ° C., the temperature is desirably 1000 ° C. or less in order to prevent outward diffusion of impurities from the surface of the mixed crystal semiconductor layer 4 of silicon and germanium. And FIG.
As shown in (d), the mixed semiconductor layer 4 of silicon and germanium of the second conductivity type is removed with a mixed solution of ammonia, hydrogen peroxide water and water, and only the diffusion layer 5 of the second conductivity type is formed. .

FIGS. 4A to 4D are cross-sectional views showing an example of a manufacturing process according to the second embodiment of the present invention. Example 2 is an example in which a shallow junction layer 5 is formed in an opening formed by an insulating film layer 6.

Example 2 will be described according to the manufacturing process. First, as shown in FIG. 4A, a first insulating film layer 6 having an opening is formed on a semiconductor substrate 1 by a known method.
Next, a mixed crystal semiconductor layer 2 of silicon and germanium is formed on the entire surface of the semiconductor substrate 1. The mixed crystal semiconductor layer 2 of silicon and germanium is formed on the insulating film layer 6 as polycrystal or amorphous. Next, as shown in FIG. 4B, the impurity ions 3 are converted into a mixed crystal semiconductor layer 2 of silicon and germanium.
To form a mixed-conductivity semiconductor layer 4 of silicon and germanium of the second conductivity type doped with 10 ²⁰ / cm ³ or more impurities of the second conductivity type. Next, as shown in FIG. 4C, a silicon layer 5 of the second conductivity type is formed by solid phase diffusion from the mixed crystal semiconductor layer 4 of silicon and germanium of the second conductivity type by heat treatment. The thermal diffusion rate of impurities in the mixed crystal semiconductor layer 4 of silicon and germanium is about 10 times that in silicon.
Since it is 0 times faster, the impurity is uniformly doped even in a region where the thickness of the mixed crystal semiconductor layer 4 of silicon and germanium at the edge of the opening is large. Then, as shown in FIG. 4 (d), the mixed crystal semiconductor layer 4 of silicon and germanium of the second conductivity type is removed with a mixed solution of ammonia, hydrogen peroxide water and water, and a low resistance and shallow junction The two-conductive type diffusion layer 5 was left.

FIGS. 5 (a) to 5 (e) show M of Embodiment 3 of the present invention.
FIG. 7 is a cross-sectional view illustrating an example of a process in a method for manufacturing a semiconductor device having an OS transistor.

In FIG. 5A, reference numeral 10 denotes a semiconductor substrate.
For example, it is doped into n-type. First, a first insulating film layer 6 for element isolation, a second insulating film layer 7 for a gate insulating film, and ap disposed on the second insulating film layer are formed on the semiconductor substrate 10 by a known method. Forming a polycrystalline silicon gate electrode 8 and a third insulating film layer 9 formed on the gate electrode.

Next, as shown in FIG. 5B, a mixed crystal semiconductor layer 2 of silicon and germanium is formed on the entire surface of the semiconductor substrate 10. Next, as shown in FIG. 5C, a mixed crystal semiconductor layer of silicon and germanium doped with p-type impurities of 10 ²⁰ / cm ³ or more is formed by ion implantation.
Simultaneously with the formation of the p-type silicon-germanium mixed crystal semiconductor layer 4 by the heat treatment, the p-type source and drain 5 are formed by solid-phase diffusion from the p-type silicon-germanium mixed crystal semiconductor layer 4. Next, as shown in FIG. 5D, the p-type mixed crystal semiconductor layer 4 of silicon and germanium is removed with a mixed solution of ammonia, hydrogen peroxide solution and water.
Then, after forming the fourth insulating film layer 11 on the side wall of the gate electrode by a well-known method, the deep source and the drain 12 were formed by ion implantation to form the MOS transistor shown in FIG. According to this embodiment, a low-resistance and shallow source and drain 5 are formed, and a MOS transistor that realizes the suppression of the single-channel effect and the high current driving capability is formed.

FIGS. 6A to 6E show C of Example 4 of the present invention.
FIG. 4 is a cross-sectional view illustrating a process example of a method for manufacturing a semiconductor device having a MOS transistor. In FIG. 6A, a well 13 of the second conductivity type is doped with, for example, p-type. Reference numeral 14 denotes an n-type well, and 15 denotes an n-type polycrystalline silicon gate electrode. First, a p-type well 13, an n-type well 14, a first insulating film layer 6 for element isolation, and a second insulating film layer 7 for a gate insulating film are formed on a semiconductor substrate 10 by a known method.
To form Next, as shown in FIG. 6A, the n-type polysilicon gate electrode 1 disposed on the p-type well 13 is formed.
5. A p-type polycrystalline silicon gate electrode 8 disposed on the n-type well 14 is formed. Next, as shown in FIG. 6B, a mixed crystal semiconductor layer 2 of silicon and germanium is formed on the entire surface of the semiconductor substrate 10. Next, as shown in FIG. 6C, a mixed crystal semiconductor layer 16 of silicon and germanium doped with an n-type impurity and a silicon-germanium mixture of silicon and germanium doped with a p-type impurity are separately formed by ion implantation using a photoresist as a mask. The mixed crystal semiconductor layers 17 are respectively formed. Next, as shown in FIG. 6D, an n-type mixed crystal semiconductor layer 1 of silicon and germanium is formed by heat treatment.
6 and p-type mixed crystal semiconductor layer 17 of silicon and germanium
N-type shallow source / drain 18 and p
The shallow source and drain 5 are formed, and the mixed crystal semiconductor layer of silicon and germanium is removed with a mixed solution of ammonia, hydrogen peroxide and water. Then, after forming the fourth insulating film layer 11 on the side wall of the gate electrode by a known method, an n-type deep source and drain 21 and a p-type deep source and drain 12 are formed by ion implantation. Then, as shown in FIG. 6E, the gate electrode and the source and drain were silicidated to form a CMOS transistor. The silicide layer 52 has, for example, TiSi
2 or CoSi2 can be used. CMOS with low resistance and shallow junction source and drain according to this embodiment
A transistor could be formed.

FIGS. 7 (a) to 7 (e) show M of Embodiment 5 of the present invention.
FIG. 7 is a cross-sectional view illustrating an example of a process in a method for manufacturing a semiconductor device having an OS transistor. Embodiment 5 is an example in which the present invention is applied to a MOS transistor having a polymetal gate structure which can prevent an increase in gate resistance even if the gate length is reduced.

First, as shown in FIG. 7A, a first insulating film layer 6 for element isolation and a second insulating film layer 7 for a gate insulating film are formed on an n-type semiconductor substrate 10 by a known method. A p-type polycrystalline silicon gate electrode layer 8 disposed on the second insulating film layer, a metal electrode layer 19 formed on the p-type polycrystalline silicon gate electrode, and formed on the gate electrode. Third
Is formed. The metal electrode layer 19 is made of, for example, tungsten or tungsten and tungsten.
A nitride laminated film is used. Next, as shown in FIG. 7B, an insulating film 20 having a thickness of about 10 nm is formed on the side wall of the gate electrode. When forming the insulating film 20, the n
A method in which an insulating film is deposited on the entire surface of the semiconductor substrate 10 and then formed using anisotropic dry etching, or a method in which the entire surface of the semiconductor substrate 10 is oxidized and then formed using anisotropic dry etching. May be used. Next, a mixed crystal semiconductor layer 2 of silicon and germanium is formed on the entire surface of the semiconductor substrate 10. Next, FIG.
As shown in FIG. 1C, a silicon-germanium mixed crystal semiconductor layer 4 doped with p-type impurities of 10 ²⁰ / cm ³ or more is formed by ion implantation. Next, a p-type source and a drain 5 having a diffusion depth d are formed by solid-phase diffusion from the mixed crystal semiconductor layer 4 of p-type silicon and germanium by heat treatment. In order to prevent a decrease in current driving capability, the diffusion depth d needs to be larger than the thickness t of the insulating film on the side wall of the gate electrode by this heat treatment. Next, as shown in FIG. 7D, the mixed crystal semiconductor layer 4 of p-type silicon and germanium is removed with a mixed solution of ammonia, hydrogen peroxide solution and water. Then, as shown in FIG. 7E, a fourth insulating film layer 11 is formed on the side wall of the gate electrode by a known method, and then a deep p-type source and drain 12 are formed by ion implantation. According to this embodiment, a MOS transistor having a low resistance and a shallow source and drain 5 and a polymetal gate could be formed.

FIGS. 8A to 8E show C of Embodiment 6 of the present invention.
FIG. 4 is a cross-sectional view illustrating a process example of a method for manufacturing a semiconductor device having a MOS transistor. Embodiment 6 is an example in which the present invention is applied to a CMOS transistor having a polymetal gate structure.

After forming a well in the same manner as in the fourth embodiment, as shown in FIG. 8A, an n-type polysilicon gate electrode layer is formed on the p-type well 13 with the second insulating film layer 7 interposed therebetween. 15, a metal layer 19, a third insulating film layer 9, a p-type polycrystalline silicon gate electrode 8 on the n-type well 14 with a second insulating film layer 7 interposed therebetween, a general-purpose layer 19, and a third insulating film The layer 9 is formed. Next, after forming an insulating film 20 on the side wall of the gate electrode, FIG.
As shown in (b), a mixed crystal semiconductor layer 2 of silicon and germanium is formed on the entire surface of the semiconductor substrate 10. Next, FIG.
As shown in FIG. 1C, a mixed crystal semiconductor layer 16 of silicon and germanium doped with an n-type impurity and a mixed crystal semiconductor layer of silicon and germanium doped with a p-type impurity are separately formed by ion implantation using a photoresist as a mask. Each of the layers 17 is formed. Next, by heat treatment
n-type mixed crystal semiconductor layer 16 of silicon and germanium and p
N-type shallow source / drain 18 and p-type shallow source / drain 5 are formed by solid phase diffusion from mixed crystal semiconductor layer 17 of silicon and germanium, respectively, and a mixed solution of ammonia, hydrogen peroxide water and water Then, the mixed crystal semiconductor layer of silicon and germanium is removed. Then, after forming the fourth insulating film layer 11 on the side wall of the gate electrode by a well-known method, the n-type deep source and drain 2 are formed by ion implantation.
1 and p-type deep source and drain 12 are formed, and FIG.
A CMOS transistor as shown in FIG.
According to this embodiment, a CMOS transistor having a polymetal gate and a source and a drain having a low resistance and a shallow junction can be formed.

FIG. 9 is a sectional view of a MOS transistor according to a seventh embodiment of the present invention. In FIG. 9, 5 is a shallow source and drain region containing germanium and has a junction depth d.
1 is 30 nm or less, and 11 is a fourth insulating film layer not containing germanium formed on the side wall of the gate electrode.

In this embodiment, the source and drain regions 5
The short channel effect was suppressed by the shallow junction, and the mobility was increased by introducing germanium into the source and drain regions, and the high current driving capability was obtained by reducing the resistance of the source and drain regions.

It is known that the solid solubility limit of impurities in a mixed crystal semiconductor of silicon and germanium increases with an increase in the composition ratio of germanium in silicon. this is,
This is because the incorporation of germanium into silicon causes stress in the crystal structure, which makes it easier for impurities to enter. Since this stress is also generated by introducing carbon and oxygen into silicon, the shallow source and drain layers 5 can be formed of a silicon layer containing any of germanium, carbon, and oxygen.

FIG. 10 shows a CMOS according to an eighth embodiment of the present invention.
1 shows a cross-sectional view of a transistor. Example 8 corresponds to M of Example 7
This is an example in which an OS transistor is applied to a CMOS transistor. In Example 8, 5 and 18 are shallow source and drain regions containing germanium and have a junction depth d1.
Is a fourth insulating film layer formed on the side wall of the gate electrode and containing no germanium.

FIG. 11 is a sectional view of a MOS transistor according to the ninth embodiment of the present invention. The ninth embodiment is a semiconductor device in which high-voltage and low-voltage MOS transistors are formed on the same semiconductor substrate. In FIG. 11, deep source and drain regions 22 are for forming a high withstand voltage MOS transistor, and shallow source and drain regions 5 containing germanium are for forming a low withstand voltage and high performance MOS transistor. The method of manufacturing the source and drain regions 22 for the high breakdown voltage MOS transistor is the same as the method of manufacturing the MOS transistor of the third embodiment except that the source and drain regions 2 are formed by using the selective growth technique.
2 is covered with a silicon oxide film so as not to form a silicon-germanium mixed crystal semiconductor layer on a region where silicon and germanium mixed silicon semiconductor layers are formed on a region where shallow source and drain regions 5 are formed. Can be realized.

FIGS. 12A to 12C show Embodiment 10 of the present invention.
FIG. 7 is a cross-sectional view illustrating a step example of the method for manufacturing a semiconductor device having the capacitor of FIG. First, as shown in FIG. 12A, an insulating film layer 23 and a first-conductivity-type polycrystalline silicon layer 24 are sequentially formed on the semiconductor substrate 1, and then island-like silicon and germanium of the first-conductivity type are formed. Is formed. The island-shaped mixed crystal semiconductor layer 25 of silicon and germanium has a diameter of about 50 nm, and the mixed crystal semiconductor of silicon and germanium has a large anisotropy during crystal growth, so that it can be easily formed on the polycrystalline silicon layer. it can.

Next, as shown in FIG. 12B, the island-shaped mixed crystal semiconductor layer 2 of silicon and germanium of the first conductivity type is next formed.
5 is used as a mask to selectively etch the first conductivity type polycrystalline silicon layer using a hydrazine solution. As shown in FIG. 2, polycrystalline silicon and silicon germanium can change the etching selectivity rather than changing the composition ratio of germanium in silicon. And FIG.
As shown in (c), an insulating film 26 is formed on the entire surface of the semiconductor substrate 1.
A first conductivity type polycrystalline silicon layer 27 was sequentially formed to form a semiconductor device having a capacitor. According to the present invention, a capacitor having an increased surface area of a semiconductor substrate and an increased capacitance per unit area has been realized.

FIGS. 13A to 13F show Embodiment 11 of the present invention.
FIG. 14 is a cross-sectional view showing a step example of the method for manufacturing a semiconductor device having the bipolar transistor shown in FIG. In FIG. 13A,
Reference numeral 1 denotes a semiconductor substrate, which is, for example, n-type doped.
First, as shown in FIG. 13A, a first insulating film layer 6 for element isolation, a p-type polysilicon layer 28, and a p-type polysilicon layer are disposed on the semiconductor substrate 1 by a known method. The formed insulating film layer 29 is sequentially formed. Next, the insulating film layer 29 and the p-type polycrystalline silicon layer 28 in the base formation region are removed by dry etching to open a base region formation window 30. Next, as shown in FIG. 13B, at 900 ° C. in a nitrogen atmosphere using a lamp heating device.
After performing the heat treatment for 30 seconds to form the external base region 31 by solid-phase diffusion from the p-type polycrystalline silicon layer 28, the mixed crystal semiconductor layer 2 of silicon and germanium is formed. Next, as shown in FIG. 13 (c), boron is introduced into the mixed crystal semiconductor layer of silicon and germanium by ion implantation, and 900 is used in a nitrogen atmosphere using a lamp heating device.
By performing heat treatment at 30 ° C. for 30 seconds, a shallow junction p-type base layer 33 is formed by solid-phase diffusion from the p-type mixed crystal semiconductor layer 32 of silicon and germanium. Next, FIG.
As shown in (d), the mixed crystal semiconductor layer 3 of p-type silicon and germanium is formed by a mixed solution of ammonia, hydrogen peroxide and water.
Remove 2. Next, as shown in FIG. 13E, after forming the insulating film layer 34, the insulating film layer 35 is formed on the side wall in the opening by a known method. Then, after forming an n-type polycrystalline silicon layer 36 as shown in FIG. 13 (f), a heat treatment is performed at 1000 ° C. for 10 seconds in a nitrogen atmosphere using a lamp heating device to thereby form the n-type polycrystalline silicon layer. An n-type emitter region 37 was formed by solid-phase diffusion from. According to this embodiment, a low-resistance and thin base layer 33 is formed, and a high-speed bipolar transistor is realized. In this embodiment, only a bipolar transistor is formed. However, a BiCMOS LSI can be formed by forming a MOS transistor on the same substrate.

FIGS. 14A to 14D show Embodiment 12 of the present invention.
FIG. 14 is a cross-sectional view showing a process example of the method for manufacturing the semiconductor device having the metal gate MOS transistor of FIG. In FIG. 14A, reference numeral 38 denotes a gate electrode formed of a mixed crystal semiconductor of silicon and germanium. First, a MOS transistor having a shallow source and drain 39 is formed by a known method. Next, after depositing the insulating film layer 40, the CM
Using P (Chemical Mechanical Polishing), FIG.
The gate electrode 38 is planarized so as to appear in the insulating film layer 40 as shown in FIG. Next, as shown in FIG. 14C, the mixed crystal semiconductor layer 38 of silicon and germanium is removed with a mixed solution of ammonia, hydrogen peroxide solution, and water to form an opening 41 for forming a gate electrode. Then, as shown in FIG. 14D, a metal gate electrode 42 was formed by filling the opening with a metal, for example, tungsten or a laminated film of tungsten and tungsten nitride, thereby forming a metal gate MOS transistor.

[0045]

According to the present invention, since a mixed crystal semiconductor layer of silicon and germanium can be doped with impurities by ion implantation, a low-resistance and shallow diffusion layer of a desired conductivity type can be formed in a desired region. Was completed. Further, according to the present invention, the source and drain regions of the MOS transistor are formed in a low-resistance and shallow diffusion layer, so that a short-channel effect can be suppressed and a high current driving capability can be obtained. Further, after forming a source and drain region of a mixed crystal semiconductor layer of silicon and germanium serving as a solid-phase diffusion source, the gate capacity is increased by selectively removing the mixed solution with a mixed solution of ammonia, hydrogen peroxide and water. And a shallow junction could be formed.

[Brief description of the drawings]

FIGS. 1A to 1D are views for explaining the steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention in order of steps, and FIGS.

FIG. 2 is a diagram of experimental data showing etching rates of a mixed crystal semiconductor of silicon and germanium with respect to a mixed solution of ammonia, hydrogen peroxide and water (2: 1: 5) and a hydrazine solution.

3A and 3B are cross-sectional views for explaining a difference between a conventional example and a MOS transistor according to the present invention.
(c) is a sectional view of the semiconductor device of the present invention.

FIGS. 4A to 4D are views for explaining the steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention in order of steps, and FIGS.

FIGS. 5A to 5E are views for explaining the steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention in order of steps, and FIGS.

FIGS. 6A to 6E are views for explaining the steps of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention in order of steps, and FIGS.

FIGS. 7A to 7E are views for explaining each step of a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention, and FIGS. 7A to 7E are cross-sectional views of each step;

FIGS. 8A to 8E are cross-sectional views illustrating the steps of a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention. FIGS.

FIG. 9 is a sectional view showing a semiconductor device according to a seventh embodiment of the present invention.

FIG. 10 is a sectional view showing a semiconductor device according to an eighth embodiment of the present invention.

FIG. 11 is a sectional view showing a semiconductor device according to a ninth embodiment of the present invention.

FIGS. 12A to 12C are views for explaining each step of a method of manufacturing a semiconductor device according to a tenth embodiment of the present invention, and FIGS. 12A to 12C are cross-sectional views of each step;

FIGS. 13A to 13F are views for explaining each step of the method for manufacturing a semiconductor device according to the eleventh embodiment of the present invention, and FIGS. 13A to 13F are cross-sectional views of each step;

FIGS. 14A to 14E are views for explaining each step of a method of manufacturing a semiconductor device according to a twelfth embodiment of the present invention, in which FIGS.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Mixed crystal semiconductor layer of silicon and germanium, 3 ... Impurity ion, 4 ... Mixed crystal semiconductor layer of silicon and germanium doped with impurities, 5 ... Contains any element of germanium, carbon, and oxygen Diffusion layer of second conductivity type, 6: first insulating film layer, 7: second insulating film layer, 8
... a second conductivity type polycrystalline silicon gate electrode disposed on the second insulating film layer, 9 ... a third insulating film layer formed on the gate electrode, 10 ... semiconductor substrate, 11 ... gate Fourth insulating film layer on electrode side wall, 12 deep source and drain of second conductivity type, 13 well of second conductivity type, 14
A first conductivity type well, 15 a first conductivity type polycrystalline silicon gate electrode, 16 a mixed crystal semiconductor layer of silicon and germanium doped with a first conductivity type impurity, 17 a second
A mixed crystal semiconductor layer of silicon and germanium doped with a conductive impurity, 18: a shallow source and drain of a first conductive type, 19: a metal electrode layer formed on a polycrystalline silicon gate electrode, 20: a gate electrode side wall Insulating film, 21: deep source and drain of the first conductivity type, 22: high breakdown voltage M
Source and drain for OS transistor, 23 ... insulating film layer, 24 ... polycrystalline silicon layer of first conductivity type, 25 ...
First conductive type island-shaped mixed crystal semiconductor layer of silicon and germanium, 26: insulating film, 27: first conductive type polycrystalline silicon layer, 28: second conductive type polycrystalline silicon layer, 29: insulating film Layer, 30: opening for forming base region, 31: second
A conductive type outer base region, 32: a mixed crystal semiconductor layer of silicon and germanium of a second conductive type; 33, a second conductive type base region; 34, an insulating film layer; 35, inner wall of the opening An insulating film layer of 36, a polycrystalline silicon emitter electrode of the first conductivity type; 37, an emitter region of the first conductivity type; 38, a gate electrode formed of a mixed crystal semiconductor of silicon and germanium;
39... Shallow source and drain of second conductivity type, 40.
Insulating film layer, 41: opening for forming a gate electrode, 42: metal gate electrode, 51: silicon-germanium layer containing boron, 52: silicide layer.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/73 H01L 29/78 301S 29/78 301P 21/336 29/92 (72) Inventor Takeo Shiba Tokyo 1-280 Higashi-Koigakubo, Tokyo-Kokubunji-shi F term in Hitachi Central Research Laboratory, Inc. 5F003 AP00 BB09 BJ15 BJ18 BM01 BP05 BP06 BP21 BP31 BP42 5F040 DA01 DA05 DA10 DA18 DB03 DB07 DB09 EC01 EC07 EC08 EC12 EC13 EF02 EH02 FA04 FA05 FC11 FC19 5F048 AA00 AA08 AB01 AB03 AC03 AC05 AC07 AC10 BA01 BB06 BB07 BB08 BB09 BB12 BC06 BE03 BF06 DA23 DB01 DB06

Claims (10)

[Claims] A step of depositing a mixed crystal semiconductor of silicon and germanium on the surface of a semiconductor substrate; a step of implanting predetermined impurity ions serving as carriers into the mixed crystal semiconductor of silicon and germanium; A step of forming a diffusion layer on the surface of the semiconductor substrate by thermal diffusion from the silicon and germanium mixed crystal semiconductor of the diffusion source, and mixing the silicon and germanium mixed crystal semiconductor with a mixed solution of ammonia, hydrogen peroxide water and water Removing the semiconductor device. A step of forming a gate electrode on a surface of a semiconductor substrate having a first conductivity type via a gate insulating film; a step of depositing a mixed crystal semiconductor of silicon and germanium; a mixed crystal of silicon and germanium; A step of ion-implanting an impurity of a second conductivity type opposite to the first conductivity type into the semiconductor, and solid phase diffusion from the mixed crystal semiconductor of silicon and germanium to the surface of the semiconductor substrate on both sides of the gate electrode. Forming a shallow diffusion layer of the second conductivity type;
Removing the mixed crystal semiconductor of silicon and germanium. 3. A method of manufacturing a semiconductor device having an nMOS and a pMOS, comprising: forming a gate electrode on a surface of a semiconductor substrate via a gate insulating film; and depositing a mixed crystal semiconductor of silicon and germanium. And ion-implanting a corresponding conductivity type impurity into the silicon-germanium mixed crystal semiconductor in each of the nMOS and pMOS formation regions by using a photoresist as a mask, and the silicon-germanium mixed crystal semiconductor. Forming a shallow diffusion layer on the surface of the semiconductor substrate on both sides of the gate electrode by solid diffusion from the substrate, and removing the mixed crystal semiconductor of silicon and germanium. . 4. The method according to claim 1, wherein the gate electrode is formed in a polymetal structure, and between the gate electrode forming step and the depositing step.
3. The method according to claim 2, further comprising the step of forming an insulating film on both side surfaces of the gate electrode, wherein in the ion implantation step, the depth of the shallow diffusion layer is larger than the thickness of the insulating film. 4. The method for manufacturing a semiconductor device according to item 3. 5. The method according to claim 2, wherein a mixed solution of ammonia, hydrogen peroxide and water is used in said removing step. 6. The method according to claim 1, further comprising the steps of: forming a side wall insulating film on both side surfaces of said gate electrode; and forming a second conductive type deep diffusion layer by ion implantation. 6. The method for manufacturing a semiconductor device according to 2 to 5. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the mixed crystal semiconductor of silicon and germanium is formed of amorphous or polycrystalline. 8. The method according to claim 1, wherein in said ion implantation step, 10 ²⁰
8. The method for manufacturing a semiconductor device according to claim 1, wherein an impurity is doped at a rate of not less than an impurity / cm ³ . 9. A semiconductor device having a MOS transistor, wherein the MOS transistor has shallow source and drain regions containing germanium, carbon, or oxygen at a high concentration, and sidewalls of a gate electrode side wall containing no germanium. And a semiconductor device comprising: 10. The shallow source and drain region has a diffusion depth of 30 nm or less.
3. The semiconductor device according to claim 1.