JP2001051908A - Printed circuit board, method and device for reading data and checking write data, data writer and connector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed circuit board capable of surely reading data in a ROM from the outside, a method and a device for reading data, a method and a device for checking write data with which a write check error does not occur, a data writer and a connector. SOLUTION: The printed circuit board, which has another storage device parallel connected with a flash ROM (FROM) 12 of a storage device by a data bus extended from a CPU 11, connecting a chip select signal line extended from the CPU 11 to respective storage devices to a connector 13 for data write as well is attached to a converting board attached to a ROM writer. In the case of performing the write check of the FROM 12, data are read out of the FROM 12 while turning the FROM 12 into valid state and turning the other storage device into invalid state. Thus, output data from the other storage device are not outputted and the write check error does not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a storage device including an IC such as an electrically rewritable ROM (Read Only Memory) and an IC connected in parallel with the storage device via a data bus extending from a bus master. The present invention relates to a printed circuit board such as a facsimile control board equipped with another storage device. Also,
The present invention relates to a data reading method for reading data stored in a predetermined storage device among a plurality of storage devices mounted on a target board such as the printed circuit board, and a device therefor. Further, the present invention provides write data for checking whether write data written to a predetermined storage device among a plurality of storage devices mounted on a target board such as the printed board is correctly written. The present invention relates to an inspection method and an inspection device. Furthermore, the present invention relates to a data writing device having the function of the write data inspection device, and a connector for connecting the data writing device to a target board such as the printed circuit board.

[0002]

2. Description of the Related Art As a storage device comprising an electrically rewritable IC, an EPROM (Erasable Programmable Programmable Programmable Programmable Programmable Memory) capable of erasing written data by ultraviolet rays or the like and writing data again can be used.
ble ROM) and flash EEPROM of batch erase type
OM (Electric Erasable Prog)
ramble ROM; hereinafter simply referred to as “flash R
OM ". ) Are known. In order to reduce the size of products, flat-package flash ROMs for surface mounting are often used.

Conventionally, when data is written in such a ROM, the ROM is stored in a state separate from the printed circuit board on which the ROM is mounted, that is, in a state of a single ROM.
It was mounted on an M writer to write data. After the writing operation is completed, the ROM in which the data is written is mounted on the printed circuit board by soldering. However, in such a writing method, the ROM
When the lead is removed from the ROM writer, the lead is bent, and defects such as defective soldering are likely to occur.

To solve such a problem, Japanese Patent Application Laid-Open No. 9-274798 discloses a method in which an electrically rewritable ROM is mounted on a printed circuit board and a predetermined ROM is mounted.
A writing method capable of writing program data in the ROM using a writer has been proposed. According to this method, the ROM is mounted on a printed circuit board, and then program data is written into the ROM.
There is no work to remove the ROM from the writer, and the lead does not bend.

The present applicant has also proposed a data writing device for writing write data to a predetermined ROM while a plurality of electrically rewritable ROMs are mounted on a printed circuit board (Japanese Patent Application No. Hei 10-26139). 11-162164). This data writing device can automatically write predetermined write data into each ROM even if two or more ROMs are mounted on one printed circuit board, so that the work efficiency is correspondingly increased. Can be improved.

In a data writing apparatus disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 9-274798 or Japanese Patent Application No. 11-162164, a flash ROM to be written from a CPU as a bus master mounted on the printed circuit board is used. The data is written to the flash ROM using a data bus or address bus extending to the flash ROM. When writing the data, the CPU reads the flash ROM
A chip select signal, which is a write operation signal for making the flash ROM writable, is sent from outside using a chip select signal line extending to the flash ROM to make the flash ROM valid. Specifically, the data bus, the address bus, the chip select signal line connected to the flash ROM, and the like are led out to an interface section provided on the printed board, and the CPU is connected to the CPU.
Is set to the sleep state to write data.

[0007]

However, after writing data by such a method, the flash RO
When the write data written in M is checked, an error occurs even though the write data is correctly written in the flash ROM. This problem occurs because, when the write data is read from the flash ROM in the write check, data is also output from another storage device such as an SRAM or a ROM on the printed circuit board. It turned out that there is.

More specifically, the flash ROM to be read is connected in parallel with another storage device such as the above-described SRAM or ROM by a data bus wired on the printed circuit board. Also, when reading out the write data written in the flash ROM at the time of writing check, the read data can be read out of the ROM by using the data bus.
Read to writer and check write. Therefore, if data is also output from another storage device during a write check, the output from the other storage device and the flash RO
The output from M collides with the data bus, and an error occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a first object of the present invention is to provide a printed circuit board, a data reading method, and a data reading device capable of reliably reading data to be read. That is. A second object is to provide a write data inspection method, a write data inspection device, a data write device, and a connector which do not cause a write check error when checking write data written in a predetermined storage device. It is to provide.

[0010]

In order to achieve the first object, the invention according to claims 1 to 3 is directed to a storage device comprising an electrically rewritable IC and a data bus extending from a bus master. IC connected in parallel with the device
And an interface unit for controlling the storage device and the other storage device from outside, and the data bus is connected to the interface unit for reading data of the storage device from outside. A read operation signal line for connecting the interface unit and the storage device and transmitting a read operation signal for making data in the storage device readable from the outside on the printed circuit board; A read operation disable signal line for connecting the interface unit and the other storage device and transmitting a read operation disable signal for making data in the other storage device unreadable from the outside; It is characterized by the following.

In this printed circuit board, when data is read from a storage device to be read, another storage device connected in parallel with the storage device by a data bus can be made unreadable. . Therefore, when data is read from the storage device, no data is output from the other storage device. Further, in this printed circuit board, data is not output from the other storage device. Therefore, when a write check is performed on a storage device mounted on the printed circuit board, the write data is read. Sometimes, a collision between the output from the storage device and the output from another storage device can be avoided.

In particular, according to a second aspect of the present invention, in the printed circuit board of the first aspect, the read operation signal line is a transmission line branched from a chip select signal line connecting between the bus master and the storage device. It is characterized by the following. If the read operation signal line is separately provided, circuit design becomes very difficult. Therefore,
In this printed circuit board, a transmission line is branched from a chip select signal line provided on the printed circuit board to form the read operation signal line.

[0013] The invention of claim 3 is the invention of claim 1 or 2.
Wherein the read operation disable signal line is a transmission line branched from a chip select signal line connecting the bus master and the other storage device. As in the case of the above-mentioned read operation signal line, if the above-mentioned read operation disable signal line is additionally provided, circuit design becomes very difficult. Therefore, in this printed circuit board, the transmission line is branched from the chip select signal line provided on the printed circuit board to form the above-mentioned read operation disable signal line.

According to a fourth aspect of the present invention, there is provided a storage device comprising an electrically rewritable IC and a data bus extending from a bus master connected in parallel with the storage device. The data stored in the storage device on the target board provided with another storage device including an IC and an interface unit for externally controlling the storage device and the other storage device is transmitted to the interface unit. In the data read method for reading from the outside using the connected data bus, when reading data from the storage device, the storage device is set to a readable state, and the other storage device is set to a non-readable state. It is characterized by the following.

In this data reading method, when data is read from a storage device to be read provided on the target board, another data storage device connected in parallel with the storage device via the data bus cannot be read. After the state, the data stored in the storage device is read. Therefore, at the time of this data reading, no data is output from the other storage device. When performing a write check of the write data written in the storage device,
If the data read method is applied when reading the write data, it is possible to avoid a situation in which the output from the storage device and the output from the other storage device collide.
Note that this data reading method is not limited to data reading performed at the time of writing check, and can be widely applied to a method of reading data from a recording device including an IC mounted on a target board.

In a fifth aspect of the present invention, the target board is the printed circuit board of the first, second or third aspect, and the data read from the storage device on the printed circuit board is read out. Transmitting the read operation signal to the storage device via the read operation signal line, and transmitting the read operation disable signal to the other storage device via the read operation disable signal line. It is a feature. In this data reading method, it is possible to read only the data stored in the storage device to be read, which is mounted on the printed circuit board according to the first, second, or third aspect of the present invention.

According to a sixth aspect of the present invention, there is provided a storage device comprising an electrically rewritable IC and an IC connected in parallel with the storage device by a data bus extending from a bus master. Data stored in the storage device on the target board including another storage device consisting of: and an interface unit for externally controlling the storage device and the other storage device, and connected to the interface unit. A data read device for reading data from the outside using the data bus, a read operation signal output means for outputting a read operation signal for making data in the storage device readable from the outside, Read operation disable signal output means for outputting a read operation disable signal for making data unreadable from the outside. .

In this data reading device, when data is read from a storage device to be read provided on a target board, another data storage device connected in parallel with the storage device via a data bus cannot be read. State. Therefore, when data is read from the storage device, no data is output from the other storage device. Further, when performing a write check of the write data written in the storage device, if the data read device is used when reading the write data, the output from the storage device and the output from the other storage device can be performed. It is possible to avoid a situation where the output collides with the output. The data reading device is not limited to data reading performed at the time of writing check, and can be widely applied to a device that reads data from a recording device including an IC mounted on a target board.

According to another aspect of the present invention, there is provided a storage device comprising an electrically rewritable IC, and an IC connected in parallel with the storage device by a data bus extending from a bus master. The write data written to the storage device on the target board provided with another storage device consisting of, and an interface unit for externally controlling the storage device and the other storage device is written to the interface unit. 6. The data according to claim 4, wherein said read data is read out in a write data inspection method for reading out externally using said connected data bus and checking whether said write data is correctly written. It is characterized by using a reading method.

This write data inspection method reads out write data written in a storage device provided on a target board and checks whether the write data is written to a correct address or not. A write data check is performed to determine whether the write data is the same as the write data. In this write data inspection method, when reading out the write data written in the storage device at the time of this write data inspection, the above-described data read method of claim 4 or 5 is applied. Thus, only the write data written in the storage device can be read without the output from the storage device colliding with the output from the other storage device.

According to another aspect of the present invention, there is provided a storage device comprising an electrically rewritable IC and an IC connected in parallel with the storage device by a data bus extending from a bus master. The write data written to the storage device on the target board provided with another storage device consisting of, and an interface unit for externally controlling the storage device and the other storage device is written to the interface unit. 7. A write data inspection device for reading out to the outside using the connected data bus and checking whether or not the write data is correctly written, wherein the data read device according to claim 6 and the write data are correctly written. Inspection means for inspecting whether data has been written is provided.

This write data inspection apparatus reads write data written in a storage device provided on a target board, and checks whether the write data is written to a correct address or not. A write data check is performed to determine whether the write data is the same as the write data. Since the write data inspection device includes the data read device according to claim 6 described above, when reading write data written in the storage device at the time of a write check, an output from the storage device is used. The output from the other storage device does not collide.

In order to achieve the second object, the invention of claims 9 and 10 is directed to a storage device comprising an electrically rewritable IC and a data bus extending from a bus master connected in parallel with the storage device. Connecting means connectable to the storage device on the target board, which is provided with another storage device comprising an integrated IC and an interface unit for controlling the storage device and the other storage device from outside After writing the write data via the data bus, reading the write data using the data bus connected to the interface unit, and checking whether the write data is correctly written. In a data writing device provided with an inspection unit, the write data inspection unit includes:
A write data inspection apparatus according to claim 8 is characterized.

The data writing device according to claim 8, as write data inspection means for writing write data to a storage device on a target board, and then reading the write data to perform a write check. A write data inspection device is used. Therefore, only the write data written in the storage device can be read without the output from the storage device colliding with the output from the other storage device.
The connection means may be fixedly provided in the data writing device or may be detachably provided in the data writing device main body as long as the connection means can be connected to the interface unit provided on the target board. Is also good.

In a tenth aspect of the present invention, in the data writer according to the ninth aspect, wherein the write data is written and inspected by using a ROM writer having a ROM socket, the connection means includes an interface of the target board. It is a connector for connecting the unit and the ROM socket. In this data writing device, the ROM socket of the ROM writer can be connected to the interface section of the target board by a connector separately formed from the ROM writer that is the main body of the data writing device. If this connector is configured to conform to the shape of the interface unit, there is no need to change the configuration of the data writing device main body. Therefore, when writing data to a recording device mounted on a target board and then reading out the writing data to perform a writing check, an RO having a ROM socket generally used conventionally has
It becomes possible to use an M writer.

According to another aspect of the present invention, there is provided a storage device comprising an electrically rewritable IC, and an IC connected in parallel with the storage device by a data bus extending from a bus master. 7. An interface unit provided on a target board on which the storage device and the other storage device are mounted, in order to externally control the other storage device comprising: and a data writing device having the function of the data reading device of claim 6. A connection device for connecting the data input / output unit of the device to the data input / output unit; a read operation signal line for transmitting a read operation signal output from the data input / output unit to the storage device on the target board; A read operation signal line transmitted to the other storage device on the target board.

According to the present invention, there is provided a connector comprising: an interface section of a target board such as a printed circuit board according to claim 1, 2 or 3; Connect.
The connection device transmits a read operation signal output from the data writing device to a storage device to be read mounted on the target board via a read operation signal line provided in the connection device. can do. Also, the read operation disable signal output from the data writing device is transferred to another storage device that is not mounted on the target board and is not a read target via the read operation disable signal line provided in the connector. Can be transmitted. still,
If the connection tool is provided with a read operation disable signal output means, the read operation disable signal output from the read operation disable signal output means is mounted on the target board via the read operation disable signal line. It can also be transmitted to another storage device that is not a read target. Therefore, only the write data written in the storage device can be read without the output from the storage device colliding with the output from the other storage device. Further, the structure of the connection tool is simply configured to conform to the shape and structure of the interface unit, and is not limited to the structure of the data input / output unit of the data writing device. Data can be read.

[0028]

[Embodiment 1] Hereinafter, the present invention will be described.
Printed circuit board (hereinafter referred to as “PC
B ". An embodiment (hereinafter, this embodiment is referred to as “Embodiment 1”) applied to a case where data is written in a flash ROM as a recording device including an electrically rewritable IC mounted thereon will be described.

First, the configuration of the entire data writing device used in this embodiment will be described. FIG. 1 is a block diagram showing a schematic configuration of the data writing device of the present embodiment. FIG. 2 is a perspective view showing the data writing device with the PCB attached. This data writing device 1 is a ROM having a plurality of ROM sockets 31 as data input / output units.
It is composed of a writer 3 and a conversion board 2 which is a connector for connecting the PCB 10 to the ROM socket. The conversion board 2 is configured to be detachable from a ROM writer 3 which is a main body of the data writing device. In the data writing device 1, program data, which is write data output from the ROM writer 3, is transferred to the flash board already mounted on the PCB 10 via the conversion board 2 attached to the ROM socket 31. The data is written to the ROM 12.

The ROM writer 3 has two rows of sockets in which eight ROM sockets 31 are arranged. On the other hand, a ROM writer connector connected to the ROM socket 3 is provided on the lower surface of the conversion board 2 so as to correspond to the socket row. Therefore, in the case of the present embodiment, it is possible to attach two conversion boards 2 to the ROM writer 3. FIG. 2 shows the data writing device 1 in a state where the conversion board 2 is attached only to the socket row located on the back side in the figure.

The conversion board 2 is provided with eight connection connectors 21 that can be connected to the PCB 10.
Up to eight PCBs 10 can be attached. Therefore, the data writing device 1 of the present embodiment can write data into the flash ROMs 12 on up to 16 PCBs 10.

Next, the structure of the PCB 10 will be described. FIG. 3 is a block diagram showing a schematic configuration of the PCB 10. As shown in FIG. The PCB 10 includes a CPU 11 functioning as a bus master, the flash ROM 12, the SRAM 14, which is another recording device including an IC connected in parallel with the flash ROM and a data bus, and a non-electrically rewritable memory such as a mask ROM, EPR
An OM (hereinafter simply referred to as "ROM") 15 and a data writing unit which controls the recording device and the like including the flash ROM from the outside and forms an interface unit for writing and reading data to and from the flash ROM. Plug connector 13.

On the PCB 10, a power supply line for operating the CPU 11 and the recording devices (12, 14, 15) on the PCB, an address bus for transmitting address data, and write and read data are stored. A data bus for transmission; a plurality of control signal lines for transmitting control signals such as read signals and write signals;
A chip select signal line for transmitting a chip select signal to each recording device on the CB and a sleep signal line for transmitting a sleep signal for stopping the function of the CPU and putting it into a sleep state are printed and wired. I have. In FIG. 3, a plurality of control signal lines are connected to one.
It is represented by a book line.

An address bus extending from the CPU 11,
The data bus and the control signal line are branched on the way and connected to the respective recording devices (12, 14, 15), and are also drawn out to the data write connector 13. Also, the power supply line is connected to the data write connector 13.
Power can be externally supplied to each section of the PCB 10 via the data write connector. The sleep signal line connected to the CPU 11 is also drawn to the data write connector. In the present embodiment, each chip select signal line extending from the CPU 11 toward each of the recording devices (12, 14, 15) is also drawn out to the data write connector 13. Among the extracted chip select signal lines, the chip select signal line of the flash ROM 12 functions as a chip enable signal line as a read operation signal line for transmitting a chip enable signal as a read operation signal. The (14, 15) chip select signal line functions as a chip disable signal line as a read operation disable signal line for transmitting a chip disable signal as a read operation disable signal.

In this embodiment, since the three storage devices on the PCB 10 are the flash ROM 12, the SRAM 14, and the ROM 15, all of the chip select signal lines connected to each storage device are connected to the data write connector 13. The structure is drawn out. However, it is not necessary to pull out the chip select signal line from all the other storage devices connected in parallel with the flash ROM 12 to be read. That is, the chip select signal line functioning as the chip disable signal line is
At least it is sufficient to extract data only from another storage device that causes a problem when reading data from the read target.

During normal operation in which the PCB 10 is mounted on a facsimile and operates, the CPU 11
Is a flash ROM using the chip select signal.
12 and other recording devices (14, 15) are appropriately enabled, and each recording device is controlled using an address bus, a data bus, and a control signal line. However, when writing data to the flash ROM 12 and reading data from the flash ROM when manufacturing the PCB 10 or rewriting program data written in the PCB, the data writing Connector 1
The CPU 11 is put into a sleep state by a sleep signal input from the conversion board 2 via the CPU 3, and the flash ROM and the other recording devices (14, 15) can be controlled from the outside.

Next, the configuration of the conversion board 2 constituting the data writing device 1 will be described. FIG. 4 is a block diagram showing a schematic configuration of a portion of the conversion board 2 for connecting one ROM socket 31 provided on the ROM writer 3 and the data write connector 13 of one PCB 10. The conversion board 2 has a connector 21 connected to the data write connector 13 of the PCB 10.
A ROM writer connector 22 connected to the ROM socket 31 of the ROM writer 3, and a power supply voltage for supplying power to the PCB by following a power supply voltage from the ROM writer 3 supplied via the ROM writer connector. The follow-up supply unit 23 and an RO for inputting a signal to the PCB
And a buffer unit 24 for reducing the drive load of the M writer 3. In the present embodiment, the sleep signal is set at the GND level.

As shown in FIG. 5 (a), the power supply voltage follow-up supply section 23
The output from the DC power supply 23a is turned on / off by the relay 23b by the power supply voltage supplied through the writer connector 22.
By performing the off control, a device that supplies power to the PCB 10 from the DC power supply via the connection connector 21 can be used. Also, as shown in FIG.
The power supply voltage supplied from the ROM writer 3 via the ROM writer connector 22 changes the output voltage from the DC power supply 23a to an operational amplifier 23c and a transistor 23.
d, and the PC is connected via the connector 21.
A device that supplies power to B10 can also be used. As described above, by providing the DC power supply 23a having a sufficient power supply current capacity on the conversion board 2 as an external power supply of the ROM writer 3, even if the power consumption of the PCB 10 is large, the power is supplied from the ROM writer. The power supply current can be supplied to various types of PCBs without any problem without being limited by the power supply voltage.

As shown in FIG. 4, the buffer unit 24 includes an address bus, a data bus, a control signal line, and a chip enable signal for transmitting various data and signals transmitted and received between the ROM writer 3 and the PCB 10. It is provided in the middle of the line. This buffer unit 24
It comprises a unidirectional bus buffer provided in the middle of the address bus, control signal line and chip enable signal line, and a bidirectional bus buffer provided in the middle of the data bus. The power of the buffer unit 24 is also supplied from the power supply voltage follow-up supply unit 23. Thus, the ROM writer 3 and the PCB 10
By providing the buffer unit 24 in the conversion board 2 that connects between the two, the load seen from the ROM writer side is only the load of this buffer unit.

The conversion board 2 is provided with two chip disable signal lines for transmitting a chip disable signal. These chip disable signal lines are connected to the SRAM 14 and the ROM on the PCB 10.
15 are respectively connected to two chip select signal lines. These chip disable signal lines are connected to the power supply voltage follow-up supply unit 23.
Therefore, when a voltage is applied to the chip disable signal line while the data write connector 13 of the PCB 10 is connected to the connection connector 21, the PCB
Similarly to the chip select signal output by the CPU 11 on the normal state, the terminals of the SRAM 14 and the ROM 15 can be set to a High state to invalidate the SRAM and the ROM. That is, the power supply voltage following supply unit 23 functions as a read operation disable signal output unit.

In the conversion board 2 of the present embodiment, the PC
The storage device existing on B10 is a flash ROM 1
2. Since there are three, SRAM 14 and ROM 15, 1
The configuration is such that one chip enable signal line and two chip disable signal lines are provided. But,
The chip enable signal line and the chip disable signal line are appropriately selected according to the number of chip select signal lines drawn to the data write connector 13 on the PCB 10.

Next, the R that constitutes the data writing device 1
The configuration of the OM writer 3 will be described. FIG.
FIG. 3 is a block diagram illustrating a schematic configuration of a part of an OM writer 3; This ROM writer 3 is a ROM of the conversion board 2
A ROM socket 31 connected to the writer connector 22,
An input interface unit 32 as an instruction input unit for an operator to input a predetermined instruction, and a control unit 33 as a control unit for controlling each unit of the ROM writer 3 based on an instruction signal from the input interface unit. And the above P
A memory as storage means for storing program data as write data to be written into the flash ROM 12 of the CB 10, and a chip enable signal for enabling the flash ROM 12 on the PCB under the control of the control unit are generated. A chip enable signal generating circuit (35a, 35b, 35c) for outputting the data and a data output circuit 3 for temporarily holding the write data output from the control unit and writing the write data to the flash ROM
6, an address data output circuit 37 for temporarily holding the address data output from the control unit and giving an address to the flash ROM, and an end notifying means for notifying the worker of the end of the writing operation. End ramp 38 which is
It is composed of Further, the ROM writer 3 is provided with an NG lamp (not shown) as an error notifying means for notifying an operator of an error in the data writing step and the writing check step.

The control unit 33 includes a CPU, a step of writing data to the flash ROM 12,
It is composed of a PROM or the like in which an execution program for performing an OM write check step is stored, and controls each section of the ROM writer 3 based on an instruction signal from the input interface section 32. The memory 34 stores program data to be written in the flash ROM 12. When a write check is performed by the ROM writer 3, the control unit 33 functions as an inspection unit.

Each of the chip enable signal generation circuits (3
5a, 35b, 35c) function as read operation signal output means. That is, under the control of the control unit 33,
A chip enable signal for enabling the flash ROM 12 on the PCB 10 is generated and output. The chip enable signal according to the present embodiment is a low-level signal, similarly to the chip select signal output by the CPU 11 on the PCB 10 during normal operation.

Next, a data writing process and a writing check process of the data writing device 1 will be described. In order to simplify the description, one PCB 10 is attached to the connector 21 corresponding to the ROM socket 31a, and data is written to the flash ROM 12 on the PCB. Will be described.

First, in starting these steps,
The ROM sockets 3 of the ROM writer 3 corresponding to the respective ROM writer connectors 22 of the conversion board 2
1 and the conversion board is attached to the ROM writer. Then, the flash ROM 12 or another recording device (1
The data write connector 13 of the PCB 10 on which the PCBs (4, 15) and the like are mounted by soldering is mounted on the connection connector 21 of the conversion board 2, and the PCB is mounted on the conversion board. At this time, the sleep signal line of the data write connector 13 is at the GND level (Low level).
And the CPU 11 of the PCB 10 enters the sleep state. As a result, the flash RO
M12 and other recording devices (14, 15)
The flash ROM and other recording devices can be controlled by the ROM writer 3 electrically.

FIG. 7 is a flowchart showing the operation of the ROM writer 3. First, when a worker gives an instruction to start writing from the input interface unit 32 of the ROM writer 3, the writing operation is started, and it is checked whether or not the flash ROM 12 to be written exists (S1). If it is determined that the flash ROM 12 is present, the chip enable signal generation circuit 35a supplies the flash ROM to the flash ROM.
A chip enable signal is output to OM. By the chip enable signal, the flash ROM 1
2 is dropped to a low level, and enters an enable state in which data can be written and read. On the other hand, when the power supply is started by the power supply voltage follow-up supply unit 23 of the conversion board 2, a chip disable signal is output to the other recording devices (14, 15), and these recording devices are set to Hig.
The level becomes the h level, and the other recording device enters a disabled state in which data cannot be written or read. Then, a write signal, which is a control signal, is enabled, and the mode shifts to the write mode (S2). In addition, Flash RO
When it is determined that M does not exist, the writing operation ends.

When the mode shifts to the write mode, the control unit 33 reads out write data for address 0, which is a start address, from the memory 34, outputs the write data to the data output circuit 36, and outputs the data to the address output circuit 37. The address data 0 is output, and at the same time, a timer in which a predetermined write operation time is set is reset (S3). When the write operation is started, the write data output from the data output circuit 36 is transferred from the ROM socket 31a to the PCB 1 via the conversion board 2.
0 is written to the flash ROM 12 above. The write data for address 1 is written next, but the same procedure is performed thereafter.

While the writing operation is being performed in this manner, the timer determines whether or not a predetermined writing operation time has elapsed (S4). When the writing operation time elapses, the mode shifts to the writing check mode (S5).

After shifting to the write check mode, a read signal as a control signal is enabled, and data written in the flash ROM 12 is read (S6). Then, based on the read data from the flash ROM 12, it is checked whether or not data has been written to the flash ROM (S7). If it is determined that no data has been written, the process returns to S2. On the other hand, if it is determined that the data has been written, it is checked whether the data has been correctly written in the flash ROM 12 (S
8).

In S8, the control unit 33 compares the read data read from the flash ROM 12 to be read with the write data stored in the memory 34. As a result of the comparison, if the read data is different from the write data, it is determined that the data has not been correctly written, the NG lamp is turned on (S9), and the write operation ends. On the other hand, if the read data is the same as the write data, it is determined that the data has been correctly written, the end lamp 38 is turned on (S10), and the write operation ends.

As described above, according to the present embodiment, when the write data written in the flash ROM 12 is checked,
Since the other recording devices (14, 15) connected in parallel with the flash ROM by the data bus are disabled, the ROM writer 3 can read only the output data from the flash ROM. . Therefore, in this write check step, it can be accurately checked whether or not the write data has been correctly written.

[Embodiment 2] Next, the present invention is applied to a case where data is written to a flash ROM as a recording device comprising an electrically rewritable IC mounted on a printed board as a target board. (Hereinafter, this embodiment is referred to as “Embodiment 2”). In the first embodiment, the chip disable signal line provided on the conversion board 2 is connected to the power supply voltage follow-up supply unit 23, so that the SRAM 14 and the ROM 15
Is disabled, but in the present embodiment, the R
This embodiment differs from the first embodiment in that the SRAM 14 and the ROM 15 are disabled by a chip disable signal from the OM writer 3. The other configuration is the same as that of the first embodiment, and the description is omitted.

FIG. 8 shows a conversion board 1 according to this embodiment.
FIG. 2 is a block diagram illustrating a schematic configuration of a portion of the ROM 02 that connects one ROM socket 31 provided on the ROM writer 103 and the data write connector 13 of one PCB 10. The buffer unit 124 provided on the conversion board 102 is connected to the ROM writer 103 and the PCB
It is provided in the middle of an address bus, a data bus, a control signal line, a chip enable signal line, and a chip disable signal line for transmitting various data and signals transmitted to and received from the device 10. The buffer unit 124 includes a unidirectional bus buffer provided in the middle of the address bus, the control signal line, the chip enable signal line and the chip disable signal line, and a bidirectional bus buffer provided in the middle of the data bus. It is composed of

FIG. 9 is a block diagram showing a schematic configuration of a part of the ROM writer 103. This ROM writer 1
03 has substantially the same configuration as that of the first embodiment shown in FIG. 6, but has a chip enable signal generation circuit (35
a, 35b, 35c), a chip enable / disable signal generating circuit (135a, 35b) for generating and outputting a chip enable signal and a chip disable signal.
135b and 135c) are different from those of the first embodiment. This chip enable / disable signal generation circuit (135a, 135b, 135
c) Under the control of the control unit 33, a chip enable signal for enabling the flash ROM 12 on the PCB 10 and a chip enable signal for disabling the other storage devices (14, 15). An appropriate enable signal is generated and output.

Each of the chip enable / disable signal generation circuits (135a, 135b, 135c) functions as read operation signal output means and read operation disable signal output means. That is, in the data writing step, under the control of the control unit 33, a chip enable signal for enabling the flash ROM 12 on the PCB 10 is generated and output, and another chip enable signal on the PCB is generated. A chip disable signal for disabling the storage devices (14, 15) is generated and output. The chip enable signal and the chip disable signal in the present embodiment are the same as the chip select signal output by the CPU 11 on the PCB 10 during normal times.

As described above, according to the present embodiment, when inspecting the write data written in the flash ROM 12,
Since the other recording devices (14, 15) connected in parallel with the flash ROM by the data bus are disabled, the ROM writer 3 can read only the output data from the flash ROM. . Therefore, in this write check step, it can be accurately checked whether or not the write data has been correctly written.

[Embodiment 3] Next, the present invention is applied to a case where data is written in a flash ROM as a recording device comprising an electrically rewritable IC mounted on a printed board as a target board. Another embodiment (hereinafter, this embodiment is referred to as “third embodiment”) will be described. In the first and second embodiments, the flash ROM to be read in the write check step is P
Although the case where only one is mounted on the CB has been described, the present embodiment differs from the first and second embodiments in that a data writing step and a writing check step are performed on a PCB on which two flash ROMs are mounted. Different from 2. In the present embodiment, write data is sequentially written to the two flash ROMs, and then the data written to the two flash ROMs is checked for writing. The other basic configuration is the same as that of the data writing device according to the first embodiment.

FIG. 10 shows a schematic configuration of a portion of the conversion board 202 of the present embodiment for connecting one ROM socket 31 provided on the ROM writer 3 and the data write connector 13 of one PCB 10. FIG. In this conversion board 202, the PC
Transmitting a chip disable signal for disabling other storage devices (14, 15) on B10 2
One chip disable signal line is used in the first embodiment.
As in the case of the power supply voltage supply unit 23. This makes it possible to disable the other storage devices (14, 15) on the PCB 10 when a voltage is applied.

The conversion board 202 includes the P
A chip select signal line for transmitting a chip select signal for appropriately enabling or disabling two flash ROMs on the CB 10 is provided. These two chip select signal lines are RO
The chip enable signal generation circuit (35a,
35b, 35c) are connected to a chip select signal generation circuit provided in place of the chip select signal generation circuit. This chip select signal generation circuit functions as a read operation signal output unit and a read operation disable signal output unit, and under the control of the control unit 33,
A chip select signal for enabling one of the two flash ROMs on the PCB and appropriately disabling the other is output to each flash ROM.

In a write check step that is performed after writing data to each of the two flash ROMs, a chip select signal is first sent to one of the flash ROMs under the control of the control unit 33. The flash ROM is enabled and the flash ROM
A write check process is performed on the OM. Then, a chip select signal is sent to the other flash ROM to enable the flash ROM, and a write check process is performed on the flash ROM.

In this embodiment, two flashes R
A case has been described in which the write check process of the two flash ROMs is performed after the data write process of the OM is completed. However, the data write process and the write check process of the one flash ROM are performed. Thereafter, the data writing step and the writing check step may be performed on the other flash ROM. In this embodiment, the configuration in which the chip disable signal line on the conversion board 202 is connected to the power supply voltage follow-up supply unit 23 in order to disable the other storage devices (14, 15) has been described. As in the second embodiment, the chip disable signal line on the conversion board 202 may be connected to a ROM writer, and a chip disable signal may be sent from the ROM writer.

As described above, according to the present embodiment, even when the write data written in the two flash ROMs provided on the PCB is to be inspected, the data buses are used to connect these flash ROMs in parallel. Since the other recording devices (14, 15) that have been written are in the disabled state, the ROM writer 3 can read only the output data from the flash ROM. Also, when a write check is being performed on one flash ROM, the other flash ROM can be disabled, so that the ROM writer 3 reads only output data from the one flash ROM. be able to. Therefore, in this writing check step,
It is possible to accurately check whether or not the write data is correctly written.

In Embodiments 1, 2 and 3 described above,
The other recording devices (14, 15) on the PCB cause a problem at the time of writing check, but do not cause a problem at the time of data writing. Therefore, in the above-described embodiment, the other recording devices (14, 15) are disabled after determining whether or not a ROM exists (S1). However, at least at the time of reading data at the time of writing check. If the other recording device is disabled, the other recording device may be disabled at any time.

In the first, second and third embodiments, since the data writing device 1 has a function of performing a writing check, the data writing device performs the data writing step and the writing check. Although the case where the process is performed has been described, the data writing device performs only the data writing process, and uses the write data inspection device as the write data inspection device having the same function as the above-described write check process. A check check process may be performed.

In the first, second and third embodiments, only the case where data is read from the flash ROM 12 on the PCB 10 has been described.
The present invention can also be applied to a case where data of another storage device (14, 15) on the PCB is read. In this case, an enable signal line or a chip select signal line connected to the flash ROM 12 is applied as a read operation disable signal line, and another disable signal line connected to another storage device to be read, for example, the ROM 15, is read operation signal line. In this case, data can be read from the ROM without any problem.

In the first, second and third embodiments, the case where data is written to the flash ROM which is a batch erasing type electrically rewritable recording device has been described. If the recording device is composed of simple ICs, it is not limited to the batch erase type,
It can be applied to PROM. The present invention also relates to a PCB applied to a facsimile control boat.
However, the present invention is not limited to this and can be applied as long as a plurality of recording devices including an electrically rewritable IC are mounted.

[0068]

According to the first to third aspects of the present invention, there is provided an excellent printed circuit board capable of reliably reading out data from a recording device comprising an IC mounted on the printed circuit board. effective. In particular, when data is read from the recording device on the printed circuit board to perform a write check, there is also an excellent effect that a write check error does not occur.

According to the fourth and fifth aspects of the invention, there is an excellent effect that it is possible to provide a data reading method capable of reliably reading data from a recording device comprising an IC mounted on a target board. . In particular, in the case of performing a write check by reading data using this data reading method, there is also an excellent effect that a write check error can be prevented.

According to the invention of claim 6, there is an excellent effect that it is possible to provide a data reading device capable of reliably reading data from a recording device comprising an IC mounted on a target board. In particular, when a write check is performed by reading with this data reading device, there is also an excellent effect that occurrence of a write check error can be prevented.

According to the seventh aspect of the present invention, when data is read from a storage device on the target board, data of another storage device is not output, so that a write check error occurs when performing a write check on the storage device. There is an excellent effect that it is possible to provide a write data inspection method that does not cause any problem.

According to the eighth aspect of the present invention, when data is read from a storage device on the target board, data of another storage device is not output, so that a write check error occurs when performing a write check on the storage device. There is an excellent effect that it is possible to provide a write data inspection device that does not cause the problem.

According to the ninth and tenth aspects of the present invention, when data is written to the storage device on the target board and the read data is read, the data of another storage device is not output. There is an excellent effect that it is possible to provide a data writing device in which a writing check error does not occur when reading data and performing a writing check.

In particular, according to the tenth aspect of the present invention, there is provided an RO having a ROM socket which has conventionally been generally used.
It is possible to apply an M writer, and there is an excellent effect that existing equipment can be used.

According to the eleventh aspect of the present invention, data can be written to and read from the storage device on the target board without being limited by the shape or structure of the interface section provided on the target board. ,
Since the data of another storage device is not output when reading the write data, it is possible to provide a connector that does not cause a write check error when reading the write data and performing a write check. Has an effect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a data writing device according to a first embodiment.

FIG. 2 is an exemplary perspective view showing the data writing device with a PCB attached;

FIG. 3 is a block diagram showing a schematic configuration of the PCB.

FIG. 4 is a block diagram showing a schematic configuration of a part of a conversion board of the data writing device.

FIGS. 5A and 5B are schematic configuration diagrams showing an example of a power supply voltage follow-up supply unit of the conversion board. FIGS.

FIG. 6 is a block diagram showing a schematic configuration of a part of a ROM writer of the data writing device.

FIG. 7 is a flowchart showing the operation of the ROM writer.

FIG. 8 is a block diagram showing a schematic configuration of a part of a conversion board of the data writing device according to the second embodiment.

FIG. 9 is a block diagram showing a schematic configuration of a part of a ROM writer of the data writing device.

FIG. 10 is a block diagram showing a schematic configuration of a part of a conversion board of a data writing device according to a third embodiment.

[Explanation of symbols]

 1 Data Writer 2, 102, 202 Conversion Board 3, 103 ROM Writer 10 PCB 11 CPU 12 Flash ROM 13 Data Write Connector 14 SRAM 15 ROM 21 Connector 22 ROM Writer Connector 24, 124 Buffer 31 ROM Socket 33 Control unit 34 Memory 35 Chip enable signal generation circuit 135 Chip enable / disable signal generation circuit

Claims (11)

[Claims] 1. A storage device comprising an electrically rewritable IC, another storage device comprising an IC connected in parallel with the storage device by a data bus extending from a bus master, and the storage device and the other storage device An interface unit for externally controlling the device; and a printed circuit board having the data bus connected to the interface unit for reading data of the storage device from the outside. A read operation signal line for transmitting a read operation signal for making the data of the storage device readable from the outside, and a connection between the interface unit and the other storage device; A read operation disable signal line for transmitting a read operation disable signal for externally making data in another storage device unreadable. Printed circuit board and said. 2. The printed circuit board according to claim 1, wherein said read operation signal line is a transmission line branched from a chip select signal line connecting between said bus master and said storage device. . 3. The printed circuit board according to claim 1, wherein
A printed circuit board, wherein the read operation disable signal line is a transmission line branched from a chip select signal line connecting between the bus master and the other storage device. 4. A storage device comprising an electrically rewritable IC, another storage device comprising an IC connected in parallel to the storage device by a data bus extending from a bus master, and the storage device and the other storage device A data reading method for reading data stored in the storage device on a target board provided with an interface unit for externally controlling the device by using the data bus connected to the interface unit; A method for reading data from a storage device, wherein the storage device is set to a readable state and the other storage device is set to a non-readable state. 5. The data reading method according to claim 4, wherein the target board is the printed circuit board according to claim 1, 2 or 3, and reads data stored in the storage device on the printed circuit board. A data reading method, comprising: transmitting the read operation signal via the read operation signal line; and transmitting the read operation disable signal to the other storage device via the read operation disable signal line. 6. A storage device comprising an electrically rewritable IC, another storage device comprising an IC connected in parallel to the storage device by a data bus extending from a bus master, and the storage device and the other storage device A data reading device for reading data stored in the storage device on a target board provided with an interface unit for externally controlling the device using the data bus connected to the interface unit; Read operation signal output means for outputting a read operation signal for making the data of the storage device readable from the outside, and a read operation impossible for making the data of the other storage device unreadable from the outside A data readout device for outputting a read operation disable signal output means for outputting a signal. 7. A storage device comprising an electrically rewritable IC, another storage device comprising an IC connected in parallel with the storage device by a data bus extending from a bus master, and the storage device and the other storage device Writing data written to the storage device on a target board having an interface unit for controlling the device from the outside using the data bus connected to the interface unit; 6. A write data inspection method for inspecting whether or not data has been correctly written, wherein the data read method according to claim 4 or 5 is used when reading the write data. 8. A storage device comprising an electrically rewritable IC, another storage device comprising an IC connected in parallel with the storage device by a data bus extending from a bus master, and the storage device and the other storage device Writing data written to the storage device on a target board having an interface unit for controlling the device from the outside using the data bus connected to the interface unit; 7. A write data inspection apparatus for inspecting whether data has been written correctly, comprising a data reading apparatus according to claim 6 and an inspection means for inspecting whether said write data has been written correctly. A write data inspection device, characterized in that: 9. A storage device comprising an electrically rewritable IC, another storage device comprising an IC connected in parallel with the storage device by a data bus extending from a bus master, and the storage device and the other storage device After writing write data to the storage device on the target board provided with an interface unit for controlling the device from the outside via connection means connectable to the interface unit, the storage device is connected to the interface unit. A data writing device for reading the write data using the data bus and checking whether or not the write data is correctly written; 9. A data writing device according to claim 8, wherein said data writing device is a write data inspection device. 10. The data writing device according to claim 9, wherein the writing and writing of the write data is performed using a ROM writer having a ROM socket. The connecting means connects the interface section of the target board and the ROM socket. A data writing device, which is a connection tool for connecting. 11. A storage device for electrically controlling a storage device comprising an IC which is electrically rewritable and another storage device comprising an IC connected in parallel with the storage device by a data bus extending from a bus master. 7. A connection tool for connecting an interface unit provided on a target board on which a device and another storage device are mounted and a data input / output unit of a data writing device having the function of a data reading device according to claim 6. A read operation signal line for transmitting a read operation signal output from the input / output unit to the storage device on the target board, and a read operation signal line for transmitting a read disable operation signal to the other storage device on the target board And a connector comprising: