JPH0470579A - Testing device for electronic circuit unit - Google Patents

Abstract

PURPOSE:To make possible efficiency-good test effectiveness without causing failure and the like of a circuit element even if it is applied to an electronic circuit unit in which a power source control is performed by connecting a connection socket to a socket. CONSTITUTION:The device 2 tests a printed board unit PU in which a circuit element MPU(MPU1-3) having a power source terminal is detachably incorporated by the use of a socket SC(SC1-3). And data or signals input and output into the element MPU are input and output into the device 2 while a power source necessary for the operation of the device 2 is supplied by connecting an MPU socket CC(CC1-3) of the device 2 to the socket SC. Accordingly the power source for the device 2 is supplied after the power source is supplied to a board PU. Thereby the failure of the element MPU is prevented.

Description

[Detailed Description of the Invention] [Summary] Regarding a test device for electronic circuit units such as printed circuit board units, especially printed circuit board units equipped with a plurality of micro processor units (MPUs), the power supply control wholesaler The purpose of this test is to provide a test equipment that can perform efficient tests on electronic circuit units that are currently being tested without causing damage to the circuit elements. A test device for a removably incorporated electronic circuit unit, which has a connection socket connectable to the socket, and by connecting the connection socket to the socket, the power necessary for operation of the test device is supplied. The connection socket is configured to be supplied via the connection socket.

(Industrial Application Field) The present invention relates to an electronic circuit unit such as a printed circuit board unit, especially a plurality of microprocessor units (MPU).
This invention relates to a test device for a printed circuit board unit equipped with a.

In recent years, printed circuit board units have become more dense and have lower power consumption, so MPUs and their peripheral circuits are increasingly becoming CMO3, and functional blocks that will not be operating for the time being are being Efforts have been made to ensure that the power supply is stopped. Furthermore, a plurality of MPUs are often mounted on one printed circuit board unit.

Under these circumstances, when conducting tests such as debugging, diagnosing, inspecting, or confirming the operation of printed circuit board units, conventional test equipment has encountered various inconveniences. It is hoped that new testing equipment will emerge.

[Conventional technology]

Logic analyzers have been widely used as devices for testing printed circuit board units.

However, in the logic analyzer, it is necessary to store all the test procedures of the test object by the MPU in a ROM or the like, so the test is troublesome.

Therefore, in order to support testing of printed circuit board units for more complex systems, insert emulators (ICEs) are often used that can also store test procedures and analyze test results.

In ICE, the MPU mounted on the printed circuit board unit
It is possible to emulate the logic as if it were operating in the circuit instead of the logic such as
Tests can also be performed on PU.

[Problem to be solved by the invention]

However, when an ICE is used to test a printed circuit board unit, current may leak from the ICE to the printed circuit board unit.

For example, if the ICE is connected to a printed circuit board unit while the power is on, current will flow from the ICE into the peripheral circuit of the printed circuit board unit, causing latch-up, which may destroy circuit elements or The performance of the device may be impaired or the life of the circuit device may be reduced.

Therefore, the ICE cannot be powered on until after power is supplied to the printed circuit board unit.

Generally, in an ICE, a test program for a printed circuit board unit to be tested is loaded from an external storage device, so the start-up time from when the power is turned on until the test can be started is extremely long.

Therefore, when testing using ICE, it takes a lot of time for one printed circuit board unit, and there is a problem that it is extremely inefficient for product inspection.

Additionally, during testing of a printed circuit board unit, power supply control may be performed to stop the supply of power to one or more of the multiple functional blocks built into the printed circuit board unit. be.

For example, in a test of a printer/M board unit that incorporates multiple MPUs with different control contents or control targets,
The same number of ICEs as the number of MPUs are connected, but if the power supply to one MPU is stopped during the test, current will leak from the ICE connected instead of that MPtJ to the surrounding circuit elements. However, this may cause destruction of circuit elements.

Conventional ICE cannot prevent this,
Therefore, it is not possible to test such printed circuit board units.

In addition, in conventional ICEs, the power cannot be turned on earlier than the power is supplied to the printed circuit board unit, so it is necessary to test circuits that operate only when the power is turned on, such as a reset signal generation circuit that generates a reset signal to the MPU. The problem was that it could not be done.

In view of the above-mentioned problem, the invention of claim 1 provides a test device that can efficiently test an electronic circuit unit 7) in which power supply control is performed without causing damage to circuit elements. is intended to provide.

It is an object of the invention as claimed in claim 2 to provide a test device that can also test a circuit that operates only when the power is turned on.

[Means to solve the problem]

In order to solve the above-mentioned problem, the test device 2 according to the invention of claim 1 includes an electronic circuit unit PC in which a circuit element MPU having a Wfi terminal is removably installed using a socket SC, as shown in FIG. The test device 2 has a connection socket CC connectable to the socket SC, and by connecting the connection socket CC to the socket SC, the power necessary for the operation of the test device 2 is supplied to the connection socket. It is configured to be supplied via CC.

The test apparatus 2 according to the invention of claim 2 is provided with a reset circuit 16 that outputs a reset signal Sl for resetting the test apparatus 2, and the reset circuit 16
The time constant of the electronic circuit unit PC which is the test object
This is set smaller than the time constant of the reset circuit.

[For production]

By connecting the CC (connection socket) to the socket SC, data or signals input/output from the circuit element MPU installed in the socket SC are input/output to the test apparatus 2, and data or signals necessary for the operation of the test apparatus 2 are input/output to/from the test apparatus 2. Power is supplied.

Therefore, power is supplied to the test apparatus 2 only when power is supplied to the electronic circuit unit PC.

Since the time constant of the reset circuit 16 is smaller than the time constant of the reset circuit of the electronic circuit unit PC, the test apparatus 2 is reset before the electronic circuit unit PC is reset.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing the configuration of a test system 1 using a test device 2 according to the present invention.

The test system 1 includes a test apparatus 2 (2a, 2b) for three printed circuit board units PC1 as test objects.

2C) and a host computer 3.

The printed circuit board unit PC has three MPUs (MPt
J! , MPU2. MPU3) are each soot S
It is removably mounted via C (SC1, SC2, 5C3). These MPU peripheral elements, other circuit elements, and a glue set circuit for outputting a reset signal to the MPU when power is supplied to the printed circuit board unit PC are mounted.

These three MPUs have power supply terminals for receiving the power necessary for their respective operations. Further, these three MPUs control main control, line control, drive system control, etc. when the printed circuit board unit PC is a controller of a facsimile machine, for example.

The printed circuit board unit PC is supplied with power from a power source for testing (not shown), and after the power is supplied, there is a time T2 determined according to the time constant of the reset circuit and the threshold (+!voltage). (See FIG. 4), a reset signal S2 is output from the reset circuit to the reset terminal of each MPU.

Further, the printed circuit board unit PC has a power down mode, and the power supply is controlled.

In other words, for MPU2.3, these MPU2,
When the functions No. 3 are in a standby state, the power supplied to them is cut off by a relay or the like according to a command from the MPU 1. Therefore, printed circuit board unit PC
Even during the test, the power to the MPUs 2 and 3 may be cut off.

In addition, in the printed circuit board Unison PC shown in Fig. 2, three MPUs are removed from sockets SC, and each socket SC has an MPtJ socket CC (CCI) for input of each test device 2 instead of MPU0. , C.C.
2, CC3) is inserted.

Each test device 2 is connected to various buses and signal lines in order to connect to the printed circuit board unit PC, and each MPU
MPU socket CG that can be plugged into the socket SC of
An input/output line 34 for inputting/outputting signals that cannot be exchanged with the MPU socket CC, and an input/output line 35 for exchanging data or signals with the host computer 3.
have.

The host computer 3 outputs commands to the three test devices 2, analyzes data obtained by the tests, and comprehensively manages the tests of the printed circuit board unit PC.

FIG. 1 is a block diagram of a test device 2 according to the present invention.

In addition to the above-mentioned MPU socket CC1 input/output line 34.35, the test equipment 2 also includes an MPU II that is equivalent to or higher than the MPLI of the printed circuit board unit PC, ROM 12, and RAM.
13, arbiter 14, controller 15 with reset circuit 16, clock generator 17, latch 18
, a logic circuit 19, and input/output couplers 20a and 20b for connecting input/output power lines 34 and 35.

The MPLI socket CC has a data bus 21, an address bus 22, an RW signal line 23, and a reset signal line 2.
4, a clock line 25, an interrupt line 26, a power supply line 27, and a ground line 28 are connected.

Through these buses and lines, data or signals that should be input/output from each MPU are input/output to the test equipment 2, and power supplied to the printed circuit board unit PC (D) is input/output from the test equipment 2. 2 is also supplied.

The test equipment 2 includes various other buses or lines 29 to 3.
3 is provided.

The MPUI II operates as a controller for controlling the test device 2. A program for operating the MPUI 1 is written in the ROM 12 as firmware.

The RAM 13 is used as a work area for MPLJII.

The arbiter 14 receives a control signal S from the controller 15.
3 serves as a bidirectional bus gate that connects and separates each bus and line.

The controller 15 outputs a reset signal s1 independent from the reset signal s2 of the printed circuit board unit PC to the reset terminal of the MPU II by the reset circuit 16, and also outputs the reset signal S2 based on the reset signal s2 from the printed circuit board unit PC. MPUII
It outputs a signal S4 for reading by MPtJll to the input port of MPtJll, and also outputs a control signal S3 for the arbiter 14.

The clock generator 17 synchronizes the internal clock signal of the test device 2 with an external clock signal from the printed circuit board unit PC, and outputs the internal clock signal to the printed circuit board unit PCζ.

The latch 18 once latches the interrupt signal S5 from the printed circuit board unit PC and outputs it to its input port as an interrupt status signal S6 to be read by the MPU II.

The logic circuit 19 converts data or signals between the MPU mounted on the printed circuit board unit PC and the MPU II mounted on the test device 2, and thereby converts the MPU mounted on the printed circuit board unit PC. data and signals are created.

The input/output boat 20a is for exchanging signals with the printed circuit board unit PC. When the printed circuit board unit PC is fixed for positioning, the input/output line 34 is connected to the input/output port through a bin or the like provided on the printed circuit board unit PC using a fixing jig.

The human output port 20b is used to send and receive signals to and from the host computer 3, receive commands from the host computer 3, synchronize with other test equipment 2, and manage the entire test system I. It is something. Note that the signal output to the host computer 3 via the input/output line 35 includes test data of the printed circuit board unit PC, classification code of the MPU, etc., and the host computer 3 issues a command corresponding to the classification code.

These input/output ports 20a, 20b are connected to the line 33 side and the input/output line 34.3 by a photo isolator or the like.
However, such photo-isolators or input/output ports 20a, 20b may be provided on the printed circuit board unit PC side or the host computer 3 side.

In any case, the test device 2 is electrically connected to the outside only through the connection socket CC, and all the power necessary for the operation of the test device 2 is supplied from the connection socket CC via the power line 27. receive.

FIG. 3 is a circuit diagram showing an example of the reset circuit 16, and FIG. 4 is a diagram showing the output timing of the reset signals Sl and S2.

The reset circuit 16 includes a resistor R1, a capacitor C1, a diode DI, a Schmitt element 5MTl, and an inverter VT.
It consists of I, etc.

When power ■ is supplied to the power line 27, the capacitor C
The voltage v2 across I changes and rises as shown in FIG. 4, and after a time T1 determined according to the time constants of the resistor R1 and capacitor CI and the threshold voltage Vs of the Schmitt element 5MTl, Outputs a reset signal S1.

The time constant of this reset circuit 16 is smaller than the time constant of the printed circuit board unit PC paste circuit, and
It is set in consideration of the time required for the UII to become operational, and therefore the reset signal Sl from the reset circuit 16 is output faster than the reset signal S2 of the printed circuit board unit PC. For example, time T2
is about 500 m5, time T1 is 150 to 200
It is said to be about m5.

Next, the operation of the test apparatus 2 configured as described above will be explained.

First, when power is supplied to the printed circuit board unit PC by a test start command from the host computer 3, the M
Power is also supplied to each test device 2 via the PU socket CC and power line 27.

The reset circuit 16 provided in the test device 2 resets the MPU 1 before resetting the printed circuit board unit PC.
1 is performed, thereby initializing the boat, etc., and outputting a status signal indicating that the test device 2 is in a standby state to the host computer 3 via the turnout line 35.

The host computer 3 determines whether each test device 2 is operating normally by monitoring the status signal from each test device 2.

After the test device 2 enters the standby state, it waits for the output of the seven-step signal S2 from the printed circuit board PC.

When the reset signal S2 is output, the corresponding signal S
4 is entered into the input port of MPUI 1 and read.

As a result, testing of the state before and after the timing at which the reset signal S2 is output from the printed circuit board unit PC,
That is, a test is performed when the printed circuit board unit PC is powered on.

After that, the host computer 3 runs the three test devices 2
While sending appropriate commands to the printed circuit board unit PC, various tests are performed according to a known test menu corresponding to the printed circuit board unit PC.

When the interrupt signal S5 is output during the test, it is latched by the launch 18, and the latched signal, the interrupt status signal S6, is read from the input port of the MPU 1l. This prevents the MPU 21 from being interrupted unexpectedly during the test.

After the MPU II reads the interrupt status signal S6, it performs interrupt processing at an appropriate timing and outputs an interrupt release signal to the printed circuit board unit PC from the input/output port.

Also, during the test, if the printed circuit board unit PC goes into power down mode and the supply of its to MPU2.3 is stopped, these sockets SC2 and S
The supply of power to the test devices 2b and 2c connected to C3 is also stopped.

Therefore, current will not flow backward from the test equipment E2b, 2c to the MPU 2.3 of the printed circuit board unit PC and its peripheral circuits, and there is a risk that the circuit elements will be destroyed or the performance or lifespan will be reduced due to latch-up. There isn't.

Therefore, even if the printed circuit board unit PC1 has a plurality of MPUs or the printed circuit board unit PC has a power down mode, the test can be performed with confidence.

In addition, it is possible to start testing the printed circuit board unit PC while the power of the host computer 3 is turned on, so the test can be started immediately after positioning the printed circuit board unit PC and connecting the connection socket CC. The test time required is short and the efficiency is extremely high.

In addition, latch-up does not occur in the printed circuit board unit PC, and the test operation of the test device 2 can be started even before the printed circuit board unit PC is connected. Tests can be conducted at the time of application.

By performing multi-task processing, the host computer 3 can run tests on three test devices 2 in parallel, increasing the number of test steps per unit time, thereby reducing test time. It is possible to shorten the time.

In the above embodiment, if the MPU 11 is the same as the MPU of the printed circuit board unit PC, the logic circuit 19 in FIG. 1 can be omitted and the buses connected to the left and right sides thereof can be directly connected.

In this case, it is necessary to write in the ROM 12 a program compatible with the MPU of the printed circuit board unit PC.

In the above-described embodiments, the configuration, structure, shape, connection, format, number, circuit, wiring method, etc. of the reset circuit 1G or the test bag [2 and its parts can be modified in various ways other than those described above.

Further, the present invention can also be applied to the printed circuit board unit PC1 and other electronic circuit units in which circuit elements other than the MPU are incorporated.

〔Effect of the invention〕

According to the first aspect of the invention, it is possible to efficiently test an electronic circuit unit whose power supply is controlled without causing damage to the circuit elements.

According to the second aspect of the invention, it is also possible to test a circuit that operates only when the power is turned on.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a test device according to the present invention, FIG. 2 is a diagram showing the configuration of a test system using the test device according to the present invention, FIG. 3 is a circuit diagram showing an example of a beam setting circuit, and FIG. The figure is a diagram showing the output timing of the reset signal. In the figure, ■ is a test system, 2 is a test device, 16 is a reset circuit, PC is a printed circuit board unit (electronic circuit unit), MPU microprocessor unit (circuit base SC is a socket, CC is an MPU socket) (connection socket), Sl is a reset signal.Test system Figure 1 shows the configuration of a test system using the test device according to the present invention.

Claims (2)

[Claims] (1) A test device (2) for an electronic circuit unit (PC) in which a circuit element (MPU) having a power supply terminal is removably installed through a socket (SC), and is connectable to the socket (SC). Connection socket (CC
), and by connecting the connection socket (CC) to the socket (SC), the power necessary for the operation of the test device (2) is supplied via the connection socket (CC). 1. A testing device for an electronic circuit unit, characterized in that it is configured as follows. (2) A reset circuit (16) is provided that outputs a reset signal (S1) for resetting the test apparatus (2), and the time constant of the reset circuit (16) is the same as that of the device under test. 2. The electronic circuit unit testing apparatus according to claim 1, wherein the time constant is set smaller than a time constant of a reset circuit of the electronic circuit unit (PC).