201135450 .六、發明說明： 【發明所屬之技術領域】 本發明有關於一種電源測試系統，特別是有關於一種 針對伺服器之電源測試系統及方法。 【先前技術】 傳統對伺服器於開機過程中進行電源測試時，需等待 基本輸出輸入系統（Basic Input/Output System，BIOS ) — φ 一地對周邊硬體進行加電後自我檢查（Power-On Self Test ’ POST)程序，以便檢測其周邊硬體是否存在以及這 些周邊硬體是否可正常工作後，才能進行下一階段之電源 測試，以便測試伺服器之多種電源工作是否可正常進行^ 然而，由於測試者必須等待p〇ST程序完成後，才二 以進行後續之電源測試，使得伺服器所花費之開機時間7 嫌冗長，而且若在大量測試伺服器的前提下，此測試= 將拉長整體之測試時間。 有鑑於此，如何提出一種解決方案，可有效改善上、, 所帶來的缺失及不便，實乃相關業者目前刻不容緩:〜逑 要課題。 〜重 【發明内容】 本發明-方面揭露-種飼服器電源測試系統及對 器進行電源測試之方法，以縮短伺服器所花費之開艮 間，進而加速後續之電源壓力測試流程。 時 此種伺服器電源測試系統 包括一201135450. VI. Description of the Invention: [Technical Field] The present invention relates to a power supply test system, and more particularly to a power supply test system and method for a server. [Prior Art] Traditionally, when the server is performing power test during the boot process, it is necessary to wait for the Basic Input/Output System (BIOS) — φ to self-check the surrounding hardware after power-on (Power-On). The Self Test ' POST) program, in order to check the presence or absence of the surrounding hardware and whether these peripheral hardware can work properly, can carry out the next phase of the power test to test whether the various power supplies of the server can work normally. Since the tester must wait for the p〇ST program to complete before performing the subsequent power test, the boot time spent by the server is too long, and if a large number of test servers are used, this test = will be lengthened. Overall test time. In view of this, how to propose a solution that can effectively improve the shortcomings and inconveniences caused by the above is actually a matter of urgency: ～重重 [Summary] The invention discloses a method for power supply testing of a feeding device and a method for testing a power supply of the device, so as to shorten the opening time of the server and accelerate the subsequent power stress testing process. Such a server power test system includes one
201135450 板。主機板具有一 BIOS單元及一連接器，BI〇s單元具有 多個周邊硬體之註冊資料，連接器至少具有一電性連接 BIOS單元之控制腳位。偵錯板藉由連接器電性連接主機 板，用以改變連接器之控制腳位之電位狀態。當主機板進 行一 BIOS開機程序時，BIOS單元藉由已改變之控制腳位 之電位狀態，而不讀取周邊硬體的註冊資料，以跳過一加 電後自我檢查程序後，以供偵錯板對該伺服器 壓力測試流程。 電源 另外，主機板更設有一開機管理晶片，開機管理曰 用以依據-電源供電順序，提供不同電壓電源、定: 該主機板之多個系統狀態資訊，以及檢查該些系統二 訊是否有誤。 ’、’〜、貝 另外，開機管理晶片電性連接該偵錯板，以供資訊互 通。 另外，祠服器電源測試系統更包含一電腦 家系統模組。電腦裝置電性連接賴板。專 於電腦裝置中，藉由電職置電性連接偵錯板， 錯板所回傳m可解讀資訊，提供電源壓力之结 果。 、〇 本發明之另-態樣中，此種對词服器進行電 方法兹適㈣，服器之—域板與一偵錯板上" 服器藉由-連接器紐連接此偵錯板。此 主機板進行一 BIOS開機鋥床站I栝步驟為 n Bios 、偵·a板偵測到主機板已進 订BIOS開機釭序後，便改變連接器之一 狀態、根據控制腳位已改變之蝥你社能 +仙 之電位 I之電位狀態，主機板跳過一加 201135450 電後自我檢查程序，以及偵錯板對主機板進行多種電源壓 力測試。 另外’每當主機板進行BIOS開機程序時，連接器之 控制腳位之電位狀態回到一高電位狀態之預設狀態。 另外’當偵錯板操作控制腳位之電位狀態由—高電位 狀態改變成一低電位狀態。 另外’主機板根據控制腳位已改變之電位狀態，而不 去讀取一選擇暫存記憶體中之周邊硬體的註冊資料。 如此，本發明伺服器電源測試系統及對伺服器進行電 源測試之方法可提供縮短伺服器所花費之開機時間，進而 加速後續之電源壓力測試流程，以降低檢測時間及人事成 本0 【實施方式】 以下將以圖不及詳細說明清楚說明本發明之精神，如 熟悉此技術之人員在瞭解本發明之實施例後，當可由本發 •明所教不之技術’加以改變及修飾’其並不脫離本發明之 精神與範圍。 本發明係揭露-種伺服器電源測試系統。此祠服器電 源測試系統包括一伺服器及一偵錯板。本發明之偵錯板於 飼服器開機時’指示伺服器跳過一加電後自我檢查（p〇ST) 程序’以縮短飼服器所花費之開機時間，進而加速後續之 電源壓力測试流程。 如第1圖所不’第1圖繪示本發明伺服器電源測試系 統100於一實施例下之方塊圖。 201135450 此伺服器電源測試系統100之伺服器200包含一主機 板300、一基本輸出輸入系統（後簡稱bios )單元4〇〇 (例 如為裝有BIOS開機程序之記憶體）及一第一連接器5〇〇。 BIOS單元400位於主機板300上，具有一選擇暫存記憶體 410 (option Rom)，選擇暫存記憶體410中存放有多個周 邊硬體之註冊資料420(例如裝置ID、廠商ID等）。第一連 接器500位於主機板300上，具有多個腳位510，其中之 一稱控制腳位 510a(disableJBIOS—0PT_R0M_N)，此控制 φ 腳位5被定義用以電性連接Bi〇s單元400。 偵錯板700可拆卸地連接伺服器2〇〇，係具有一第二 連接器710。第二連接器710電性連接第一連接器5〇〇，藉 由第一連接器500電性連接主機板3〇〇，可改變控制腳位 510a之電位狀態（high/low)。 一般而言，當主機板被開機至完成系統開機，其間經 歷一未開機狀態、一 BIOS開機狀態、一 P0ST檢查狀態以 及一元件驅動狀態。「未開機狀態」是指主機板已被提供一 φ 待機電源（例如其插頭已插入市電之插座），但尚未按下啟 動開關，而未進行開機程序之狀態、「開機狀態」是指主機 板已被按下啟動開關，正在進行開機程序之狀態、「p〇ST 檢查狀態」是指主機板已進入p〇ST檢查程序，以及「元 件驅動狀態」是指主機板已完成p〇ST檢查程序，並陸續 啟動主機板所偵測到之元件（例如：硬碟、界面卡等），並 稱完成系統開機。 然而，本發明中，當該主機板3〇〇進行一 BI〇s開機 程序，而從未開機狀態進入BI〇s開機狀態時，由於偵錯 6 201135450 板700偵測到該主機板300進行BIOS開機程序後，便改 變控制腳位510a之電位狀態；BIOS單元400藉由該控制 腳位510a之電位狀態變化，而不讀取選擇暫存記憶體41〇 中之周邊硬體的註冊資料420,以不去進入一 POST檢查狀 態以及一元件驅動狀態（總稱POST程序），以便對主機板 300進行後續之電源壓力測試。 此外，主機板300上更設有一開機管理晶片600 (例 如’輸入/輸出控制晶片，I/O controller，或複雜可編程邏 • 輯器元件，CPLD，complex programmable logic device)。 開機管理晶片600的主要為（1 )依據一電源供電順序，管 理不同電壓電源（例如1.8伏、5伏、3.3伏、24伏、48伏 等電壓值）之啟動時機、（2)於各狀態下，定期收集主機 板300之多個系統狀態資訊，以及（3)檢查此些系統狀態 資訊及此些啟動事件是否有誤，並於檢查有誤時，產生一 錯誤訊息並存於一暫存區610中，以提供偵錯板700前來 讀取’其中錯誤訊息，例如為一 16進制碼之資料，為人工 φ 無法辨識之資料。如此，偵錯板700便可指示主機板3〇〇 進行多種電壓環境下之電源壓力測試。 當進行電源壓力測試時，第二連接單元插設於第一連 接單元時’偵錯板700與開機管理晶片600形成電性連接， 以供資訊互通。具體而言，偵錯板700自開機管理晶片6〇〇 之暫存區610中讀取上述之錯誤訊息，並經第二連接單元 傳回偵錯板700。偵錯板700可對錯誤訊息進行解讀，將 錯誤訊息轉換為一人工可解讀資訊，以供人員閱讀。此實 施例中，開機管理晶片600可於產生錯誤訊息時，通知偵 201135450 錯板700目前發現錯誤’並通知偵錯板7〇〇前來暫存區61〇 讀取錯誤訊息。 此外，復見第1圖所示，此伺服器電源測試系統100 更包括一專家系統模組810，專家系統模組81〇通常設於 一電腦裝置800 (NB或PC)中，電腦裝置800之一第三 連接單元820 (例如USB規格）活動地連接偵錯板7〇〇之 第四連接單元720。當第二連接單元820插設於第四連 接單元720時，偵錯板700與專家系統模組81〇形成電性 • 連接，以供資訊互通，且電腦裝置800提供偵錯板700之 工作電源。此外，彳貞錯板700將人工可解讀資訊經第三連 接單元820傳至專家系統模組810’經專家系統模組810 依據此人工可解讀資訊，提供電源壓力測試之結果。 如第1圖及第2圖所示’第2圖繪示本發明對飼服器 2〇〇進行電源測試之方法於此實施例下之流程圖。 當主機板300與偵錯板700電性連接時，兩者依據下 列步驟進行： • 步驟（201)主機板300進行一 BIOS開機程序： 此步驟中’當此主機板300已被按下啟動開關後，此 主機板300便啟動BIOS單元400，以使BIOS單元400進 行一 BIOS開機程序而進入開機程序之狀態，其間，開機 官理晶片600提供一種電壓（例如3.3伏）至第一連接器 50〇 °此外’每當主機板300進行此BIOS開機程序時，控 制腳位510a之電位狀態均會視為回到一預設狀態「高 (high)電位狀態」。 步驟（202)偵錯板700於偵測到主機板300已進行此 201135450 - BI0S開機程序，便改變控制腳位510a之電位狀態： - 當彳貞錯板藉由第一連接器500而偵測開機管理晶 片600所提供之電壓時，偵錯板7〇〇便操作控制腳位51〇& 之電位狀態由「高（high)電位狀態」改變成「低（1〇w) 電位狀態」。具體而言，偵錯板700發出高電位狀態之信號 至控制腳位510a ’使得BIOS單元400得知控制腳位5°1〇a 處於一「低（low )電位狀態」。 步驟（203) BIOS單元400跳過POST程序： • 由於BIOS單元400偵測控制腳位510a之電位狀態為 「低（low)電位狀態」，BIOS單元400便被指示不去讀取 選擇暫存記憶體410中之周邊硬體的註冊資料42〇，無法 進行POST程序，進而無法開啟周邊硬體的功能^故，開 機時間可由2分鐘降為約15秒。接著，BIOS單元4〇〇直 接進入電源壓力測試程序。 然而’設計者亦可更改設定，使得BIOS單元4〇〇得 知控制腳位510a處於一「高（high )電位狀態」後，不去 _ 讀取選擇暫存記憶體410中之周邊硬體的註冊資料42〇。 步驟（204)偵錯板700對主機板300進行多種不同電 壓環境下之電源壓力測試，以確認主機板300是否符合不 同電源壓力測試之規格要求： 偵錯板700透過第一連接單元要求開機管理晶片6〇〇 依序提供多種電壓電源（例如1.8伏、5伏、3.3伏、24伏、 48伏等電壓值）其中之一 ’經由開機管理晶片6〇〇之回報， 以確認主機板300是否可符合不同電源壓力測試之規格要 求。 201135450 - 當檢查有誤時，開機管理晶片000便發出失敗訊號， • 以通知偵錯板700 一「可讀取錯誤訊息」之訊息，如此， 偵錯板700便可透過第一連接單元中控制腳位51〇a外之其 他數個腳位510將錯誤訊息傳回偵錯板7⑽，偵錯板7〇〇 並回傳人工可解讀資訊至電腦裝置800。 需說明的是，本發明伺服器電源測試系統之伺服器2〇〇 仍可於進行電源壓力測試完成後，通知BI0S單元400進 行POST程序。 φ 綜上所述，本發明縮短伺服器所花費之開機時間，進 而加速後續之電源壓力測試流程’以降低檢測時間及人事 成本。 本發明所揭露如上之各實施例中，並非用以限定本發 明，任何熟習此技藝者’在不脫離本發明之精神和範圍内， 當可作各種之更動與潤飾’因此本發明之保護範圍當視後 附之申請專利範圍所界定者為準。 φ 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂’所附圖式之詳細說明如下： 第1圖繪示本發明伺服器電源測試系統於一實施例下 之方塊圖。 第2圖繪示本發明對伺服器進行電源測試之方法於此 實施例下之流程圖。 【主要元件符號說明】 201135450 100:伺服器電源測試系統 600 開機管理晶片 200 :伺服器 610 暫存區 300 :主機板 700 偵錯板 400 : BIOS 單元 710 第二連接器 410 :選擇暫存記憶體 720 第四連接單元 420 :註冊資料 800 電腦裝置 500 :第一連接器 810 專家系統模組 510 :腳位 820 第三連接單元 510a :控制腳位 201- 204 :步驟201135450 board. The motherboard has a BIOS unit and a connector. The BI〇s unit has a plurality of registration data of peripheral hardware, and the connector has at least one control pin electrically connected to the BIOS unit. The debug board is electrically connected to the host board through a connector to change the potential state of the control pin of the connector. When the motherboard performs a BIOS boot process, the BIOS unit does not read the registration data of the peripheral hardware by changing the potential state of the control pin, so as to skip the self-checking procedure after power-on, for detection. The wrong board tests the pressure of the server. In addition, the motherboard is further provided with a boot management chip, and the boot management is used to provide different voltage power according to the power supply sequence, determine: multiple system status information of the motherboard, and check whether the two systems are incorrect. . ‘,’~, 贝 In addition, the boot management chip is electrically connected to the debug board for information communication. In addition, the server power test system further includes a computer system module. The computer device is electrically connected to the board. It is specially designed for computer devices. It is connected to the error detection board by electric power. The error board can be used to interpret the information and provide the result of power supply pressure. In the other aspect of the present invention, the electronic method is applied to the word processor (4), and the server-domain board and the error-detecting board are connected by the connector-link. board. This motherboard performs a BIOS booting trampoline station I step for n Bios, the detective a board detects that the motherboard has subscribed to the BIOS boot sequence, then changes the state of one of the connectors, according to the control pin has changed蝥 社 社 社 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙 仙In addition, whenever the motherboard performs the BIOS boot process, the potential state of the control pin of the connector returns to a preset state of a high potential state. In addition, the potential state of the control board is changed from a high-potential state to a low-potential state. In addition, the motherboard is not required to read the registration data of the peripheral hardware in the selected temporary memory according to the potential state in which the control pin has changed. In this way, the server power supply test system of the present invention and the method for performing power test on the server can provide a shortening of the boot time spent by the server, thereby accelerating the subsequent power stress test process, thereby reducing the detection time and personnel cost. [Embodiment] In the following, the spirit of the present invention will be clearly described in the following detailed description, and those skilled in the art, after having understood the embodiments of the present invention, may be modified and modified by the technique taught by the present invention. The spirit and scope of the present invention. The present invention discloses a server power supply test system. The server power test system includes a server and a debug board. The debug board of the present invention indicates that the server skips a self-check (p〇ST) program after power-on when the feeding device is turned on to shorten the booting time spent by the feeding device, thereby accelerating the subsequent power stress test. Process. 1 is a block diagram of a server power supply test system 100 of the present invention in an embodiment. 201135450 The server 200 of the server power test system 100 includes a motherboard 300, a basic output input system (hereinafter referred to as bios) unit 4 (for example, a memory with a BIOS boot program) and a first connector. 5〇〇. The BIOS unit 400 is located on the motherboard 300 and has a selection of a temporary storage memory 410 (option Rom) for selecting a registration data 420 (e.g., device ID, vendor ID, etc.) in which a plurality of peripheral hardware is stored in the temporary storage memory 410. The first connector 500 is located on the motherboard 300 and has a plurality of pins 510, one of which is called a control pin 510a (disableJBIOS_0PT_R0M_N). The control φ pin 5 is defined to electrically connect the Bi〇s unit 400. . The debug board 700 is detachably coupled to the server 2, and has a second connector 710. The second connector 710 is electrically connected to the first connector 5A. The first connector 500 is electrically connected to the motherboard 3A, and the potential state (high/low) of the control pin 510a can be changed. Generally, when the motherboard is powered on until the system is powered on, it experiences an unpowered state, a BIOS boot state, a P0ST check state, and a component drive state. "Unpowered state" means that the motherboard has been supplied with a φ standby power supply (for example, its plug has been plugged into the mains socket), but the startup switch has not been pressed, and the boot process is not in the state, and the "on state" refers to the motherboard. The start switch has been pressed, the status of the boot process is being performed, "p〇ST check status" means that the motherboard has entered the p〇ST check program, and "component drive status" means that the motherboard has completed the p〇ST check procedure. And gradually start the components detected by the motherboard (for example: hard disk, interface card, etc.), and said to complete the system boot. However, in the present invention, when the motherboard 3 performs a BI〇s booting process and enters the BI〇s boot state from the power-on state, the debugger 6 detects the motherboard 300 to perform the BIOS. After the booting process, the potential state of the control pin 510a is changed; the BIOS unit 400 does not read the registration data 420 of the peripheral hardware in the temporary storage memory 41 by the potential state change of the control pin 510a. Instead of entering a POST check state and a component drive state (collectively, the POST program), a subsequent power stress test is performed on the motherboard 300. In addition, the motherboard 300 is further provided with a boot management chip 600 (for example, an input/output control chip, an I/O controller, or a complex programmable logic device, CPLD). The boot management chip 600 is mainly (1) according to a power supply sequence, managing the start timing of different voltage power sources (for example, voltage values of 1.8 volts, 5 volts, 3.3 volts, 24 volts, and 48 volts), and (2) in each state. Collecting multiple system status information of the motherboard 300 periodically, and (3) checking the status information of the system and whether the startup events are incorrect, and when an error is detected, an error message is generated and stored in a temporary storage area. In 610, the error detection board 700 is provided to read 'the error message, for example, the data of a hexadecimal code, which is the data that cannot be recognized by the artificial φ. In this way, the debug board 700 can instruct the motherboard 3 to perform a power stress test under various voltage environments. When the power supply pressure test is performed, when the second connection unit is inserted into the first connection unit, the error detection board 700 is electrically connected to the power-on management chip 600 for information intercommunication. Specifically, the debug board 700 reads the error message from the temporary storage area 610 of the boot management chip 6 and transmits it to the debug board 700 via the second connection unit. The debug board 700 can interpret the error message and convert the error message into a manually interpretable information for the person to read. In this embodiment, the boot management chip 600 can notify the detection 201135450 that the error board 700 currently finds an error when the error message is generated and notifies the debug board 7 to come to the temporary storage area 61 to read the error message. In addition, as shown in FIG. 1 , the server power supply testing system 100 further includes an expert system module 810. The expert system module 81 is usually disposed in a computer device 800 (NB or PC), and the computer device 800 A third connection unit 820 (for example, a USB specification) movably connects the fourth connection unit 720 of the debug board 7A. When the second connecting unit 820 is inserted into the fourth connecting unit 720, the debugging board 700 forms an electrical connection with the expert system module 81 for information intercommunication, and the computer device 800 provides the working power of the debugging board 700. . In addition, the error reading board 700 transmits the manually interpretable information to the expert system module 810 via the third connection unit 820 via the expert system module 810 to provide the result of the power stress test based on the artificially interpretable information. As shown in Fig. 1 and Fig. 2, Fig. 2 is a flow chart showing the method of power supply testing of the feeding device according to the present invention. When the motherboard 300 is electrically connected to the debug board 700, the two steps are performed according to the following steps: • Step (201) The motherboard 300 performs a BIOS boot process: In this step, 'When the motherboard 300 has been pressed, the start switch is turned on. Afterwards, the motherboard 300 activates the BIOS unit 400 to cause the BIOS unit 400 to perform a BIOS boot process and enter a boot process state. During this time, the boot wafer 600 provides a voltage (eg, 3.3 volts) to the first connector 50. In addition, 'when the motherboard 300 performs this BIOS boot process, the potential state of the control pin 510a is regarded as returning to a preset state "high potential state". Step (202) The debug board 700 changes the potential state of the control pin 510a after detecting that the motherboard 300 has performed the 201135450-BI0S boot process: - detecting the error board by the first connector 500 When the voltage supplied from the memory management chip 600 is turned on, the potential state of the debug board 7 操作 operation control pin 51 〇 & is changed from "high potential state" to "low (1 〇 w) potential state". Specifically, the debug board 700 signals a high potential state to the control pin 510a' so that the BIOS unit 400 knows that the control pin 5°1〇a is in a "low" state. Step (203) The BIOS unit 400 skips the POST program: • Since the BIOS unit 400 detects that the potential state of the control pin 510a is "low" state, the BIOS unit 400 is instructed not to read the selected temporary memory. The registration data of the peripheral hardware in the body 410 is 42〇, the POST program cannot be performed, and the function of the peripheral hardware cannot be turned on, and the boot time can be reduced from 2 minutes to about 15 seconds. Next, the BIOS unit 4 is directly connected to the power supply stress test procedure. However, the designer can also change the settings so that the BIOS unit 4 knows that the control pin 510a is in a "high" state, and does not read the peripheral hardware in the temporary memory 410. Registration information 42〇. Step (204) The debug board 700 performs a power stress test on the motherboard 300 in a plurality of different voltage environments to confirm whether the motherboard 300 meets the specifications of different power stress tests: the debug board 700 requires power-on management through the first connection unit. The chip 6 is sequentially provided with a plurality of voltage power sources (for example, voltage values of 1.8 volts, 5 volts, 3.3 volts, 24 volts, and 48 volts), and one of the 'returns through the power management chip 6 to confirm whether the motherboard 300 is Can meet the specifications of different power stress tests. 201135450 - When the check is incorrect, the boot management chip 000 will send a failure signal, to notify the error detection board 700 of a "readable error message" message, so that the debug board 700 can be controlled through the first connection unit. The other plurality of pins 510 outside the pin 51〇a transmit an error message back to the debug board 7 (10), the debug board 7〇〇, and the manual interpretable information to the computer device 800. It should be noted that the server 2 of the server power supply test system of the present invention can still notify the BI0S unit 400 to perform the POST program after the power stress test is completed. φ In summary, the present invention shortens the boot time spent by the server, thereby accelerating the subsequent power stress test procedure to reduce detection time and personnel costs. The present invention is not limited to the embodiments of the present invention, and any skilled person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. This is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; A block diagram of an embodiment. Fig. 2 is a flow chart showing the method of power supply testing of the server according to the embodiment of the present invention. [Main component symbol description] 201135450 100: Server power supply test system 600 Boot management chip 200: Server 610 Storage area 300: Motherboard 700 Debug board 400: BIOS unit 710 Second connector 410: Select temporary memory 720 fourth connection unit 420: registration data 800 computer device 500: first connector 810 expert system module 510: pin 820 third connection unit 510a: control pin 201-204: steps