JP2001042006A - Semiconductor integrated circuit test apparatus and method of restoration from its failure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a decrease in availability due to a failure by shortening a warming up execution time after the failure is restored. SOLUTION: Temperature detection parts 17, 27 and 37 are installed in spare substrates 15, 25 and 35 for failure restoration. The spare substrates are preheated before mounting. When a substrate 13 fails, the spare substrate 15 is mounted in place of the failing substrate 13, and the failure is restored. A temperature of the mounted spare substrate 15 is detected by the temperature detecting part 17 during warming up after the failure is restored. The execution of the warming up is stopped based on the detected temperature of the spare substrate 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus for testing the electrical characteristics of a semiconductor integrated circuit and a method for restoring the same in the event of a failure. 1. Field of the Invention The present invention relates to a circuit test apparatus and a method for restoring the circuit test apparatus when it fails.

[0002]

2. Description of the Related Art Generally, a semiconductor integrated circuit (hereinafter, IC)
In the test apparatus, a predetermined power supply voltage and a test signal are supplied to the IC under test, and an output signal of the IC under test with respect to the supplied test signal is compared with a predetermined expected value, thereby obtaining a test target. A test of the electrical characteristics of the test IC (hereinafter referred to as an IC test) is performed.

In order to obtain the required test accuracy in such an IC test apparatus, a test signal must be supplied to the IC under test with high timing accuracy and high amplitude accuracy. Furthermore, the power supply voltage supplied to the IC under test also requires high accuracy. And their accuracy is I
It is strongly affected by the temperature characteristics of electronic components such as integrated circuit elements that constitute the C test apparatus.

[0004] Therefore, usually, warm-up is performed immediately after the IC test apparatus is started (ie, the main power of the IC test apparatus is turned on). After the electronic components have been thermally stabilized sufficiently by this warm-up, the necessary test accuracy is ensured by performing automatic calibration (so-called system calibration) of the test signal and the power supply voltage supplied to the IC under test. I have.

[0005] In the conventional IC test apparatus, the execution time of the warm-up is set in advance, and the warm-up is always performed for a fixed time. The warm-up execution time is
Usually, it is set to about 30 minutes so that all the electronic components constituting the IC test apparatus are thermally stable.

FIG. 6 is a flowchart showing the operation of the conventional IC test apparatus from startup to execution of an IC test. A conventional IC test apparatus operates as follows.

First, the main power of the IC test apparatus is manually turned on, and the IC test apparatus is started (step S10).
1).

Immediately after startup, execution of warm-up is started (step S102).

The execution of the warm-up is continued until a predetermined time has elapsed (step S103), and when the predetermined time has elapsed, the execution of the warm-up is stopped (step S104).

Further, after performing system calibration (step S105), an IC test is performed (step S106).

[0011]

In recent years, the cost of manufacturing an IC test apparatus has been increasing with the increase in functions and speed of the IC test apparatus, and it has been desired to improve the operation rate of the IC test apparatus. I have.

Generally, when a failure occurs in an IC test apparatus, an IC
Turn off the main power supply of the test equipment, temporarily stop, and repair the faulty part. Since the repair is performed by replacing the failed circuit for each board, the time required for the repair is about several minutes. When the repair is completed, the power is turned on again, warm-up and system calibration are performed in that order, and then I
The C test is restarted. Thus, the IC test apparatus is restored.

Originally, the execution time of the warm-up required after the repair of the failure increases or decreases in accordance with the time required for the repair (ie, the stop time of the IC test apparatus). Execution time can be reduced. However, in the conventional IC test apparatus, even after the failure is repaired, the warm-up for a certain time is executed according to the flowchart of FIG. For this reason, unnecessary time is spent for warm-up, and the time required for recovery from a failure cannot be reduced. Therefore, there is a problem that the operation rate is greatly reduced due to the failure.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit test apparatus capable of shortening the execution time of warm-up after repairing a failure, and a method of restoring the semiconductor integrated circuit when the failure occurs.

Another object of the present invention is to provide a semiconductor integrated circuit test apparatus capable of suppressing a decrease in the operation rate due to a failure, and a method for restoring the same upon failure.

[0016]

(1) A semiconductor integrated circuit test apparatus according to the present invention is a semiconductor integrated circuit test apparatus in which warm-up is performed at the time of start-up to stabilize the operation, and a failure-producing substrate is provided when a failure occurs. A spare board that can be mounted instead, and a temperature detection unit that detects the temperature of the spare board when the spare board is mounted, the spare board is pre-heated before mounting, and When the failure is repaired by mounting the spare board, the warm-up executed by restart is stopped based on the detected temperature of the spare board.

(2) In the semiconductor integrated circuit test device of the present invention, the temperature detecting means detects a temperature of the spare board mounted for repairing the failure. Then, based on the detected temperature of the spare substrate, the warm-up executed after the repair of the failure is stopped. Moreover,
The preliminary board is preheated (ie, preheated) before mounting.

Therefore, the execution of the warm-up can be stopped immediately after the operation is stabilized, and unnecessary time is not spent for the warm-up. Furthermore, the time required for stabilizing the operation is reduced by the preheating of the preliminary substrate. Therefore, the execution time of the warm-up after the repair of the failure can be reduced, and the reduction in the operation rate due to the failure can be suppressed.

Preferably, the temperature detection means is provided on the spare substrate so that the temperature of the spare substrate can be directly detected.

(3) Japanese Unexamined Patent Application Publication No. 9-61503 discloses a semiconductor test apparatus in which a temperature change detecting means detects an internal temperature of the apparatus. However, Japanese Patent Application Laid-Open
In the semiconductor test apparatus disclosed in Japanese Patent No. 61503, the detection of the temperature in the apparatus by the temperature change detecting means is performed for the purpose of suppressing the skew error by adjusting the delay time of the test signal according to the temperature change in the apparatus. Things.

On the other hand, Japanese Patent Laying-Open No. 10-170603 discloses a method of calibrating an IC tester in which an ambient temperature in the IC tester is detected by a temperature detecting means. However, Japanese Patent Application Laid-Open No. 10-170603 discloses I
In the calibration method of the C tester, the detection of the ambient temperature in the IC tester by the temperature detection means is for determining whether or not to perform the calibration, and is performed for the purpose of shortening the calibration time. is there.

Further, Japanese Patent Application Laid-Open Nos. 63-163290 and 4-190175 also disclose an IC inspection apparatus having a temperature sensor. However, even in the IC inspection apparatuses disclosed in these publications, the temperature detection by the temperature sensor is intended to improve the skew accuracy by adjusting the timing of the test signal.

Therefore, the purpose of the present invention is to stop the warm-up based on the detected temperature of the spare substrate, thereby shortening the execution time of the warm-up after the repair of the failure and suppressing the decrease in the operation rate caused by the failure. Of the present invention and the above-mentioned JP-A-9-61503 and JP-A-10-170
603, JP-A-63-163290 and JP-A-4-190175 are clearly different.

(4) In a preferred example of the semiconductor integrated circuit testing apparatus of the present invention, the spare substrate is provided with a plurality of the temperature detecting means, and the temperature detected by each of the plurality of the temperature detecting means is determined. Let the minimum value be the temperature of the spare substrate. In this case, even if a temperature distribution occurs in the spare substrate, there is an advantage that the temperature distribution is less likely to be affected.

In another preferred embodiment of the semiconductor integrated circuit testing apparatus according to the present invention, the temperature detecting means is provided in close contact with a ground wiring region of the spare substrate. In this case, since the ground wiring region has a relatively large specific heat, a rapid change in temperature is suppressed in the ground wiring region. In addition, by closely adhering to the ground wiring region, heat conduction to the temperature detecting means is promoted. Therefore, there is an advantage that the temperature of the spare substrate can be detected more accurately because the influence of disturbance is less.

In still another preferred embodiment of the semiconductor integrated circuit test apparatus according to the present invention, the temperature detecting means includes a plurality of phase inverters connected in cascade, an input signal to the first-stage phase inverter, and a final-stage A phase comparator for detecting a phase difference from an output signal of the phase comparator. The phase comparator outputs a signal corresponding to a temperature of the mounted spare board to the controller.

In still another preferred embodiment of the semiconductor integrated circuit test apparatus of the present invention, the apparatus further comprises a spare board holding means provided adjacent to a mounting position of the spare board, wherein the spare board before mounting is provided. The preliminary substrate is held by the preliminary substrate holding means, so that the preliminary substrate is heated in advance before mounting.

In still another preferred embodiment of the semiconductor integrated circuit testing apparatus according to the present invention, the semiconductor integrated circuit testing apparatus further includes a spare board storage means capable of heating the accommodated spare board before mounting.

(5) The method for restoring a failure of a semiconductor integrated circuit test apparatus according to the present invention is a method for restoring a failure of a semiconductor integrated circuit test apparatus in which a warm-up is performed for stabilizing operation at startup. Mounting a pre-heated spare board in place of the faulty board when a fault occurs, repairing the fault, repairing the fault, restarting and executing the warm-up, During execution, the method includes a step of detecting a temperature of the mounted spare board and a step of stopping the warm-up based on the detected temperature of the spare board.

(6) In the method for restoring a failure of a semiconductor integrated circuit test apparatus according to the present invention, a spare board which has been heated in advance is mounted in place of the failed board, and the failure is repaired. Warm-up is performed, and the warm-up is stopped based on the temperature of the spare substrate detected during the warm-up.

Therefore, for the same reason as described in the semiconductor integrated circuit test apparatus of the present invention, the execution time of the warm-up after the repair of the failure can be shortened, and the reduction of the operation rate caused by the failure can be suppressed.

(7) In a preferred example of the method for restoring a failure of the semiconductor integrated circuit test apparatus of the present invention, the temperatures of a plurality of parts of the spare board are detected, and the minimum values of the temperatures of the plurality of parts are determined by the spare board. Temperature. In this case, even if a temperature distribution occurs in the spare substrate, there is an advantage that the temperature distribution is less likely to be affected.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

FIG. 1 shows the configuration of an IC test apparatus according to one embodiment of the present invention.

As shown in FIG. 1, the IC test apparatus is
A CPU (Central Processing Unit) 1, a memory 2, a timing control unit 10, a device power supply unit 20, a pin electronics unit 30, and a failure repair spare board 15, 25, 35 are provided. I have.

The CPU 1 controls the entire IC test apparatus based on a predetermined control program.
It is electrically connected to the bus line 3. When the IC test apparatus fails, the CPU 1 executes a failure diagnosis program, which is a part of the control program, to specify a failure location.

The memory 2 stores a control program and predetermined data, and is electrically connected to the bus line 3.

The timing control section 10 has an interface 11 electrically connected to the bus line 3 and a plurality of substrates provided with a timing control circuit 16 and a temperature detection section 17, respectively. Actually, the IC under test
Although the number of substrates corresponds to the number of input / output pins (not shown), two substrates 13 and 14 are shown here to simplify the drawing. Hereinafter, the timing control unit 1
It is assumed that 0 has only the substrates 13 and 14.

The timing control circuit 16 for the substrates 13 and 14
Generates a timing signal such as a clock pulse and a determination strobe. The temperature detector 17 of the substrates 13 and 14 detects the temperature of the substrates 13 and 14.

The boards 13 and 14 are mounted on the timing control section 10 by being mounted on corresponding mounting sockets 18, respectively. The mounting sockets 18 are fixed to the frame 7, respectively, and the mounting sockets 18 are electrically connected to the bus lines 12, respectively. For this reason, the timing control circuit 16 and the temperature detection unit 17 of the substrates 13 and 14 are electrically connected to the interface 11 via the corresponding mounting sockets 18, respectively. The temperature detectors 17 of the substrates 13 and 14 output temperature data signals TD1 and TD2 based on the detected temperatures to the bus lines 12, respectively.

FIG. 2 shows the structure of the temperature detecting section 17 of the substrate 13.

The temperature detector 17 in FIG. 2 has two temperature sensors 41 a and 41 b provided on the substrate 13 and a temperature data generator 43. Temperature sensors 41a, 4
1b detects the temperature of a predetermined portion of the substrate 13 respectively,
Output signals TS1 and TS2 corresponding to the detected temperature are supplied to the temperature data generator 43, respectively. The temperature data generator 43 outputs the output signals TS of the temperature sensors 41a and 41b.
1. Generate a temperature data signal TD1 based on TS2,
Output to the bus line 12.

The temperature sensors 41a and 41b are connected to two ground planes (ie, two ground planes) formed on the surface of the substrate 13.
Ground wiring areas) 42a and 42b are provided in close contact with each other. The ground planes 42a and 42b are generally made of a copper material as a base, which is plated with gold or solder, and has a larger heat capacity than the substrate 13 made of an epoxy material or the like. For this reason, in the ground planes 42a and 42b, rapid heat fluctuation hardly occurs, and the temperature is stable. The temperature sensors 41a, 4b are attached to the ground planes 42a, 42b having these characteristics.
By adhering 1b, resistance to heat disturbance is increased, and stable output signals TS1 and TS2 can be obtained. That is, the temperature of the substrate 13 can be detected more accurately.

The temperature detecting section 17 shown in FIG. 2 has two temperature sensors 41a and 41b.
This is because consideration is given to the case where a temperature distribution occurs in No. 3.
That is, the lower one of the temperatures detected by the temperature sensors 41a and 41b may be set as the temperature of the substrate 13. Then, it is less likely to be affected by the temperature distribution. Depending on the degree of the temperature distribution, it is effective to provide more temperature sensors in addition to the temperature sensors 41a and 41b.

Conversely, only one of the temperature sensors 41a and 41b may be provided. In that case, the temperature range of the determination condition of the warm-up stop described later is set high. Then, it is less likely to be affected by the temperature distribution.

FIG. 3 shows a specific example of the temperature sensor 41a.

The temperature sensor 41a shown in FIG. 3 comprises seven cascaded phase inverters (inverters) 61a, 61b, 6
It comprises an IC having 1c, 61d, 61e, 61f, 61g and a phase comparator 62.

The reference signal B is supplied to the first-stage phase inverter 61a.
S is input, and a signal obtained by inverting the phase of the reference signal BS is output from the phase inverter 61a. As the reference signal BS, for example, a clock pulse generated by the timing control circuit 16 is used.

The second to seventh stage phase inverters 61b, 61
c, 61d, 61e, 61f, and 61g have the first to sixth stages.
Stage phase inverters 61a, 61b, 61c, 61d, 61
e and 61f are input, and the signals obtained by inverting the phases of the output signals of the phase inverters 61a, 61b, 61c, 61d, 61e and 61f are phase inverters 61b and 61f.
c, 61d, 61e, 61f, and 61g. The output signal PS of the phase inverter 61g is supplied to one input terminal of the phase comparator 62.

A reference signal BS is supplied to the other input terminal of the phase comparator 62. The phase comparator 62 outputs a signal TS1 corresponding to the phase difference between the reference signal BS and the output signal PS of the phase inverter 61g.

The temperature sensor 41a having the above configuration is
Phase inverters 61a, 61b, 61c, 61d, 61e,
This is based on the fact that the phases of the output signals 61f and 61g change according to the operating temperature. That is, as the operating temperature increases, the output signal PS of the phase inverter 61g increases.
Becomes larger, and the output signal T of the phase comparator 62 becomes larger.
S1 also increases. Thus, a signal corresponding to the operating temperature (that is, the temperature of the substrate 13) is obtained.

The temperature sensor 41b has the same configuration as the above-mentioned temperature sensor 41a.

From here, the description returns to FIG.

The device power supply section 20 has an interface 21 electrically connected to the bus line 3 and a plurality of substrates provided with a device power supply circuit 26 and a temperature detection section 27, respectively. Actually, as in the case of the timing control unit 10, the number of substrates corresponds to the number of input / output pins of the IC under test. However, here, two substrates 23 and 24 are shown to simplify the drawing. ing. Hereinafter, a description will be given assuming that the device power supply unit 20 has only the substrates 23 and 24.

The device power supply circuit 26 of the substrates 23 and 24
Supplies a power supply voltage to the IC under test. The temperature detectors 27 of the substrates 23 and 24 detect the temperatures of the substrates 23 and 24 and have substantially the same configuration as the temperature detector 17.

The substrates 23 and 24 are mounted on the device power supply unit 20 by being mounted on corresponding mounting sockets 28, respectively. The mounting sockets 28 are fixed to the frame 8, respectively, and the mounting sockets 28 are electrically connected to the bus lines 22, respectively. Therefore, the device power supply circuit 26 and the temperature detection unit 27 of the substrates 23 and 24 are electrically connected to the interface 21 via the corresponding mounting sockets 28, respectively. The temperature detectors 27 of the substrates 23 and 24 output temperature data signals TD3 and TD4 based on the detected temperatures to the bus lines 22, respectively.

The pin electronics section 30 includes an interface 31 electrically connected to the bus line 3 and a plurality of substrates provided with the pin electronics circuit 36 and the temperature detection section 37, respectively. Actually, similarly to the timing control unit 10, the number of substrates corresponds to the number of input / output pins of the IC under test. However, here, two substrates 33 and 34 are illustrated in order to simplify the drawing. Is shown. Hereinafter, the pin electronics section 30 is
Description will be made assuming that only three and 34 are provided.

The pin electronics circuits 36 of the substrates 33 and 34 supply a test signal to the IC under test and compare the output signal from the IC under test with a predetermined expected value stored in the memory 2 in advance. It is. Substrates 33, 34
The temperature detecting section 37 detects the temperature of the substrates 33 and 34 and has substantially the same configuration as the temperature detecting section 17.

The boards 33 and 34 are mounted on the corresponding mounting sockets 38, respectively.
0 is implemented. The mounting socket 38 is the frame 9
The mounting socket 38 is electrically connected to the bus line 32. For this reason, the pin electronics circuit 36 and the temperature detecting section 37 of the boards 33 and 34 are electrically connected to the interface 31 via the corresponding mounting sockets 38, respectively. The temperature detectors 37 of the substrates 33 and 34 output temperature data signals TD5 and TD6 based on the detected temperatures to the bus lines 32, respectively.

An IC test is executed by the CPU 1, the memory 2, the timing control section 10, the device power supply section 20, and the pin electronics section 30.

The spare board 15 has the same timing control circuit 16 and temperature detecting section 17 as the boards 13 and 14, and is mounted on the dummy socket 19. The dummy socket 19 is fixed to the frame 7 like the mounting socket 18, but the dummy socket 19 is not electrically connected to the bus line 12. For this reason, the timing control circuit 16 and the temperature detection unit 17 of the spare board 15 are not electrically connected to the interface 11.

The spare board 25 has the same device power supply circuit 26 and temperature detecting section 27 as the boards 23 and 24, and is mounted on the dummy socket 29. dummy·
The socket 29 is the same as the mounting socket 28 for the frame 8.
However, the dummy socket 29 is not electrically connected to the bus line 22. Therefore, the device power supply circuit 26 and the temperature detection unit 27 of the spare board 25 are not electrically connected to the interface 21.

The spare board 35 has the same pin electronics circuit 36 and temperature detecting section 37 as the boards 33 and 34, and is mounted on the dummy socket 39.
The dummy socket 39 is fixed to the frame 9 similarly to the mounting socket 38, but the dummy socket 39 is not electrically connected to the bus line 32.
For this reason, the pin electronics circuit 3 of the spare board 35
6 and the temperature detector 37 are not electrically connected to the interface 31.

In the IC test apparatus shown in FIG.
Is removed from the mounting socket 18, and the spare board 15 is mounted on one of the mounting sockets 18, so that when a failure occurs in the timing control circuit 16, the board can be replaced in units of boards. Device power supply circuit 26
Similarly, the pin electronics circuit 36 can be replaced on a board basis.

FIG. 4 shows the substrates 13 and 14 and the spare substrate 1
5 shows a state of being mounted on the mounting socket 18 and the dummy socket 19.

As shown in FIG. 4, the mounting socket 18 and the dummy socket 19 are
4 and the substrate 15 are arranged adjacent to each other such that their respective surfaces face each other at a predetermined interval. For this reason, when the timing control circuit 16 of the boards 13 and 14 generates heat during operation, the spare board 15 is preheated (that is, preheated) by radiation or convection before mounting. When the preliminary heating is sufficiently performed, the temperature of the preliminary substrate 15 becomes substantially equal to that of the substrate 13 (for example, about 50 ° C.).

The state in which the boards 23 and 24 and the spare board 25 are mounted on the mounting socket 28 and the dummy socket 29 is the same as in the case of the boards 13 and 14 and the spare board 15. Further, the substrates 33 and 34 and the spare substrate 35
Is mounted on the mounting socket 38 and the dummy socket 39 in the same manner as in the case of the boards 13, 14 and the spare board 15. Therefore, during the operation of the device power supply circuit 26 of the substrates 23 and 24, the spare substrate 25
Preheating is performed until the temperature becomes substantially equal to that of 3, 24.
During the operation of the pin electronics circuit 36 on the substrates 33, 34, the preliminary substrate 35 is preheated to a temperature substantially equal to that of the substrates 33, 34.

Next, the operation of detecting the temperature by the temperature detectors 17, 27 and 37 and controlling the warm-up by the CPU 1 will be described with reference to FIGS.

When the IC test apparatus shown in FIG. 1 is started, power is supplied to the timing control unit 10, the device power supply unit 20, and the pin electronics unit 30, and the warm-up is started.

Immediately after the start of the warm-up, the temperature detectors 17 of the substrates 13 and 14 detect the temperatures of the substrates 13 and 14, respectively, and output the temperature data signals TD1 and TD2 to the bus line 12, respectively. Similarly, the substrate 23,
The 24 temperature detectors 27 detect the temperatures of the substrates 23 and 24, respectively, and output the temperature data signals TD3 and TD4 to the bus line 22, respectively. The temperature detectors 37 of the boards 33 and 34 detect the temperatures of the boards 33 and 34, respectively, and output the temperature data signals TD5 and TD6 to the bus line 32, respectively. Temperature data signals TD1, TD2, temperature data signals TD3, TD4, and temperature data signal TD output to bus lines 12, 22, 32, respectively.
5 and TD6 are supplied to the bus line 3 via the interfaces 11, 21, and 31, respectively.

The CPU 1 measures the elapsed time of the warm-up (time count) and executes the control program stored in the memory 2 to execute the board 13, 14, 23,
The temperature of the substrate designated in advance among 24, 33, and 34 is monitored. The designation of the board is performed by a command from the operator to the CPU 1. Hereinafter, the description will be made assuming that the substrate 13 is specified.

The CPU 1 receives the temperature data signals TD1, TD2, TD3, TD4, TD supplied from the bus line 3.
5. Only the temperature data signal TD1 corresponding to the temperature of the substrate 13 is extracted from TD6. Then, the CPU 1 determines whether the temperature of the substrate 13 satisfies a predetermined condition. The condition used for the determination is the timing control circuit 1
6, so that the operation of the device power supply circuit 26 and the pin electronics circuit 36 is stabilized,
3, 24, 33, and 34 are set and stored in the memory 2 in advance. Here, the specified determination condition of the substrate 13 is applied.

In the case of the substrate 13, the temperature data signal TD 1 indicates the temperatures detected by the temperature sensors 41 a and 41 b in FIG. 2, respectively, and the lower temperature is the temperature of the substrate 13. Then, the CPU 1 determines whether or not the temperature of the substrate 13 is within a predetermined temperature range.

When the temperature of substrate 13 is within a predetermined temperature range, CPU 1 transmits control data signals CD1, CD2, CD
3, CD4, CD5, and CD6 are output to the bus line 3, respectively.

If the temperature of the substrate 13 is out of the predetermined temperature range, the CPU 1 determines whether or not the measured warm-up elapsed time exceeds a predetermined time limit. If the time limit is not exceeded, warm-up is continued. If the time limit is exceeded, error processing such as issuing an alarm is performed.

Control data signal C output from CPU 1
D1 and CD2 are supplied to the timing control circuit 16 of the substrates 13 and 14 via the interface 11 and the bus line 12, respectively. Control data signals CD3, C
D4 is supplied to the device power supply circuits 26 of the substrates 23 and 24 via the interface 21 and the bus line 22, respectively. The control data signals CD5 and CD6 are supplied to the pin electronics circuits 36 of the substrates 33 and 34 via the interface 31 and the bus line 32, respectively.

The timing control circuit 16 of the substrates 13 and 14
Stops the execution of the warm-up based on the supplied control data signals CD1 and CD2,
Perform each system calibration. The device power supply circuits 26 of the substrates 23 and 24 stop executing the warm-up based on the supplied control data signals CD3 and CD4, and execute the system calibration, respectively. The pin electronics circuits 36 of the substrates 33 and 34 respectively stop executing warm-up and execute system calibration based on the supplied control data signals CD5 and CD6.

Next, a method of restoring the IC test apparatus shown in FIG. 1 when a failure occurs will be described.

FIG. 5 is a flowchart showing a method of recovering from a failure in the IC test apparatus of FIG.

When a failure occurs in the IC test apparatus, the failure diagnosis program stored in the memory 2 is automatically executed by the CPU 1 to specify the location of the failure (step S1).

Here, it is assumed that the timing control circuit 16 of the substrate 13 in FIG. 1 has failed.

Next, the main power supply is manually turned off, and the IC
The test device is stopped (Step S2).

Subsequently, the operation of replacing the board 13 with the spare board 15 is performed, and the spare board 15 is mounted on the timing controller 10 (step S3). At this time, another board having the same configuration as the spare board 15 is mounted in the dummy socket 19 in order to prepare for a failure again.

The time required for the replacement work is about several minutes,
The reduction in the temperature of the substrates 14, 23, 24, 33, 34 accompanying the replacement operation is small. Further, as mentioned above,
The spare board 15 has already been preheated, and the temperature of the spare board 15 at the time when the replacement operation has been completed is almost equal to that of the board 14.

In the following description, it is assumed that the spare board 15 mounted in step S3 is the board 13 in FIG.

Next, the main power supply is manually turned on, and the IC test apparatus is restarted (step S4). Immediately after that, the execution of the warm-up is automatically started (step S
5).

During the warm-up, the substrates 13, 14
Temperature detection unit 17, the temperature detection unit 27 of the substrates 23 and 24,
And the temperature detector 37 of the substrates 33 and 34
14, the temperatures of the substrates 23 and 24 and the substrates 33 and 34 are detected (step S6). The temperature detectors 17 of the substrates 13 and 14 output temperature data signals TD1 and TD2, respectively, and the temperature detectors 27 of the substrates 23 and 24 output temperature data signals TD3 and TD4, respectively.
The temperature detection unit 37 of the temperature data TD5, TD6
Are output.

The CPU 1 outputs the temperature data signals TD1, TD
2, a temperature data signal TD1 of the board 13 specified by the operator is extracted from among TD3, TD4, TD5, and TD6, and it is determined whether the temperature of the board 13 satisfies a predetermined condition (step S7). ). When the temperature of the substrate 13 is within the predetermined temperature range, the CPU 1 determines to stop warm-up, and outputs the control data signals CD1, CD1.
2. Output CD3, CD4, CD5, CD6.

Control data signal C output from CPU 1
Based on D1, CD2, control data signals CD3, CD4, and control data signals CD5, CD6,
The timing control circuit 16 of 14, the device power supply circuit 26 of the substrates 23 and 24, and the pin electronics circuit 36 of the substrates 33 and 34 respectively stop executing the warm-up (step S8) and execute the system calibration (step S8). Step S9).

After the system calibration, an IC test is executed (step S10), and the IC test apparatus is restored.

If the temperature of the substrate 13 is out of the predetermined temperature range in step S7, the CPU 1 determines whether or not the warm-up time limit has been exceeded (step S7).
11). If the time limit is not exceeded, warm-up is continued. If the time limit has been exceeded, error processing is performed (step S12).

In the above-described recovery method, the failure is repaired by using the pre-heated spare board 15, and the stop of the warm-up is determined based on the temperature of the mounted spare board 15. Therefore, the time required for warm-up is several minutes (for example, about 5 minutes).

As described above, in the embodiment of the present invention, the spare board 1 that can be mounted in place of the mounted boards 13 and 14 is used.
5, a spare board 25 that can be mounted in place of the mounted boards 23 and 24, and a spare board 35 that can be mounted in place of the mounted boards 33 and 34. Moreover, those spare substrates 15, 25, 35 are used as temperature detecting units 17, 27,
37 and are preheated before mounting. When the IC test apparatus fails, the pre-heated spare board 15, 25, or 35 is replaced with the failed board and mounted to perform repair. Temperature detector 17 of mounted spare board 15 and temperature detector 2 of spare board 25
7, or the temperature detector 37 of the spare board 35 detects the temperature of the spare board 15, 25, or 35 during the warm-up, and execution of the warm-up is stopped based on the detected temperature. For this reason, the warm-up execution time can be reduced to about 1/6 of the conventional one, and a decrease in the operation rate due to a failure is suppressed.

In the above-described embodiment, the spare board is mounted on the dummy socket provided in the IC test apparatus, and the heat generated by the board in operation is transmitted.
The preliminary substrate is being preheated. However, the present invention is not limited to this. By providing a storage means capable of controlling the temperature (for example, a constant temperature bath or the like) and storing the spare board before mounting in the storage means, Can be preheated.

As the temperature sensor, a sensor using a bimetal, a thermistor, or the like can be used.

[0096]

As described above, according to the semiconductor integrated circuit test apparatus and the method for restoring the failure of the semiconductor integrated circuit of the present invention, the execution time of the warm-up after the restoration of the failure can be shortened. Therefore, it is possible to suppress a decrease in the operation rate due to the failure.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention.

FIG. 2 is a perspective view showing a temperature detection unit of the semiconductor integrated circuit test device of FIG.

FIG. 3 is a block diagram illustrating a temperature sensor of a temperature detection unit in FIG. 2;

FIG. 4 is a perspective view showing a mounted state of a substrate and a spare substrate of the semiconductor integrated circuit test device of FIG. 1;

FIG. 5 is a flowchart showing a recovery method when a failure occurs in the semiconductor integrated circuit test apparatus of FIG. 1;

FIG. 6 is a flowchart showing the operation of a conventional semiconductor integrated circuit test device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Memory 3 Bus line 7, 8, 9 Frame 10 Timing control unit 11 Interface 12 Bus line 13, 14 Mounted board 15 Spare board 16 Timing control circuit 17 Temperature detecting unit 18 Mounting socket 19 Dummy socket 20 Device Power supply unit 21 Interface 22 Bus line 23, 24 Mounted board 25 Spare board 26 Device power supply circuit 27 Temperature detection unit 28 Mounting socket 29 Dummy socket 30 Pin electronics unit 31 Interface 32 Bus line 33, 34 Mounted board 35 Spare board 36-pin electronics circuit 37 Temperature detector 38 Mounting socket 39 Dummy socket 41a, 41b Temperature sensor 42a, 42b Ground plane 43 Temperature data generator 1a, 61b, 61c, 61d, 61e phase inverter 61f, 61 g phase inverter 62 phase comparator

Claims (9)

[Claims] 1. A semiconductor integrated circuit test apparatus in which warm-up is performed at the time of start-up for stabilizing operation, a spare board that can be mounted in place of a faulty board when a fault occurs, and a spare board that is mounted when the spare board is mounted. Temperature detection means for detecting the temperature of the spare board, wherein the spare board is pre-heated before mounting, and is executed by restarting when the failure is repaired by mounting the spare board. Said warm-up,
A semiconductor integrated circuit test apparatus for stopping the operation based on the detected temperature of the spare substrate. 2. The semiconductor integrated circuit test apparatus according to claim 1, wherein said temperature detecting means is provided on said spare substrate. 3. The spare board is provided with a plurality of the temperature detecting means, and a minimum value of the temperature detected by each of the plurality of temperature detecting means is set as a temperature of the spare board. The semiconductor integrated circuit test apparatus according to the above. 4. The semiconductor integrated circuit testing device according to claim 2, wherein said temperature detecting means is provided in close contact with a ground wiring region of said spare substrate. 5. The temperature detecting means detects a phase difference between a plurality of phase inverters connected in cascade and an input signal to the first-stage phase inverter and an output signal from the last-stage phase comparator. And a phase comparator, wherein the phase comparing means comprises:
5. The semiconductor integrated circuit test apparatus according to claim 2, wherein a signal corresponding to a temperature of the mounted spare substrate is output to the control unit. 6. A spare board holding means provided adjacent to a position where the spare board is to be mounted, wherein the spare board before mounting is held by the spare board holding means. 6. The semiconductor integrated circuit test apparatus according to claim 1, wherein the substrate is heated before mounting. 7. A spare board storage means capable of heating the accommodated spare board before mounting.
6. The semiconductor integrated circuit test apparatus according to any one of 5. 8. A method for restoring a failure of a semiconductor integrated circuit test apparatus in which a warm-up operation is performed for stabilizing operation at the time of starting, wherein a pre-heated spare board is mounted in place of the failure board at the time of failure. Repairing the failure, after repairing the failure, restarting and executing the warm-up, and detecting the temperature of the mounted spare board during the execution of the warm-up. Stopping the warm-up based on the detected temperature of the spare substrate. 9. The recovery method for a semiconductor integrated circuit test apparatus according to claim 8, wherein temperatures of a plurality of portions of the spare substrate are detected, and a minimum value of the temperatures of the plurality of portions is set as the temperature of the spare substrate.