JP2001036402A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit whose lockup time is short, whose power consumption is small and whose cost is at a low cost and which is easily made an LSI. SOLUTION: This device is provided with a generating means 3 generating a plurality of reference signals whose phases are mutually different, 1st and 2nd frequency dividing parts 2 and 31a respectively perform frequency division of an output signal of a voltage controlled oscillator 29, and phase comparators 12 to 19 which compare each feedback signal with each reference signal outputted from the parts 2 and 31a in a phase and output an error signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a PLL device.

[0002]

2. Description of the Related Art Conventionally, this type of apparatus is, for example, "SANY
O TECHNICAL REVIEW ”, VOL. 1
0, NO. 1, FEB. It is shown on page 32 of 1978. However, this device is a one-stage phase comparator (using only one stage comparator), and performs only one phase comparison during one cycle of the reference signal. The first disadvantage is that the time until the signal is synchronized is short.

[0003] In order to solve this drawback, Japanese Patent Laid-Open No.
No. 135822 has been proposed. According to this publication, generating means for generating a plurality of reference signals having different phases, a plurality of (for example, four) frequency dividers for dividing an output signal of the voltage controlled oscillator, and a feedback signal of each frequency divider are provided. A plurality of phase comparators for comparing each reference signal and a plurality of gates and the like provided on the input side of each frequency divider are provided.

[0004]

However, the apparatus disclosed in the above publication has a second drawback in that the power consumption is large. The inventor of the present invention has investigated the cause and found that the reason is that a plurality of frequency dividers are provided. If the phase comparison is performed eight times during one cycle of the reference signal in order to further reduce the lock-up time, eight frequency dividers are required, and the power consumption is further increased.

Further, since a plurality of frequency dividers requiring a relatively large amount of space are used, there is a third disadvantage that the size of the apparatus is increased, the cost is increased, and it is difficult to implement an LSI. Therefore, the present invention provides a PLL device that has a short lock-up time, consumes less power, is inexpensive, and can be easily made into an LSI in consideration of the conventional drawbacks.

[0006]

In order to solve the above-mentioned problems, according to the present invention, a generating means for generating a plurality of reference signals having different phases from each other and an output signal of a voltage-controlled oscillator are respectively separated. A first frequency divider and a second frequency divider,
A phase comparator that compares the phases of the feedback signals output by the first frequency divider and the second frequency divider with the reference signals and outputs an error signal.

According to a second aspect of the present invention, there is provided a main frequency divider for dividing the output signal by a frequency dividing ratio N1, and a sub frequency divider for dividing the output of the main frequency divider by a frequency dividing ratio N2. , A distribution circuit that distributes the output of the sub-divider to the plurality of feedback signals, configures the first frequency divider, and forms the main frequency divider and the sub-frequency divider with a variable frequency divider or It consists of a counter.

According to a third aspect of the present invention, the second frequency divider is constituted by a variable frequency divider for dividing the frequency by a set frequency division ratio N, and a product of the frequency division ratio N1 and the frequency division ratio N2 is provided. To the set division ratio N or a value close thereto.

According to a fourth aspect of the present invention, the first frequency divider is operated before locking, the first frequency divider is stopped after locking, and the second frequency divider is locked before and after locking. The frequency division is continued at the set frequency division ratio N.

According to a fifth aspect of the present invention, the distribution circuit includes:
A plurality of phase comparators are provided for outputting the respective feedback signals in accordance with the generation timing of the respective reference signals, and comparing the phases of the respective feedback signals and the respective reference signals.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL device 1 according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of the PLL device 1, and FIG. 2 is a detailed block diagram of a first frequency divider 2 used in the PLL device 1.

In these figures, the generating means 3 is, for example,
A reference oscillator 4, seven delay circuits 5 connected in series,
6, 7, 8, 9, 10, 11 and the like. The reference oscillator 4 outputs a reference signal fR1 of 10 KHZ, for example. The timing chart of FIG. 4 shows the waveform of the reference signal fR1. The reference signal fR1 is at timings T1 and T9.
In, is standing up. The reference signal fR1 is supplied to the phase comparator 12
Is input to one side.

The delay circuit 5 delays the reference signal fR1 by 1/8 (1/8 period) of one cycle (1Tref) of the reference signal fR1, and supplies it to the phase comparator 13 as the reference signal fR2. The delay circuit 6 delays the reference signal fR1 by ／ cycle, and supplies it to the phase comparator 14 as the reference signal fR3.

The delay circuit 7 delays the reference signal fR1 by 3/8 cycle, and supplies it to the phase comparator 15 as a reference signal fR4. The delay circuit 8 sets the reference signal fR1 to 4
/ 8 cycle, and using it as a reference signal fR5,
It is provided to the phase comparator 16.

The delay circuit 9 delays the reference signal fR1 by ／ cycle, and supplies it to the phase comparator 17 as a reference signal fR6. The delay circuit 10 delays the reference signal fR1 by 6/8 cycle, and supplies it to the phase comparator 18 as the reference signal fR7. The delay circuit 11 receives the reference signal f
R1 is delayed by 7/8 period, and is delayed by the reference signal fR8.
To the phase comparator 19.

As described above, the generating means 3 generates a plurality of reference signals fR1 to fR8 having different phases. Reference signals fR1, fR2, fR3, fR4, fR5, fR6,
At the time of rising of fR7 and fR8, timing T
1, T2, T3, T4, T5, T6, T7, and T8 (see FIG. 4).

The feedback signals fV1, fV2, fV3, fV
4, fV5, fV6, fV7, fV8 (described later)
Phase comparators 12, 13, 14, 15, 16, 17, 1
8 and 19 are input to the other side.

The phase comparator 12 compares the phase of the feedback signal fV1 with the phase of the reference signal fR1, and outputs a pump-up signal and a pump-down signal to the charge pump 20 as a result of the comparison. The charge pump 20 supplies the error signal ER to the low-pass filter 21 in accordance with the two signals.
Outputs 1.

Similarly, the phase comparators 13, 14, 15, 1
6, 17, 18, and 19 are feedback signals fV2, fV3, f
Each phase of V4, fV5, fV6, fV7, fV8 and reference signals fR2, fR3, fR4, fR5, fR6, fR
7. Compare each phase of fR8.

As a result of the above comparison, the phase comparators 13, 14,
15, 16, 17, 18, 19 respectively correspond to the charge pumps 22, 23, 24, 25, 26, 27, 28.
It outputs a pump up signal and a pump down signal. Charge pumps 22, 23, 24, 25, 26, 27, 2
8, according to each of the above signals, the error signals ER2, ER3, ER4, ER5,
ER6, ER7, and ER8 are output.

The low-pass filter 21 outputs each error signal ER
A control voltage CV is output to the voltage controlled oscillator 29 in response to 1 to ER8. Voltage controlled oscillator 29 outputs output signal fVCO in response to control voltage CV.

The first frequency divider 2 comprises a main frequency divider 30, a sub frequency divider 31, a distribution circuit 32 and the like. The main frequency divider 30 outputs the output signal fVCO of the voltage controlled oscillator 29.
Is divided by the dividing ratio N1 to output an intermediate signal fV ′. The sub-divider 31 divides the output (intermediate signal fV ′) of the main divider 30 by a division ratio N2, and outputs a signal (Q1).
a, Q2a, Q3a).

The second frequency divider 31a is composed of, for example, a 13-bit variable frequency divider. The input side is connected to the connection point between the voltage controlled oscillator 29 and the main frequency divider 30, and the output side is connected to the phase comparator 12.
Connected to the other side. The control unit 58 (described later)
A set dividing ratio N (N is an integer) is set for the dividing unit 31a.

With this configuration, the second frequency divider 31a outputs the output signal fVCO of the voltage controlled oscillator 29 at the set frequency division ratio N, and outputs the output (feedback signal fV1) of the phase comparator 1.
Supply to 2. As described above, the second frequency divider 31a includes at least one phase comparator (in the above example, the phase comparator 12).
Outputs a feedback signal fV1. If necessary, the second frequency divider 31a may output a feedback signal to two or more phase comparators.

The distribution circuit 32 converts the intermediate signal fV 'and the outputs (signals Q1a, Q2a, Q3a) of the sub-divider 31 into a plurality of feedback signals fV2, fV3, fV4, fV5, fV.
6, fV7 and fV8, and converted into phase comparators 13 to
19 is output.

The main frequency divider 30 includes, for example, an input terminal 33,
Inverter 34, toggle flip-flops 35, 3
6, 37, 38, and 39; an inverter 40; an AND gate 41; a D-flip-flop 42;
3 and so on.

The inverter 34 is connected between the input terminal 33 and the toggle flip-flop 35. Each of the toggle flip-flops 35, 36, 37, 38, and 39 has, for example, an input inversion function, and is connected in series. Each J terminal of the toggle flip-flops 35 to 39 is connected to input terminals D1, D2, D3, D4, D5.

A counter 44 is constituted by the toggle flip-flops 35 to 39. The counter 44 uses the inverted signal of the output signal fVCO as a clock pulse CL and counts down at the frequency dividing ratio N1 given to the input terminals D1 to D5. The countdown is preset by the signal PR applied to the terminal PE.

The matching circuit 45 is connected to the inverter 40 and AND
It comprises a gate 41 and the like. Toggle flip-flop 35,
Each output terminal Q of 37, 38, and 39 is connected to the input terminal of the AND gate 41, respectively. The output terminal Q of the toggle flip-flop 36 is connected to the
It is connected to the input terminal of the ND gate 41. Thus, when the output of the counter 44 becomes "2", the coincidence circuit 45 outputs the detection signal CO which becomes High.

The D-flip-flop 42 has, for example, a built-in input inversion function. The D-flip-flop 42 uses the inverted signal of the output signal fVCO as a clock pulse and converts the detection signal CO of the coincidence circuit 45 by one-frequency division of the output signal fVCO. The delayed signal PR is output from the terminal Q. That is, the signal PR (intermediate signal fV ′) is output from the output terminal 43.

As described above, the input terminals D1, D2, D3,
When a predetermined input is made to each of D4 and D5, the dividing ratio N1
Is determined, and the intermediate signal fV ′ obtained by dividing the output signal fVCO by N1 is output from the output terminal 43. Like this
The main frequency divider 30 is composed of, for example, a 10-bit variable frequency divider or a counter.

The sub frequency divider 31 is, for example, an inverter 34a
And toggle flip-flops 35a and 36a, 37a,
38a, 39a, an inverter 40a, an AND gate 41a, a D-flip-flop 42a, and an output terminal 4
3a.

The inverter 34a is connected between the output terminal 43 of the main frequency divider 30 and the toggle flip-flop 35a. Toggle flip-flops 35a, 36a,
37a, 38a, and 39a, for example, each have a built-in input inversion function, and are connected in series. Each J terminal of the toggle flip-flops 35a to 39a is connected to input terminals D1a, D2a, D3a, D4a, and D5a.

A counter 44a is constituted by the toggle flip-flops 35a to 39a.
The inverted signal of the intermediate signal fV 'is used as a clock pulse CLa, the countdown is performed at the frequency division ratio N2 given to the input terminals D1a to D5a, and the downcount is preset by the signal PRa applied to the terminal PE.

The coincidence circuit 45a is connected to the inverter 40a and A
It comprises an ND gate 41a and the like. Each output terminal Q of the toggle flip-flop 35a, 37a, 38a, 39a is connected to the input terminal of the AND gate 41a.
The output terminal Q of the toggle flip-flop 36a is connected to the input terminal of the AND gate 41a via the inverter 40a. In this way, when the output of the counter 44a becomes "2", the coincidence circuit 45a outputs the detection signal COa which becomes High.

The D-flip-flop 42a has, for example, a built-in input inverting function, and uses the inverted signal of the intermediate signal fV 'as a clock pulse to divide the detection signal COa of the coincidence circuit 45a by 1 of the intermediate signal fV'. And outputs a signal PRa delayed by only

With the above configuration, the input terminals D1a, D2
When a predetermined input is made to each of a, D3a, D4a, and D5a, the frequency division ratio N2 is determined. For example, when N2 = 8, the signal Q1a obtained by dividing the intermediate signal fV 'by 2
Is output from the output terminal Q of the toggle flip-flop 35a.

The signal Q2a obtained by dividing the intermediate signal fV 'by four is output to the output terminal Q of the toggle flip-flop 36a.
Output from A signal Q3 obtained by dividing the intermediate signal fV 'by 8
a is output from the output terminal Q of the toggle flip-flop 37a. As described above, the sub-divider 31 is constituted by, for example, a 3-bit variable frequency divider or a counter.

The distribution circuit 32 is, for example, a decoder, and includes conductive lines 46, 47, 48, and 49 and AND gates 51 and 5,
2, 53, 54, 55, 56 and 57. The conductive lines 46, 47, 48, 49 each have an intermediate signal f
V 'and signals Q1a, Q2a, Q3a. The conductive lines 46, 47, 48, and 49 are also connected to the first terminal, the second terminal, and the third terminal provided on each of the AND gates 51 to 57.
Terminal and the fourth terminal.

With this configuration, the AND gate 51 outputs a signal fV2 obtained by ANDing the signal fV ', the inversion of Q1a, and the inversions of Q2a and Q3a. AND gate 52
Outputs a signal fV3 obtained by logically ANDing the signal fV ', Q1a, Q2a, and the inverse of Q3a. AND gate 53
Are the signal fV ', the inversion of Q1a, the inversion of Q2a and Q
A signal fV4 obtained by ANDing 3a is output.

The AND gate 54 outputs the signal fV 'and Q1
a and the inverted signal of Q2a and the signal fV5 obtained by ANDing Q3a
Is output. The AND gate 55 outputs the signal fV ′ and Q1
The signal fV6 obtained by ANDing a and a logical product of Q2a and Q3a
Is output. The AND gate 56 outputs the signal fV ′ and Q1
a, and outputs a signal fV7 obtained by ANDing Q2a and Q3a. The AND gate 57 outputs the signal fV ′ obtained by ANDing the signal fV ′, the inversion of Q1a, the inversion of Q2a and the inversion of Q3a.
V8 is output. The PLL device 1 is configured by the above components.

Next, according to FIG. 1 to FIG.
The operation of the device 1 will be described. FIG. 3 shows signals fVCO, CL, Q1, Q2, Q3, Q4, Q used in the PLL device 1.
5, CO, PR timing chart, FIG.
5 is a timing chart of V ′, fV1 to fV8.

First, it is assumed that, for example, 1280 KHZ as a set frequency of the output signal fVCO is input to the control unit 58 via input means (not shown). The control unit 58
As the set dividing ratio N of the second dividing section 31a, N = 1280
KHZ / 10KHZ = 128 (the frequency of the reference signal is 10
KHZ).

Then, the control unit 58 sets the dividing ratio N = 1.
28, the frequency division ratio N1 of the main frequency divider 30 is determined as 16 and the frequency division ratio of the sub frequency divider 31 is determined as N2 = 8. That is, the control unit 58 performs control such that the product of the frequency division ratio N1 and the frequency division ratio N2 matches the set frequency division ratio N of the second frequency division unit 31a.

According to the determination of the frequency division ratio N1 = 16, the input terminals D1, D2, D3, D
4 and D5 respectively have “High”, “High”, and “H”.
“high”, “High”, and “Low” signals are input. As described above, the predetermined input (Hi) is applied to the input terminals D1 to D5.
gh or Low) is input, the main frequency divider 30
Comprises a variable frequency divider or counter capable of dividing the output signal fVCO with a variable (programmable) frequency dividing ratio N1.

At this time, the clock pulse CL has the waveform shown by CL in FIG. 3 because the output signal fVCO is inverted. As shown in FIG. 3, the signal Q1 is delayed by one division of the output signal fVCO, and the output signal fVCO is
It becomes a divided waveform. The signal Q2 is delayed from the signal Q1 by a predetermined phase, and has a waveform obtained by dividing the signal Q1 by two.

The signal Q3 is delayed from the signal Q2 by a predetermined phase, and has a waveform obtained by dividing the signal Q2 by two. Signal Q4
Is a waveform obtained by delaying the signal Q3 by a predetermined phase and dividing the signal Q3 by two. The signal Q5 is delayed from the signal Q4 by a predetermined phase, and has a waveform obtained by dividing the signal Q4 by two.

The AND gate 41 logically ANDs the signals Q1, Q2, Q3, Q4, and Q5 and outputs a signal CO (see the waveform diagram of CO in FIG. 3). The signal CO is
The output signal fVCO is delayed by one division and the signal PR is delayed.
(FV '). When the signal PR is applied to the terminals PE of the toggle flip-flops 35 to 39, the signals Q1 to Q5 have waveforms with preset down counts. In this way, the main frequency divider 30 outputs the intermediate signal f obtained by dividing the output signal by the N1 division ratio (N1 = 16).
V ′ is output.

The intermediate signal fV 'is input to the toggle flip-flop 35a via the inverter 34a of the sub frequency divider 31. Further, as described above, the input terminals D1a and D2 provided in the sub-divider 31 according to the division ratio N2 = 8.
a, D3a, D4a, and D5a each have "High",
"High", "High", "Low", "High"
A signal is input.

In this way, by inputting a predetermined input (High or Low) to the input terminals D1a to D5a, the sub-divider 31 can control the intermediate frequency at a variable (programmable) frequency division ratio N2. It is composed of a variable frequency divider or a counter that can divide the signal fV '.

As in FIG. 3, the signal Q1a is delayed from the intermediate signal fV 'by a predetermined phase to
It becomes a divided waveform. The signal Q2a is delayed from the signal Q1a by a predetermined phase, and has a waveform obtained by dividing the signal Q1a by two. The signal Q3a is delayed from the signal Q2a by a predetermined phase, and has a waveform obtained by dividing the signal Q2a by two. Signal Q4
a is delayed from the signal Q3a by a predetermined phase,
The waveform is obtained by dividing 3a by two. The signal Q5a has a waveform obtained by delaying the signal Q4a by a predetermined phase and dividing the signal Q4a by two.

The AND gate 41a outputs the signal Q1a and the signal Q1.
Invert 2a and AND with Q3a, Q4a and Q5a,
The signal COa is output. D-flip-flop 42
The signal PRa is output in response to the input of the signal COa. The signal P is applied to the terminals PE of the toggle flip-flops 35a to 39a.
By applying Ra, the signals Q1a to Q5a have waveforms in which the down-count is preset.

With the above configuration, the sub-divider 31 outputs the signal Q1a obtained by dividing the intermediate signal fV 'by 2, and the intermediate signal fV'.
To the distribution circuit 32. The signal Q2a obtained by dividing the frequency by 4 and the signal Q3a obtained by dividing the intermediate signal fV 'by 8 (N2 = 8) are output.

In the distribution circuit 32, the intermediate signal fV '
The signals Q1a, Q2a, Q3a are respectively conductive lines 46, 47,
The signals are input to the respective input terminals of the AND gates 51 to 57 via 48 and 49.

The feedback signal fV output from the second frequency divider 31a
The control unit 58 controls the second frequency dividing unit 31a such that 1 is synchronized with the intermediate signal fV '(without a phase difference) and has a waveform obtained by dividing the intermediate signal fV' by eight.

The AND gate 51 outputs the signal fV and Q1a.
, And a feedback signal fV2 obtained by ANDing Q2a and Q3a. As a result, as shown in FIG. 4, the feedback signal fV2 is obtained by dividing the intermediate signal fV 'by one frequency.
The waveform is delayed to V1 and the intermediate signal fV 'is divided by eight.

Similarly, the feedback signals fV3, fV4, fV
5, fV6, fV7, and fV8 are delayed by two, three, four, five, six, and seven divisions of the intermediate signal fV 'to the feedback signal fV1, respectively, and all have a waveform obtained by dividing the intermediate signal fV' by eight.

Next, the frequency of the reference signal fR1 is obtained.
fR1 = fVCO / N. FVCO = N1 × f
V ′, N = N1 × N2. Therefore, fR1 = (N1
× fV ′) / (N1 × N2) = fV ′ / N2 = fV ′ /
8, that is, the reference signal fR1 is obtained by dividing the intermediate signal fV 'by eight. Therefore, one cycle Tref of the reference signal fR1
Is as shown in FIG. That is, the feedback signal fV
1, fV2, fV3, fV4, fV5, fV6, fV
7, the rise of fV8 is based on the aforementioned reference signals fR1 to fR8.
Rising timings T1, T2, T3, T4, T5,
It can be seen that they coincide with T6, T7, and T8 (see FIG. 4).

In this way, the phase comparators 12, 13, 1
4, 15, 16, 17, 18, and 19 are feedback signals fV1, fV2, fV3, fV4, fV5 at timings T1, T2, T3, T4, T5, T6, T7, and T8, respectively.
Each phase of fV6, fV7, fV8 and the reference signal fR1,
fR2, fR3, fR4, fR5, fR6, fR7, f
Each phase of R8 is compared.

That is, the control section 58 causes the second frequency dividing section 31a to output the feedback signal fV1 in accordance with the generation timing of the reference signal fR1, and the phase comparator 12 outputs the feedback signal fV1 and the reference signal fR1. Are compared in phase. After the lock, the operation of the first frequency divider 2 is stopped and the second frequency divider 31
By operating only a, power consumption can be reduced. Further, the distribution circuit 32 includes the reference signals fR2 to fR
8, each of the feedback signals fV2 to fV
V8, and the phase comparators 22 to 28 compare the phases of the feedback signals fV2 to fV8 and the reference signals fR2 to fR8, respectively.

According to this configuration, the phase comparison is performed eight times during one cycle (Tref) of the reference signal fR1, so that the lock-up time (synchronized with the output signal fVCO) is higher than that of the conventional single-stage phase comparator. Time until the time is shortened to about 1/8 times.

As a result of the comparison, the phase comparators 12 to 12
Reference numeral 19 outputs a pump-up signal and a pump-down signal to the charge pumps 20 to 28, respectively. The charge pumps 20 to 28 output error signals ER1 to ER8 to the low-pass filter 21 in accordance with the two signals.

The low-pass filter 21 outputs each error signal ER
A control voltage CV is output to the voltage controlled oscillator 29 in response to 1 to ER8. Voltage controlled oscillator 29 outputs output signal fVCO in response to control voltage CV.

By repeating the operation in the above loop, the PLL device 1 sends the set frequency 1280 KHZ to the output terminal 59 connected to the output side of the voltage controlled oscillator 29.
Will be output.

Further, for example, 320 KHz as the set frequency of the output signal fVCO is input to the control unit 5 via the input means.
It is assumed that the input has been made to 8. The control unit 58 controls the second frequency dividing unit 31
As the set dividing ratio N of a, N = 320 KHZ / 10 KH
Calculate Z = 32.

Then, the control section 58 sets the division ratio N = 3
2, the division ratio N of the main divider 30 and the division ratio N2 of the sub divider 31 are determined as N = 16 and N2 = 2, respectively. As described above, when the set frequency division ratio N = 32 is relatively small, the control unit 58 determines the frequency division ratio N2 of the sub frequency divider 31 to a relatively small value (for example, 2).

With this configuration, the power consumption in the sub-frequency divider 31 can be reduced by reducing the frequency division ratio N2. As described above, the frequency division ratio N2
Is the number of phase comparators 12 to 19 (8 in the above description)
It is provided below. For example, the dividing ratio N2 is 1, 2,
3, 4, 5, 6, 7, and 8 are selected.

As described above, the dividing ratio N2 is the set dividing ratio N
An appropriate value is selected from the magnitude of 1, the desired lockup time, the desired power consumption, and the like. Sub divider 31
Is composed of a variable frequency divider or a counter, so that an appropriate frequency division ratio N2 can be selected as described above.

For example, it is assumed that 1290 KHZ is input to the control unit 58 via the input means as the set frequency of the output signal fVCO. In this case, the control unit 58
Is N = 12 as the set dividing ratio N of the second dividing section 31a.
9 is calculated.

Then, the control unit 58 sets the division ratio N = 1.
29, the frequency division ratio N1 of the main frequency divider 30 is determined as 16 and the frequency division ratio N2 of the sub frequency divider 31 is determined as 8. Like this
The control unit 58 matches the product of the frequency division ratio N1 and the frequency division ratio N2 with the set frequency division ratio N or a value close thereto. As a result, P
As described above, the LL device 1 outputs, to the output terminal 59, the output signal fVCO obtained by multiplying the dividing ratio N1 × N2 = 128 by the reference frequency.

For example, each AND gate (not shown) to which the pump-up signal and the pump-down signal output from each of the phase comparators 12 to 19 are provided is provided. By inputting the output of each AND gate to the control unit 58, the control unit 58
Can detect that the output signal fVCO has reached the division ratio N1 × N2 = 129 (at this time, the control unit 58 determines that the locking has been performed).

After the detection, the control unit 58 sets the main frequency divider 30
Then, the operation of the sub-divider 31 is stopped, the second divider 31a is operated, and the division is continued at the set division ratio N = 129.
As a result, even after locking, the second frequency divider 31a outputs to the phase comparator 12 a feedback signal fV1 obtained by dividing the output signal fVCO to the set division ratio N1 = 129. Then, the PLL device 1 multiplies the output terminal 59 by the set frequency division ratio N = 129 (set frequency 1290 KHZ) and outputs the output signal fV.
Outputs CO.

As described above, for a predetermined division ratio (for example, N = 129) related to the output signal fVCO, first, the main divider 30, the sub divider 31, and the second divider 31a output the output signal fVCO. After the frequency of the fVCO is divided and locked, the frequency is divided only by the second frequency divider 31a.

As described above, the second frequency dividing section 31a always performs frequency division at the set frequency division ratio N = 128 before and after locking. Therefore, when lock is detected, the frequency division ratio is changed from N1 × N2 to N
When changing to N, the frequency division ratio changes smoothly (no overshoot or the like) (because the difference between the value of N1 × N2 and the value of N is relatively small). Therefore, after the lock is detected, the frequency division by the sub frequency divider 31 is stopped, and the frequency division ratio of the main frequency divider 30 is switched from N1 to N (the difference between the value of N1 and the value of N is relatively large). According to the present invention, since the frequency division ratio can be switched more smoothly, the lock-up time is shorter than in the above configuration.

With this configuration, the frequency division ratio N of the main frequency divider 30
The output signal fVCO obtained by multiplying the reference frequency by the set frequency dividing ratio N is also used for a set frequency dividing ratio N (for example, N = 129) which is not a product of 1 and the frequency dividing ratio N2 of the sub frequency divider 31. You can get it.

The frequency dividing ratio N1 of the main frequency divider 30 (for example, N1 = 16) and the frequency dividing ratio N2 of the sub frequency divider 31 (for example, N2
= 8), the set dividing ratio N (for example, N = 12)
8), the output signal fVCO is frequency-divided by the main frequency divider 30, the sub-frequency divider 31, and the second frequency divider 31a, locked, and then frequency-divided only by the second frequency divider 31a. .

As described above, at the time of rising (before locking), the main frequency divider 30, the sub frequency divider 31, and the second frequency divider 31a
, The lock-up time is shortened. Then, after rising (after locking), the main frequency divider 30
And the operation of the sub frequency divider 31 is stopped, and the second frequency divider 31a
The power consumption can be reduced by dividing the frequency by only the frequency.

[0078]

As described above, according to the first aspect of the present invention, the generating means for generating a plurality of reference signals having different phases from each other, and the first frequency divider for dividing the output signal of the voltage controlled oscillator, respectively. And a second frequency divider, and a phase comparator that compares the phases of the respective feedback signals output by the first frequency divider and the second frequency divider with the respective reference signals and outputs an error signal. As described above, by comparing a plurality of reference signals having different phases with each feedback signal, the phase comparison is performed a plurality of times during one cycle of the reference signal, so that the lock-up time is shortened. Further, since the frequency divider for dividing the output signal is only the first frequency divider and the second frequency divider, there is no need for more than eight frequency dividers as in the prior art. Therefore, the cost is low, the LSI can be easily formed, and the power consumption is small.

According to a second aspect of the present invention, there is provided a main frequency divider for dividing the output signal by a frequency dividing ratio N1, and a sub frequency divider for dividing the output of the main frequency divider by a frequency dividing ratio N2. , A distribution circuit that distributes the output of the sub-divider to the plurality of feedback signals, configures the first frequency divider, and forms the main frequency divider and the sub-frequency divider with a variable frequency divider or It consists of a counter. As described above, since the main frequency divider and the sub frequency divider are configured by variable frequency dividers or counters, the frequency division ratio N1 of the main frequency divider and the frequency division ratio N2 of the sub frequency divider can be set to any values. You can choose from. That is,
The division ratio N2 of the sub-divider is determined from the magnitude of the set division ratio, the desired lock-up time, the desired power consumption, and the like.
Appropriate values can be selected.

According to the third aspect of the present invention, the second frequency divider is constituted by a variable frequency divider that divides the frequency by a set frequency division ratio N, and a product of the frequency division ratio N1 and the frequency division ratio N2. Is set equal to the set dividing ratio N or a value close thereto. As a result, if the frequency of the reference signal is fR1, the frequency of the output signal is fVCO, the frequency of the intermediate signal output from the main frequency divider is fV ', and the set frequency division ratio is N, fR1 =
fVCO / N. FVCO = N1 × fV ′, N
= N1 × N2. Therefore, fR1 = (N1 × f
V ′) / (N1 × N2) = fV ′ / N2. That is,
The reference signal is obtained by dividing the intermediate signal by N2, and the rising timing of each reference signal matches the rising timing of each feedback signal.

According to the present invention, the first frequency divider is operated before locking, the first frequency divider is stopped after locking, and the second frequency divider is locked before and after locking. The frequency division is continued at the set frequency division ratio N. As described above, the first frequency division ratio N1, which is not the product of the frequency division ratio N1 of the main frequency divider and the frequency division ratio N2 of the sub frequency divider, constitutes the first frequency division unit. The frequency is divided in parallel by the peripheral part and the second frequency dividing part. Then, the second frequency dividing unit sets the frequency dividing ratio N
Since the frequency division is always continued,
The frequency division ratio of the output signal can be smoothly changed from N1 × N2 to N. As described above, since the change can be smoothly performed, the lock-up time can be further reduced. And after locking,
Since the first frequency divider is stopped, power consumption is further reduced. Also, at the time of rising (before locking), the first frequency dividing unit and the second frequency dividing unit divide the frequency by the first frequency dividing unit and the second frequency dividing unit with respect to the set frequency dividing ratio N which can be the product of the frequency dividing ratio N1 and the frequency dividing ratio N2. Lock-up time is reduced. Then, after the rise (after lock-up), the power consumption can be further reduced by dividing the frequency only by the second frequency dividing section.

According to a fifth aspect of the present invention, the distribution circuit includes:
A plurality of phase comparators are provided for outputting the respective feedback signals in accordance with the generation timing of the respective reference signals, and comparing the phases of the respective feedback signals and the respective reference signals. With this configuration, in the plurality of phase comparators, the comparison between the plurality of reference signals having different phases and each feedback signal is performed at the same timing, so that the phase comparison can be accurately performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL device 1 according to an embodiment of the present invention.

FIG. 2 is a block diagram of a first frequency divider 2 used in the PLL device 1.

FIG. 3 shows signals Q1 to Q5 used in the PLL device 1.
6 is a timing chart of FIG.

FIG. 4 is a feedback signal FV1 used in the PLL device 1;
It is a timing chart of FV8.

[Explanation of symbols]

2 First frequency divider 3 Generator 12, 13, 14, 15, 16, 17, 18, 19 Phase comparator 29 Voltage controlled oscillator 30 Main frequency divider 31 Secondary frequency divider 31 a Second frequency divider 32 Distribution circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 CC01 CC30 CC38 CC41 CC58 DD32 DD46 GG09 HH10 JJ02 KK03 KK37 KK38 KK40 LL02

Claims (5)

[Claims] 1. A generator for generating a plurality of reference signals having different phases, and an output signal of a voltage controlled oscillator,
A first frequency divider and a second frequency divider for frequency division; and a phase comparing each feedback signal output from the first frequency divider and the second frequency divider with each reference signal to output an error signal. A PLL device comprising a comparator. 2. A main divider that divides the output signal by a dividing ratio N1, a sub divider that divides an output of the main divider by a dividing ratio N2, and the sub divider. And a distribution circuit for distributing the output of the above to the plurality of feedback signals, the first frequency divider is configured, and the main frequency divider and the sub frequency divider are configured by a variable frequency divider or a counter. The PL according to claim 1, wherein
L device. 3. The frequency divider according to claim 2, wherein the second frequency divider is a variable frequency divider that divides the frequency by a preset frequency division ratio N. 3. The PLL device according to claim 2, wherein the ratio is equal to or close to the ratio N. 4. The first frequency divider is operated before locking, the first frequency divider is stopped after locking, the second frequency divider is locked before and after locking, and the setting is performed. 4. The PLL device according to claim 3, wherein frequency division is continued at a frequency division ratio N. 5. The distribution circuit outputs a plurality of feedback signals in accordance with the generation timing of each of the reference signals, and includes a plurality of phase comparators for comparing the phases of each of the feedback signals and each of the reference signals. 2. The PLL according to claim 1, wherein the PLL is provided.
apparatus.