JP2001036398A - Level shifter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a large time loss caused by reread-out by dispensing with the re-layout of the circuit, even when a product specification is changed after a product is completed. SOLUTION: The gate of a first P-channel MOS transistor TP1 and the drain of a second P-channel MOS transistor TP2 are provided at the drain of a second N-channel MOS transistor TN2. The drain of the first P-channel MOS transistor TP1, the source of a third N-channel MOS transistor TN3 and the drain of a third P-channel MOS transistor TP3 are connected to the gate of this second P-channel MOS transistor TP2. The drain of the third NB- channel MOS transistor TN3 and the source of the third P-channel MOS transistor TP3 are connected via a latch circuit R1. Thus, even when the input to the level shifter circuit is made unstable, by fixedly outputting a potential depending on the input signal held in the latch circuit R1, specification changes can be dealt with.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a level shifter circuit for converting a low power supply voltage amplitude signal of a semiconductor integrated circuit requiring a plurality of power supply voltages into a high power supply voltage amplitude signal.

[0002]

2. Description of the Related Art In recent years, a level shifter circuit converts a signal having a low potential level signal amplitude into a signal having a high potential level signal amplitude, and reduces power consumption in a logic circuit having a low potential level signal amplitude. This is used when converting a signal output from a semiconductor device into a signal amplitude output of a high potential level in order to conform to a signal amplitude standard outside the semiconductor device, which contributes to lower power consumption of the semiconductor device.

Hereinafter, a conventional level shifter circuit will be described. 4 and 5 are circuit diagrams showing configuration examples of a conventional level shifter circuit. FIG. 4 shows a high-voltage output fixed level shifter circuit in which a signal from a first input terminal A having an amplitude from the voltage of the first power supply to the voltage of the second power supply is used as a signal from the second power supply. The second N-channel MOS transistor TN1 receives a signal having a phase opposite to that of the signal from the first input terminal A by using a second power supply as a source.
Of the N-channel MOS transistor TN2, and the drain of the second N-channel MOS transistor TN2 is connected to the first P-channel MOS transistor TP1.
Gate and second P-channel MOS transistor TP2
And the gate of the second P-channel MOS transistor TP2 and the drain of the first P-channel MOS transistor TP1 are connected to the output terminal B.
The drain of the channel MOS transistor TN3 is connected to the output terminal B, and the source of the third N-channel MOS transistor TN3 is connected to the second power supply.

[0004] Third N-channel MOS transistor TN
3 and the gate of the third P-channel MOS transistor TP3 are connected to the second input terminal C.
During operation of the circuit, a third power supply voltage is input so that the second power supply voltage has an amplitude from the third power supply voltage, and a signal having the same phase as the signal from the first input terminal A is output from the output terminal B. When the first power supply is turned off by inputting the second power supply voltage when the circuit is not operating,
The signal at the output terminal B is configured to be fixed at the third power supply voltage level.

The operation of the level shifter circuit configured as described above will be described below. As an operation example,
The case where a signal having a low voltage amplitude of 0 V to 2 V is input to a logic circuit block operating at an amplitude voltage of 0 V to 3 V will be described as an example. When a low-voltage power supply is input to the low-voltage amplitude operation circuit (hereinafter referred to as active), first, when the voltage of the low-voltage amplitude signal A is 2 V, the output of the first inverter I1 operating at 2 V is 0 V. And the output of the second inverter I2 operating at 2V voltage is 2V.
At that time, the first N-channel MOS transistor T
N1 is turned on by the output of the second inverter I2, and the second N-channel MOS transistor TN2 is
Is turned off by the output of the inverter I1.

When active, 3V is applied to the second input terminal C.
And the third inverter I3 operating at a high voltage
Output from the third P-channel MOS transistor TP
3 is on, and the third N-channel MOS transistor TN3 is off. At this time, the second node N2
Is 3V, which is the same potential as the potential of the power supply V1 of 3V, the first P-channel MOS transistor TP1 is off,
The first node N1 and the third node N3 are at 0 V, and the second P-channel MOS transistor TP2 is on.

At this time, 3 V is output as an input signal from the output terminal B to the external high-voltage amplitude operation circuit via the fourth inverter I4 operating at a high voltage. When the voltage of the low-voltage amplitude signal at the first input terminal A changes from 2V to 0V, the output of the first inverter I1 changes from 0V to 2V, and the output of the second inverter I2 converts from 2V to 0V. . Thereby, the first N-channel MOS transistor TN1 shifts from the on state to the off state. Also, the second
N-channel MOS transistor TN2 changes from off to on. Both N-channel MOS transistors T
The transition of N1 and TN2 to the ON state lowers the potential of the second node N2, turning on the first P-channel MOS transistor TP1.

At this time, since the first N-channel MOS transistor TN1 has been turned off, the potentials of the first node N1 and the third node N3 rise.
In these operations, the first node N1 is completely at the same potential as the power supply V1 at 3V, the second node N2 is at 0V,
The process ends when the potential of the output terminal B becomes 0 V by the fourth inverter. When the voltage of the low-voltage amplitude signal at the first input terminal A shifts from 0 V to 2 V, the reverse operation is performed, and 3 V is output to the output terminal B.

No input of a low-voltage power supply from the active to the low-voltage swing operation circuit (hereinafter referred to as sleep)
When shifting to the state, the potential of the second input terminal C which is the control terminal of the level shifter circuit is set to 0V. As a result, the third N-channel MOS transistor TN3 turns on, and the third P-channel MOS transistor TP3 turns off. Even when the voltage from the low-voltage operation circuit at the first input terminal A is undefined, the third P-channel MOS transistor TP3 is turned off and the third N-channel MOS transistor TN3 is turned on. 3
The node N3 and the first node N1 are fixed at 0 V, and the voltage of the output terminal B is fixed at 3 V, and does not become unstable. When returning from sleep to active, the normal operation is returned by inputting 3 V to the second input terminal C.

[0010] Similarly, FIG. 5 shows a low-voltage output fixed level shifter circuit which converts a signal from a first input terminal A having an amplitude of a voltage of a second power supply from a voltage of a first power supply into a first N terminal.
A signal having a phase opposite to that of the signal from the first input terminal A is received by the gate of the second N-channel MOS transistor TN2, and a drain of the second N-channel MOS transistor TN2 is received by the gate of the channel MOS transistor TN1. The gate of the first P-channel MOS transistor TP1 is connected to the drain of the second P-channel MOS transistor TP2, and the gate of the second P-channel MOS transistor TP2 and the drain of the first P-channel MOS transistor TP1 are connected to the output terminal B. And the drain of the third P-channel MOS transistor TP3 is connected to the output terminal B.
And a third P-channel MOS transistor T
The source of P3 is connected to a third power supply.

Third N-channel MOS transistor TN
3 and the gate of the third P-channel MOS transistor TP3 are connected to the second input terminal C.
During operation of the circuit, a third power supply voltage is input so that the second power supply voltage has an amplitude from the third power supply voltage, and a signal having the same phase as the signal from the first input terminal A is output from the output terminal B. When the circuit is not operating, the second power supply voltage is input to the second input terminal C so that the signal at the output terminal B can be changed to the third power supply voltage level even when the first power supply is cut off. It is configured to be fixed to.

The operation of the level shifter circuit configured as described above will be described below. As an operation example,
The case where a signal having a low voltage amplitude of 0 V to 2 V is input to a logic circuit block operating at an amplitude voltage of 0 V to 3 V will be described as an example. In the active state, first, when the voltage of the low-voltage amplitude signal A is 2V, the first operating at the 2V voltage
The output of the inverter I1 is 0V, and the output of the second inverter I2 operating at the voltage of 2V is 2V. Also,
At this time, the first N-channel MOS transistor TN1 is turned on by the output of the second inverter I2,
N-channel MOS transistor TN2 is turned off by the output of first inverter I1.

When active, 3V is applied to the second input terminal C.
Is input, the third N-channel MOS transistor TN3 is on, and the third P-channel MOS transistor TP3 is off. At this time, the potential of the second node N2 is 3V, which is the same potential as the potential of the power supply V1 of 3V,
The first P-channel MOS transistor TP1 is off, the first node N1 and the third node N3 are at 0 V, and the second P-channel MOS transistor TP2 is on.

At this time, 3 V is output as an input signal from the output terminal B to the external high-voltage amplitude operation circuit via the third inverter I3 operating at a high voltage. When the voltage of the low-voltage amplitude signal at the first input terminal A changes from 2V to 0V, the output of the first inverter I1 changes from 0V to 2V, and the output of the second inverter I2 converts from 2V to 0V. . Thereby, the first N-channel MOS transistor TN1 shifts from the on state to the off state. Also, the second
N-channel MOS transistor TN2 changes from off to on. Both N-channel MOS transistors T
The transition of N1 and TN2 to the ON state lowers the potential of the second node N2, turning on the first P-channel MOS transistor TP1.

At this time, since the first N-channel MOS transistor TN1 has been turned off, the potentials of the first node N1 and the third node N3 rise.
In these operations, the first node N1 is completely at the same potential as the power supply V1 at 3V, the second node N2 is at 0V,
The process ends when the potential of the output terminal B becomes 0 V by the third inverter. When the voltage of the low-voltage amplitude signal at the first input terminal A shifts from 0 V to 2 V, the reverse operation is performed, and 3 V is output to the output terminal B.

When shifting from the active state to the sleep state, the potential of the second input terminal C which is the control terminal of the level shifter circuit is set to 0V. As a result, the third P-channel MOS transistor TP3 turns on, and the third N-channel MOS transistor TN3 turns off. Even when the voltage from the low-voltage operation circuit at the first input terminal A is undefined, the third N-channel MOS transistor TN3 is turned off and the third P-channel MOS transistor TP3 is turned on. The node N3 of the third node and the first node N1 are fixed at 3V, and the voltage of the output terminal B is fixed at 0V and does not become unstable. When returning from sleep to active, the normal operation is returned by inputting 3 V to the second input terminal C.

[0017]

In the conventional level shifter circuit as described above, the transfer of a signal from a low-voltage operating circuit or a low-voltage operating semiconductor device to a high-voltage operating circuit or a high-voltage operating semiconductor device and ultra-low power consumption are realized. In order to realize a power semiconductor device, a low-voltage operation circuit or a system configuration for turning off the power supply of the low-voltage operation semiconductor device when the low-voltage operation circuit is not operating is considered. The voltage becomes undefined, and a through current flows through the level shifter circuit from its high potential power supply.

In order to solve this problem, a switch transistor is provided in a differential circuit section for converting a signal to a high voltage of a voltage conversion circuit in advance, and the switch transistor is turned on or off in synchronization with control of a low voltage power supply. By fixing the signal of the differential circuit section, and simultaneously fixing the output state to a desired signal level by a pull-up transistor or a pull-down transistor provided at the output terminal, a switch is provided in the voltage conversion circuit. This has been realized by providing a transistor and using a transistor having a small off-leakage current as a transistor to be turned off in a voltage conversion circuit which outputs a desired circuit when the low-voltage operation circuit is not operating.

However, in the conventional configuration circuit, in order to generate a desired fixed output when the power supply to the low-voltage operation circuit or the low-voltage operation semiconductor device is cut off when the low-voltage operation circuit is not operating, a predetermined fixed output is required. After the desired fixed output is determined, the circuit layout must be performed by selecting either the level shifter circuit shown in FIG. 4 or FIG. 5. If the product specification is changed after the product is completed, the circuit layout is again performed. Has to be redone, and there is a problem that a large amount of time loss is required for re-leading out.

The present invention solves the above-mentioned conventional problems. Even when the product specifications are changed after the product is completed, the output voltage from the circuit is changed to a desired fixed output according to the product specifications. By doing so, there is no need to re-layout the circuit, and a level shifter circuit capable of eliminating a large time loss caused by re-readout is provided.

[0021]

In order to solve the above-mentioned problems, a level shifter circuit according to the present invention is provided in synchronism with a differential circuit section for converting a signal to a high voltage of a voltage conversion circuit and control of a low voltage power supply. By providing a control terminal for turning on or off the switch transistor and a switch transistor for fixing a signal of the differential circuit portion, a pull-up transistor and a pull-down transistor for fixing a desired signal level to an output terminal, and a latch circuit By eliminating the through current flowing through the circuit when the input signal voltage becomes unstable, the output voltage from the circuit is fixed even when the input signal voltage is unstable, and immediately before the low-voltage power supply is turned off. Determine the desired fixed output depending on the input signal of
The fixed output is provided by a latch circuit provided at the output terminal.
By continuing to hold even after turning off the low-voltage power supply,
Even after the product is completed, if the low-voltage power supply is turned off at the timing of inputting an input signal having the same phase as the desired fixed output, the output is changed to the desired fixed output.

As described above, even when the product specifications are changed after the product is completed, the output voltage from the circuit is changed to a desired fixed output in accordance with the product specifications, thereby eliminating the need for circuit re-layout. In addition, it is possible to eliminate a great amount of time loss caused by the re-readout.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A level shifter circuit according to a first aspect of the present invention is a circuit comprising a plurality of MOS transistors, a first shifter having a voltage difference between a first power supply and a second power supply as an amplitude. And a signal having an opposite phase to the signal from the input terminal and a voltage difference between a third power supply and the second power supply, and the input thereof controls the operation state of the circuit including the MOS transistor. A signal from an input terminal is input, and a desired level-shifted signal is output from an output terminal connected via a latch circuit including a plurality of inverters operating at a high voltage, and On the other hand, a voltage difference between the third power supply and the second power supply is used as an amplitude, and a signal from a third input terminal for controlling a latch operation of the latch circuit is input by the input, and the second Entering By the said MOS transistors operate the circuit consisting of the state by inputting the third voltage of the power supply to the terminal, during the circuit operation, for inputting the third voltage of the power supply to the third input terminal,
A signal having an amplitude of the second power supply voltage from the voltage of the third power supply and having the same phase as the signal from the first input terminal is output from the output terminal. At the same time, the first signal is supplied to the latch circuit. By holding a signal in phase with the signal from the input terminal and inputting the voltage of the second power supply to the second input terminal, the circuit composed of the MOS transistor is made inactive, and when this circuit is inactive, When the supply of the first power supply is cut off by inputting the voltage of the third power supply to the third input terminal, the signal of the output terminal is also cut off by the supply of the first power supply. The power supply voltage level depends on a signal from the immediately preceding first input terminal.

According to a second aspect of the present invention, there is provided a level shifter circuit having a first voltage having a voltage of a second power supply as an amplitude from a voltage of a first power supply.
At the gate of the first N-channel MOS transistor, and a signal having the opposite phase to the signal from the first input terminal is supplied to the second N-channel MOS transistor.
The gate of the S transistor receives the drain of the second N-channel MOS transistor and the first P-channel MO
Connected to the gate of the S transistor and the drain of the second P-channel MOS transistor;
The gate of the OS transistor and the first P-channel MO
Drain of S transistor and third N-channel M
A source of the OS transistor and a drain of the third P-channel MOS transistor are connected to an output terminal via a latch circuit including a third inverter operating at a high voltage and a fourth inverter operating at a high voltage, and The output terminal is connected to the drain of the third N-channel MOS transistor and the source of the third P-channel MOS transistor via the latch circuit, thereby connecting the fourth N-channel MOS transistor and the fourth P-channel MOS transistor. Connect the second input terminal to the gate of the MOS transistor,
A circuit is operated by connecting a third input terminal to the gates of the third N-channel MOS transistor and the third P-channel MOS transistor and inputting a third power supply voltage to the second input terminal. In this circuit operation, by inputting the voltage of the third power supply to the third input terminal during the circuit operation, the signal having the amplitude of the second power supply voltage from the voltage of the third power supply is used as the signal of the third power supply. A signal having the same phase as the signal from the first input terminal is output from the output terminal, a signal having the same phase as the signal from the first input terminal is held in the latch circuit, and the second input terminal is connected to the second input terminal. 2, the circuit is deactivated by inputting the voltage of the first power supply, and when the circuit is not operating, the voltage of the third power supply is input to the third input terminal to thereby supply the first power supply. Cut Even if the signal of the output terminal,
The power supply voltage level depends on a signal from the first input terminal immediately before the supply of the first power supply is cut off.

According to a third aspect of the present invention, in the level shifter circuit, a signal from a first input terminal having an amplitude of a voltage difference between a first power supply and a second power supply is supplied to a circuit including a plurality of MOS transistors. A signal having the opposite phase and a signal from a second input terminal for controlling an operation state of a circuit including the MOS transistor based on the voltage difference between a third power supply and the second power supply. And outputs a desired signal whose level has been shifted from an output terminal connected through a latch circuit composed of a plurality of inverters operating at a high voltage. A voltage difference between a power supply and the second power supply is defined as an amplitude, and a signal from a third input terminal for controlling a latch operation of the latch circuit by an input thereof is output to the output terminal via an exclusive OR circuit. A signal from a fourth input terminal for switching and controlling the polarity of these signals is input, and the voltage of the third power supply is input to the second input terminal, whereby the circuit composed of the MOS transistor is brought into an operating state. age,
At the time of this circuit operation, the voltage of the third power supply is input to the third input terminal, whereby the signal having the amplitude of the second power supply voltage from the voltage of the third power supply is used as the first input. A signal having the same phase as the signal from the terminal is output from the output terminal. At the same time, a signal having the same phase as the signal from the first input terminal is held in the latch circuit, and the second power supply is supplied to the second input terminal. By inputting the voltage of
When the circuit including the S transistor is in a non-operating state, and when the circuit is not operating, the voltage of the third power supply is input to the third input terminal, so that the supply of the first power is cut off. , The signal at the output terminal is fixed to a power supply voltage level depending on a signal from the first input terminal immediately before the supply of the first power is cut off, and the output terminal is fixed by the exclusive OR circuit. Is configured to be switchable between the normal phase and the negative phase with respect to the polarity of the signal of.

According to a fourth aspect of the present invention, in the level shifter circuit according to the first aspect, the voltage of the first power supply is changed from the voltage of the second power supply to the first power supply.
At the gate of the first N-channel MOS transistor, and a signal having the opposite phase to the signal from the first input terminal is supplied to the second N-channel MOS transistor.
The gate of the S transistor receives the drain of the second N-channel MOS transistor and the first P-channel MO
Connected to the gate of the S transistor and the drain of the second P-channel MOS transistor;
The gate of the OS transistor and the first P-channel MO
Drain of S transistor and third N-channel M
A source of the OS transistor and a drain of the third P-channel MOS transistor are connected to an output terminal via a latch circuit including a third inverter operating at a high voltage and a fourth inverter operating at a high voltage, and The output terminal is connected to the drain of the third N-channel MOS transistor and the source of the third P-channel MOS transistor via an exclusive OR circuit having the latch circuit and a fourth input terminal, Fourth N-channel MOS
A second input terminal connected to the gates of the transistor and the fourth P-channel MOS transistor;
A third input terminal is connected to the gates of the N-channel MOS transistor and the third P-channel MOS transistor, and a voltage of a third power supply is input to the second input terminal to make the circuit operative; During this circuit operation,
By inputting the voltage of the third power supply to the third input terminal, a signal having an amplitude of the second power supply voltage from the voltage of the third power supply is used as a signal from the first input terminal. An in-phase signal is output from the output terminal, and at the same time, a signal in phase with the signal from the first input terminal is held in the latch circuit, and a voltage of the second power supply is input to the second input terminal. In this case, the circuit is brought into a non-operating state. When the circuit is not operated, the voltage of the third power supply is inputted to the third input terminal, so that the supply of the first power is cut off. A signal at the output terminal is fixed to a power supply voltage level depending on a signal from the first input terminal immediately before the supply of the first power is cut off, and further, the signal at the output terminal is controlled by the exclusive OR circuit. Positive and negative for the polarity of Configured to Rikae controllable.

According to these configurations, by eliminating a through current flowing through the circuit when the input signal voltage becomes unstable, the output voltage from the circuit is fixed even when the input signal voltage is unstable, Determining a desired fixed output depending on an input signal immediately before turning off the low-voltage power supply, and keeping the fixed output by a latch circuit provided at an output terminal even after the low-voltage power supply is turned off. Thus, even after the product is completed, if the low-voltage power supply is turned off at the timing of inputting an input signal having the same phase as the desired fixed output, the desired fixed output is changed.

Hereinafter, a level shifter circuit according to an embodiment of the present invention will be specifically described with reference to the drawings. (Embodiment 1) A level shifter circuit according to Embodiment 1 of the present invention will be described. FIG. 1 is a circuit diagram showing a configuration of the level shifter circuit according to the first embodiment. In FIG. 1, A is a first input terminal, B is an output terminal, C is a second input terminal, D
Is a third input terminal, TP1 is a first P-channel MOS transistor, TP2 is a second P-channel MOS transistor, TP3 is a third P-channel MOS transistor,
TP4 is a fourth P-channel MOS transistor, TN1
Is the first N-channel MOS transistor, and TN2 is the second
, TN3 is a third N-channel MOS transistor, TN4 is a fourth N-channel MOS transistor, I1 is a first inverter of low voltage operation, I2 is a second inverter of low voltage operation, and I3 is The third inverter of the high voltage operation, I4 is the fourth inverter of the high voltage operation.
The inverter I5 is a fifth inverter operating at a high voltage,
I6 is a sixth inverter operated at a high voltage, I7 is a seventh inverter operated at a high voltage, I8 is an eighth inverter operated at a high voltage, R1 is a latch circuit, N1 is a first node, N2
Is a second node, and N3 is a third node.

The level shifter circuit according to the first embodiment includes a first
A signal from the first input terminal A having an amplitude of the voltage of the second power supply from the voltage of the second power supply is received at the gate of the first N-channel MOS transistor TN1, and the signal from the first input terminal A is inverted. The phase signal is received at the gate of the second N-channel MOS transistor TN2, and the drain of the second N-channel MOS transistor TN2 is connected to the gate of the first P-channel MOS transistor TP1 and the second P-channel MOS transistor TP2. Connected to the drain, the second
Of the P-channel MOS transistor TP2 and the first
Of the P-channel MOS transistor TP1, the source of the third N-channel MOS transistor TN3, and the drain of the third P-channel MOS transistor TP3 are connected to the third inverter I3 for high voltage operation and the fourth inverter for high voltage operation. Latch circuit R composed of inverter I4
1 via a latch circuit R1 and a third N-channel MOS transistor from the output terminal B via a latch circuit R1.
The drain of the transistor TN3 and the third P-channel MO
Connected to the source of S transistor TP3.

Fourth N-channel MOS transistor TN
4 and the gate of the fourth P-channel MOS transistor TP4 are connected to the second input terminal C.
During operation of the circuit, a third power supply voltage is input so that the second power supply voltage has an amplitude from the third power supply voltage, and a signal having the same phase as the signal from the first input terminal A is output from the output terminal B. When the circuit is not operating, the second power supply voltage is input.

Further, a third N-channel MOS transistor TN3 and a third P-channel MOS transistor TP3
A third input terminal D is connected to the gate of the third input terminal D, and a third power supply voltage is input to the third input terminal D during circuit operation, so that the second power supply voltage is changed from the third power supply voltage to an amplitude, A signal having the same phase as the signal from the first input terminal A is output from the output terminal B, and at the same time, the first signal is supplied to the latch circuit R1.
The signal in the same phase as the signal from the input terminal A is held. When the first power supply is turned off by inputting the second power supply voltage when the circuit is not operating, the signal at the output terminal B is output to the first input terminal immediately before the first power supply is turned off. A
The power supply voltage level depends on the signal from the power supply.

The operation of the level shifter circuit configured as described above will be described below. As an operation example,
The case where a signal having a low voltage amplitude of 0 V to 2 V is input to a logic circuit block operating at an amplitude voltage of 0 V to 3 V will be described as an example. In the active state, first, when the voltage of the low-voltage amplitude signal A is 2V, the first operating at the 2V voltage
The output of the inverter I1 is 0V, and the output of the second inverter I2 operating at the voltage of 2V is 2V. Also,
At that time, the first N-channel MOS transistor TN1
Is turned on by the output of the second inverter I2, and the second N-channel MOS transistor TN2 is turned off by the output of the first inverter I1.

When active, 3V is applied to the second input terminal C.
, And a fourth N-channel MOS transistor TN4 and a fourth P-channel MOS transistor TP4
Is on. At this time, the second node N2 is at 3V, which is the same potential as the potential of the 3V power supply V1, the first P-channel MOS transistor TP1 is off, and the first node N1 and the third node N3 are at 0V. And the second P-channel MOS transistor TP2 is on.

When active, 3V is input to the third input terminal D, and both the third P-channel MOS transistor TP3 and the third N-channel MOS transistor TN3 are off. At this time, an input signal from the output terminal B to the external high-voltage amplitude operation circuit is output as 3 V through the third inverter I3 operating at a high voltage.
At the same time, the output of the fourth inverter operating at high voltage is 0V.

When the voltage of the low-voltage amplitude signal at the first input terminal A changes from 2V to 0V, the output of the first inverter I1 changes from 0V to 2V, and the output of the second inverter I2 changes from 2V to 0V. Changes to Thereby, the first N
The channel MOS transistor TN1 shifts from on to off. Further, the second N-channel MOS transistor TN2 shifts from off to on. When both N-channel MOS transistors TN1 and TN2 shift to the ON state, the potential of the second node N2 drops,
The first P-channel MOS transistor TP1 turns on.

At this time, since the first N-channel MOS transistor TN1 has been turned off, the potentials of the first node N1 and the third node N3 rise.
In these operations, the first node N1 is completely at the same potential as the power supply V1 at 3V, the second node N2 is at 0V,
The process ends when the potential of the output terminal B becomes 0 V by the third inverter. When the voltage of the low-voltage amplitude signal at the first input terminal A shifts from 0 V to 2 V, the reverse operation is performed, and 3 V is output to the output terminal B.

When shifting from the active state to the sleep state, first, the third terminal, which is the control terminal of the level shifter circuit,
Is input to the input terminal D of the third P-channel MOS transistor TP3 and the third N-channel M
The OS transistor TN3 is turned on, and 3 V is fixedly output to the output terminal B from the output of the fourth inverter I4 operating at high voltage via the third inverter I3 operating at high voltage. Next, 0 V is input to the second input terminal C, and the fourth P-channel MOS transistor TP4 and the fourth N-channel MOS transistor TN4 are turned off. When returning from sleep to active, after setting the voltage of the low-voltage amplitude signal of the first input terminal A, first, 3 V is input to the second input terminal C, and then 3 V is input to the third input terminal D. To return to the normal operation.

As described above, according to the present embodiment, by providing the latch circuit R1, the second input terminal C, and the third input terminal D, a desired fixed output can be freely made dependent on an input signal. Fixed output can be selected. When the specification of the product is changed, an input signal having the same phase as the desired fixed output signal is input to the first input terminal A, and the state shifts to the sleep state at the timing stored in the latch circuit R1. The output can be changed to a desired fixed output, and the time required for laying out the circuit again can be omitted.

Further, in consideration of the change, the conventional low voltage output fixed level shifter circuit and high voltage output fixed level shifter circuit need not be prepared in advance so that the chip area can be increased and selected, and can be realized with a small area. (Embodiment 2) A level shifter circuit according to Embodiment 2 of the present invention will be described.

FIG. 2 is a circuit diagram showing a configuration of the level shifter circuit according to the second embodiment. In FIG. 2, A is a first input terminal, B is an output terminal, C is a second input terminal, D is a third input terminal, TP1 is a first P-channel MOS transistor, and TP2 is a second P-channel. MOS transistor, TP3 is a third P-channel MOS transistor, T
P4 is a fourth P-channel MOS transistor, TN1 is a first N-channel MOS transistor, TN2 is a second N-channel MOS transistor, TN3 is a third N-channel MOS transistor, and TN4 is a fourth N-channel MOS transistor.
An OS transistor, I1 is a first inverter operated at a low voltage, I2 is a second inverter operated at a low voltage, I3 is a third inverter operated at a high voltage, I4 is a fourth inverter operated at a high voltage, and I5 is a high inverter Voltage-operated fifth inverter, I
Reference numeral 6 denotes a sixth inverter operating at a high voltage, I7 denotes a seventh inverter operating at a high voltage, I8 denotes an eighth inverter operating at a high voltage, R1 denotes a latch circuit, N1 denotes a first node, and N2 denotes a second inverter. The node N3 is a third node, which has the same configuration as that of FIG. 1 is different from FIG. 1 in that a fourth input terminal E and an exclusive OR circuit 1 are connected to the latch circuit R1.
And the drain of the third N-channel MOS transistor TN3 and the third P-channel MOS transistor TP3
And the source.

The operation of the level shifter circuit configured as described above will be described below. As an operation example,
The case where a signal having a low voltage amplitude of 0 V to 2 V is input to a logic circuit block operating at an amplitude voltage of 0 V to 3 V will be described as an example. In the active state, first, when the voltage of the low-voltage amplitude signal A is 2V, the first operating at the 2V voltage
The output of the inverter I1 is 0V, and the output of the second inverter I2 operating at the voltage of 2V is 2V. Also,
At that time, the first N-channel MOS transistor TN1
Is turned on by the output of the second inverter I2, and the second N-channel MOS transistor TN2 is turned off by the output of the first inverter I1.

When active, 3 V is applied to the second input terminal C.
, And a fourth N-channel MOS transistor TN4 and a fourth P-channel MOS transistor TP4
Is on. At this time, the second node N2 is at 3V, which is the same potential as the potential of the 3V power supply V1, the first P-channel MOS transistor TP1 is off, and the first node N1 and the third node N3 are at 0V. And the second P-channel MOS transistor TP2 is on.

When active, 3 V is input to the third input terminal D, and both the third P-channel MOS transistor TP3 and the third N-channel MOS transistor TN3 are off. At this time, an input signal from the output terminal B to the external high-voltage amplitude operation circuit is output as 3 V through the third inverter I3 operating at a high voltage.
At the same time, the output of the fourth inverter operating at high voltage is 0V.

When the voltage of the low voltage amplitude signal at the first input terminal A changes from 2V to 0V, the output of the first inverter I1 changes from 0V to 2V, and the output of the second inverter I2 changes from 2V to 0V. Changes to Thereby, the first N
The channel MOS transistor TN1 shifts from on to off. Further, the second N-channel MOS transistor TN2 shifts from off to on. When both N-channel MOS transistors TN1 and TN2 shift to the ON state, the potential of the second node N2 drops,
The first P-channel MOS transistor TP1 turns on.

At this time, since the first N-channel MOS transistor TN1 has been turned off, the potentials of the first node N1 and the third node N3 rise.
In these operations, the first node N1 is completely at the same potential as the power supply V1 at 3V, the second node N2 is at 0V,
The process ends when the potential of the output terminal B becomes 0 V by the third inverter. When the voltage of the low-voltage amplitude signal at the first input terminal A shifts from 0 V to 2 V, the reverse operation is performed, and 3 V is output to the output terminal B.

When shifting from the active state to the sleep state, first, the third terminal, which is the control terminal of the level shifter circuit,
Is input to the input terminal D of the third P-channel MOS transistor TP3 and the third N-channel M
The OS transistor TN3 is turned on, and 3 V is fixedly output to the output terminal B from the output of the fourth inverter I4 operating at high voltage via the third inverter I3 operating at high voltage. Next, 0 V is input to the second input terminal C, and the fourth P-channel MOS transistor TP4 and the fourth N-channel MOS transistor TN4 are turned off.

In the case where 3 V is output to the output terminal B in the sleep state, 0 V is output to the output of the fourth inverter I4 operating at a high voltage. Therefore, when it is desired to invert the fixed signal from the output terminal B, 3
When V is input, 3V is input to the input of the third inverter I3 operating at a high voltage via the exclusive OR circuit 1.
0 V is output from the output terminal B. Then, at the same time that 3V is output to the output of the fourth inverter I4,
0V is input to and held at the input terminal E of, and an inverted signal is continuously output. Similarly, in the sleep state, 0 is output from the output terminal B.
When V is output, when it is desired to invert the fixed signal from the output terminal B, when 3 V is input to the fourth input terminal E, the third high-voltage operation is performed via the exclusive OR circuit 1.
0V is input to the input of the inverter I3, and 3V is output from the output terminal B. After that, at the same time that 0 V is output to the output of the fourth inverter I4, 0 V is input to the fourth input terminal E and the output is kept, thereby continuously outputting the inverted signal. When not inverting, 0 V is applied to the fourth input terminal E.
Is entered.

When returning from sleep to active,
After setting the voltage of the low-voltage amplitude signal at the first input terminal A, first, 3 V is input to the second input terminal C, and then 3 V is input to the third input terminal D, whereby the normal operation is performed. Return. As described above, by providing the fourth input terminal E and the exclusive OR circuit 1 in the latch circuit R1, the low-voltage power supply is cut off, and the fixed output signal B depending on the low-voltage input signal A is output. In this case, the output signal B can be freely inverted.

The fourth input terminal E may be an internally generated signal instead of an external input signal to the input terminal as long as it can be controlled. Further, the exclusive OR circuit 1 does not have to have the configuration of FIG. 2 and may be an exclusive NOR circuit. Further, instead of the exclusive OR circuit 1, as shown in FIG. 3, a circuit that switches and outputs a positive-phase output and a negative-phase output of an output signal by a switch may be used.

[0050]

As described above, according to the present invention, when the input signal voltage becomes unstable, the through current flowing through the circuit is eliminated, so that even if the input signal voltage is unstable, the output from the circuit can be reduced. While fixing the voltage, determine a desired fixed output depending on the input signal immediately before turning off the low-voltage power supply,
The fixed output is provided by a latch circuit provided at the output terminal.
By continuing to hold even after turning off the low-voltage power supply,
Even after the product is completed, the desired fixed output can be changed to the desired fixed output by turning off the low-voltage power supply at the timing of inputting an input signal in phase with the desired fixed output.

Also, by providing one new control terminal in this circuit and providing an exclusive OR circuit in the latch circuit, the fixed output held and output after the low-voltage power supply is turned off can be changed to a desired voltage level. Can be changed to Therefore, even if the product specifications are changed after the product is completed, by changing the output voltage from this circuit to the desired fixed output in accordance with the product specifications, there is no need to re-layout the circuit, and The enormous time loss that has occurred due to the lead-out can be eliminated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a level shifter circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a level shifter circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing another configuration of the level shifter circuit according to the second embodiment;

FIG. 4 is a circuit diagram showing a configuration of a conventional level shifter circuit

FIG. 5 is a circuit diagram showing another configuration of a conventional level shifter circuit.

[Explanation of symbols]

 A input terminal (low voltage amplitude signal) B output terminal (high voltage amplitude signal) C input terminal (control terminal) D input terminal (control terminal) E input terminal (control terminal) I1 low voltage amplitude inverter I2 low voltage amplitude inverter I3 High voltage swing inverter I4 High voltage swing inverter I5 High voltage swing inverter I6 High voltage swing inverter I7 High voltage swing inverter I8 High voltage swing inverter TP1 P channel MOS transistor TP2 P channel MOS transistor TP3 P channel MOS transistor TP4 P channel MOS transistor TN1 N-channel MOS transistor TN2 N-channel MOS transistor TN3 N-channel MOS transistor TN4 N-channel MOS transistor N1 node N2 node N3 node R1 Latch circuit 1 Other-OR circuits 2 switch circuit

Claims (4)

[Claims] 1. A circuit comprising a plurality of MOS transistors, a signal having a voltage difference between a first power supply and a second power supply from a first input terminal and a signal having the opposite phase, The voltage difference between the third power supply and the second power supply is set as an amplitude, and a signal from a second input terminal for controlling an operation state of a circuit including the MOS transistor is input by the input, and a high voltage operation is performed. A desired level-shifted signal is output from an output terminal connected via a latch circuit composed of a plurality of inverters, and the third power supply and the second power supply are supplied to the latch circuit. By inputting a signal from a third input terminal for controlling a latch operation of the latch circuit by the input, and inputting a voltage of the third power supply to the second input terminal. Said A circuit composed of MOS transistors is brought into an operating state. During this circuit operation, the voltage of the third power supply is inputted to the third input terminal,
A signal having an amplitude of the second power supply voltage from the voltage of the third power supply and having the same phase as the signal from the first input terminal is output from the output terminal. At the same time, the first signal is supplied to the latch circuit. By holding a signal in phase with the signal from the input terminal and inputting the voltage of the second power supply to the second input terminal, the circuit composed of the MOS transistor is made inactive, and when this circuit is inactive, When the supply of the first power supply is cut off by inputting the voltage of the third power supply to the third input terminal, the signal of the output terminal is also cut off by the supply of the first power supply. A level shifter circuit characterized in that it is configured to be fixed at a power supply voltage level depending on a signal from the immediately preceding first input terminal. 2. A gate of a first N-channel MOS transistor receiving a signal from a first input terminal having an amplitude from a voltage of a first power supply to a voltage of a second power supply,
A signal having a phase opposite to that of the signal from the first input terminal is converted to a second signal.
And the drain of the second N-channel MOS transistor is connected to the first N-channel MOS transistor.
Connected to the gate of the second P-channel MOS transistor and the drain of the second P-channel MOS transistor.
Of the third P-channel MOS transistor, the source of the third N-channel MOS transistor and the third P-channel MOS transistor.
Connecting the drain of the channel MOS transistor to an output terminal via a latch circuit composed of a third inverter operating at a high voltage and a fourth inverter operating at a high voltage;
The output terminal is connected to the drain of the third N-channel MOS transistor and the source of the third P-channel MOS transistor via the latch circuit, thereby connecting the fourth N-channel MOS transistor and the fourth P-channel MOS transistor. The second input terminal is connected to the gate of the channel MOS transistor, and the third input terminal is connected to the gates of the third N-channel MOS transistor and the third P-channel MOS transistor. The circuit is activated by inputting the voltage of the third power supply to the terminal, and during this circuit operation, by inputting the voltage of the third power supply to the third input terminal, A signal having the same amplitude as the signal from the first input terminal is output from the output terminal with a signal having an amplitude of the second power supply voltage from the voltage, and Holding the signal in phase with the signal from the first input terminal in the latch circuit, and inputting the voltage of the second power supply to the second input terminal to make the circuit inactive, When not operating, the third
Even when the supply of the first power supply is cut off by inputting the voltage of the third power supply to the input terminal of, the signal of the output terminal is changed to the signal immediately before the supply of the first power supply is cut off. A level shifter circuit comprising a power supply voltage level dependent on a signal from a first input terminal. 3. A circuit comprising a plurality of MOS transistors, a signal from a first input terminal having an amplitude equal to a voltage difference between a first power supply and a second power supply, and a signal having an opposite phase to the first input terminal. The voltage difference between the third power supply and the second power supply is set as an amplitude, and a signal from a second input terminal for controlling an operation state of a circuit including the MOS transistor is input by the input, and a high voltage operation is performed. A desired level-shifted signal is output from an output terminal connected via a latch circuit composed of a plurality of inverters, and the third power supply and the second power supply are supplied to the latch circuit. A signal from a third input terminal for controlling the latch operation of the latch circuit by its input,
Inputting a signal from a fourth input terminal for switching and controlling the polarity of the signal from the output terminal via an exclusive OR circuit, and inputting the voltage of the third power supply to the second input terminal Puts the circuit composed of the MOS transistors into an operating state, and during this circuit operation, by inputting the voltage of the third power supply to the third input terminal, the voltage of the third power supply is changed to the second power supply. A signal having the same amplitude as that of the signal from the first input terminal is output from the output terminal as a signal having an amplitude of a voltage, and the latch circuit simultaneously holds the signal in phase with the signal from the first input terminal, By inputting the voltage of the second power supply to the second input terminal, the circuit composed of the MOS transistors is made inoperative, and when the circuit is not operating, the third input terminal is connected to the third input terminal. When the supply of the first power is cut off by inputting a voltage, the signal of the output terminal depends on the signal from the first input terminal immediately before the supply of the first power is cut off. A level shifter circuit, wherein the power supply voltage level is fixed to the power supply voltage level, and the exclusive OR circuit is configured to be able to control switching between a positive phase and a negative phase with respect to the polarity of the signal at the output terminal. 4. A signal from a first input terminal having an amplitude of a voltage of a second power supply from a voltage of a first power supply is received by a gate of a first N-channel MOS transistor.
A signal having a phase opposite to that of the signal from the first input terminal is converted to a second signal.
And the drain of the second N-channel MOS transistor is connected to the first N-channel MOS transistor.
Connected to the gate of the second P-channel MOS transistor and the drain of the second P-channel MOS transistor.
Of the third P-channel MOS transistor, the source of the third N-channel MOS transistor and the third P-channel MOS transistor.
Connecting the drain of the channel MOS transistor to an output terminal via a latch circuit composed of a third inverter operating at a high voltage and a fourth inverter operating at a high voltage;
And from the output terminal thereof through the exclusive OR circuit having the latch circuit and the fourth input terminal, the third N
The drain of the channel MOS transistor and the third P
A fourth N-channel MOS transistor and a fourth P-channel MO
A second input terminal is connected to the gate of the S transistor, and a third input terminal is connected to the gates of the third N-channel MOS transistor and the third P-channel MOS transistor.
And inputting a voltage of a third power supply to the second input terminal to bring the circuit into an operating state. During this circuit operation, the voltage of the third power supply is applied to the third input terminal. To output from the output terminal a signal having an amplitude of the second power supply voltage from the voltage of the third power supply and having the same phase as the signal from the first input terminal. The circuit holds a signal in phase with the signal from the first input terminal and inputs the voltage of the second power supply to the second input terminal to make the circuit inactive, and when the circuit is inactive, When the supply of the first power is cut off by inputting the voltage of the third power to the third input terminal, the signal of the output terminal is supplied to the third input terminal. Signal from the first input terminal immediately before disconnection Fixed-dependent power supply voltage level,
A level shifter circuit, wherein the exclusive OR circuit is configured to be able to control switching between a positive phase and a negative phase with respect to the polarity of the signal at the output terminal.