JP2001035191A - Verifying pattern generating device, verifying pattern generating method, and medium in which verifying pattern generating program is recorded - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a verifying pattern generating device which can generate automatically a verifying pattern used in logic verifying and timing verifying of a memory. SOLUTION: A verifying pattern generating device comprises a basic verifying pattern storing section 21 storing a basic verifying pattern being a verifying pattern of the prescribed time for each kind of memories to be verified, an address generating section 23 generating an address of a memory, and a verifying pattern generating section 25 reading out a basic verifying pattern from the basic verifying pattern storing section 21, setting an address and input/output data generated by the address generating section 23 to a basic verifying pattern, and generating a verifying pattern. As the verifying pattern generating section 25 sets an address and input/output data to a basic verifying pattern and generates a verifying pattern, a verifying pattern can be automatically generated, and a verifying pattern having no omission can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for generating a verification pattern used in logic verification and timing verification of a memory, and more particularly, to a verification pattern for automatically generating an input / output pattern according to a memory type and a verification condition. The present invention relates to a generation device, a verification pattern generation method, and a medium recording a verification pattern generation program.

[0002]

2. Description of the Related Art Conventionally, a verifier manually creates a verification pattern used in logic verification and timing verification of a memory based on the specifications of the memory.

[0003]

However, there is a problem that it takes a lot of time to manually create verification patterns for all memory cells and operation modes. Therefore, the time required for creating a verification pattern has been reduced by performing verification by limiting the bank and address to be verified under each verification condition. Therefore, the logic and the timing of all the memory cells and the operation modes cannot be verified, and there is a problem that a logic and a timing failure cannot be detected in the logic verification and the timing verification of the memory.

The present invention has been made to solve the above problems, and a first object of the present invention is to provide a verification pattern capable of automatically generating a verification pattern used in logic verification and timing verification of a memory. It is to provide a generating device.

[0005] A second object is to provide a verification pattern generation device capable of generating a verification pattern without omission.

A third object is to provide a verification pattern generation method capable of automatically generating a verification pattern used in logic verification and timing verification of a memory.

A fourth object is to provide a verification pattern generation method capable of generating a verification pattern without omission.

A fifth object is to provide a medium on which a verification pattern generation program capable of automatically generating a verification pattern used in logic verification and timing verification of a memory is recorded.

A sixth object is to provide a medium in which a verification pattern generation program capable of creating a verification pattern without omission is recorded.

[0010]

According to a first aspect of the present invention, there is provided a verification pattern generating apparatus, wherein a plurality of operation command information corresponding to a type of a memory, and a plurality of operation command information defined according to the operation command information are provided to a control terminal of the memory. Storage means for storing control signal pattern information to be stored, an address generation means for generating an address of a memory, and read control signal pattern information from the storage means in accordance with the operation command information, and generate an address in the control signal pattern information Verification pattern generation means for generating a verification pattern by setting an address and input / output data generated by the means.

The verification pattern generation means reads the control signal pattern information from the storage means in accordance with the operation command information, and sets the address and the input / output data generated by the address generation means in the control signal pattern information to convert the verification pattern. Since it is generated, the verification pattern can be automatically generated, and a verification pattern without omission can be created.

According to a second aspect of the present invention, there is provided the verification pattern generating apparatus according to the first aspect, wherein the verification pattern generating apparatus further includes bank value generating means for generating a bank value. The pattern generation means
The control signal pattern information is read from the storage unit in accordance with the operation command information, and the control signal pattern information is set with the address generated by the address generation unit, the bank value generated by the bank value generation unit, and the input / output data for verification. Generate a pattern.

The verification pattern generation means reads control signal pattern information from the storage means in accordance with the operation command information, and stores the address generated by the address generation means and the bank value generated by the bank value generation means in the control signal pattern information. Since the verification pattern is generated by setting the input / output data and the input / output data, it is possible to generate the verification pattern for each bank in addition to the effect of the verification pattern generation device according to the first aspect.

According to a third aspect of the present invention, there is provided a verification pattern generating method, comprising: a plurality of operation command information corresponding to a type of a memory;
Storing control signal pattern information defined according to the operation command information and given to a control terminal of the memory, and generating an address of the memory;
Reading the stored control signal pattern information in response to the operation command information, and setting an address and input / output data generated in the control signal pattern information to generate a verification pattern.

According to the operation command information, the stored control signal pattern information is read, and the generated address and input / output data are set to generate the verification pattern. Therefore, the verification pattern can be automatically generated. It is possible to create a verification pattern without omission.

A verification pattern generation method according to a fourth aspect is the verification pattern generation method according to the third aspect, wherein the verification pattern generation method further includes a step of generating a bank value, and a step of generating a verification pattern. Reads the stored control signal pattern information according to the operation command information, and sets an address generated in the control signal pattern information, a generated bank value, and input / output data to generate a verification pattern.

According to the operation command information, the stored control signal pattern information is read, and the generated address,
Since the verification pattern is generated by setting the generated bank value and input / output data, it is possible to generate the verification pattern for each bank in addition to the effect of the verification pattern generation method according to the third aspect.

A verification pattern generation program recorded on a computer-readable recording medium according to claim 5 includes a plurality of operation command information corresponding to a type of a memory;
Storing control signal pattern information defined according to the operation command information and given to a control terminal of the memory, and generating an address of the memory;
Reading the stored control signal pattern information in response to the operation command information, and setting an address and input / output data generated in the control signal pattern information to generate a verification pattern.

According to the operation command information, the stored control signal pattern information is read, and the generated address and input / output data are set to generate the verification pattern. Therefore, the verification pattern can be automatically generated. It is possible to create a verification pattern without omission.

A verification pattern generation program recorded on a computer-readable recording medium according to claim 6 is the verification pattern generation program according to claim 5, wherein the verification pattern generation program further generates a bank value. The step of generating a verification pattern includes reading the stored control signal pattern information according to the operation command information, and setting the generated address, the generated bank value, and the input / output data in the control signal pattern information. To generate a verification pattern.

In accordance with the operation command information, the stored control signal pattern information is read, and the generated address,
Since the verification pattern is generated by setting the generated bank value and input / output data, the verification pattern can be generated for each bank in addition to the effect of the verification pattern generation program according to the fifth aspect.

[0022]

FIG. 1 is a diagram showing an example of the external appearance of a verification pattern generation device according to the present invention. The verification pattern generation device includes a computer main body 1, a graphic display device 2, a magnetic tape device 3 on which a magnetic tape 4 is mounted, a keyboard 5, a mouse 6, a CD-ROM (Compact Disc-
A read-only memory (CD) 8 includes a CD-ROM device 7 and a communication modem 9. The verification pattern generation program is supplied by a storage medium such as the magnetic tape 4 or the CD-ROM 8. The verification pattern generation program is executed by the computer main body 1, and the operator generates a verification pattern by operating the keyboard 5 or the mouse 6 while watching the graphic display device 2. The verification pattern generation program may be supplied to the computer main body 1 from another computer via a communication line and a communication modem 9.

FIG. 2 is a block diagram showing a configuration example of the verification pattern generation device of the present invention. The computer main body 1 shown in FIG. 1 has a CPU 10 and a ROM (Read Only Memory).
y) 11, a RAM (Random Access Memory) 12, and a hard disk 13. The CPU 10 includes a graphic display device 2, a magnetic tape device 3, a keyboard 5, a mouse 6, a CD-ROM device 7, a communication modem 9,
The processing is performed while inputting / outputting data to / from the OM 11, the RAM 12, or the hard disk 13. The verification pattern generation program recorded on the magnetic tape 4 or the CD-ROM 8 is transmitted to the magnetic tape device 3 or C by the CPU 10.
The data is temporarily stored in the hard disk 13 via the D-ROM device 7. The CPU 10 generates a verification pattern by appropriately loading the verification pattern generation program from the hard disk 13 into the RAM 12 and executing the program.

FIG. 3 is a block diagram showing a schematic functional configuration of the verification pattern generation device according to the embodiment of the present invention. This verification pattern generation device includes a basic verification pattern storage unit 21 for storing a basic verification pattern, a verification condition input unit 22 for inputting a verification condition, and an address generation unit for generating a memory address used when generating a verification pattern. Unit 23, a bank value generation unit 24 that generates a bank value used when generating a verification pattern, a basic verification pattern stored in a basic verification pattern storage unit 21, and a verification input to a verification condition input unit 22. A verification pattern generation unit 25 that generates a verification pattern based on the condition, the address generated by the address generation unit 23, and the bank value generated by the bank value generation unit 24; and a verification pattern generated by the verification pattern generation unit 25. And a verification pattern storage unit 26 to be stored.

The verification condition input unit 22 includes a type of memory to be verified, a memory capacity, a first command, a second command, a bank initial value, a bank end value, a first column address initial value, and a first column address end. Verification conditions such as a value, a second column address initial value, and a second column address end value are input.

The first command and the second command refer to any of commands such as READ, WRITE and NO-OPERATION defined by the type of memory. Here, a READ command is a command instructing generation of a memory read cycle verification pattern, a WRITE command is a command instructing generation of a memory write cycle verification pattern, and a NO-OPERATION command. Is D-RAM
Like a burst mode of a (dynamic RAM), each command indicates a command for generating a verification pattern of a cycle in which data input / output is performed without generating a normal read cycle or write cycle.

In the basic verification pattern storage unit 21, a verification pattern corresponding to a command defined by the type of memory to be verified is stored in advance. For example, the memory type is D-RAM and the command is a READ command. If so, the verification pattern of one read cycle corresponding to the READ command of the D-RAM is stored in advance.

FIGS. 4 and 5 are flowcharts for explaining the processing procedure of the verification pattern generation device according to the present embodiment. In the following description, for simplicity, the row address is fixed and only the column address is changed to generate the verification pattern. However, by changing the row address appropriately and generating the verification pattern, all the memory patterns are generated. It is possible to generate a cell verification pattern.

First, the verifier inputs the verification condition input unit 22
The verification condition is input to (S1). The verification pattern generation unit 25 generates an initialization pattern so that the verification pattern generated in step S3 and subsequent steps can be input (step S3).
2). For example, if it is a D-RAM, RAS (Row Add
ress Strobe) signal and CAS (Column Address Strob)
e) Deactivate the signal and the like, and set a state where a verification pattern can be generated in step S3 and subsequent steps.

Next, the address generator 23 initializes the first column address value and the second column address value, and the bank value generator 24 initializes the first bank value and the second bank value (S3). Then, the verification pattern generation unit 25
Reads the basic verification pattern corresponding to the first command from the basic verification pattern storage unit 21 in accordance with the type of memory specified by the verification conditions, and reads the first bank value, the first column address value, and the By confirming the input / output data, a verification pattern for one cycle is generated and stored in the verification pattern storage unit 26 (S
4).

Next, it is determined whether a command accompanying the first command is necessary (S5). The command accompanying the first command refers to, for example, a command for instructing generation of the second and subsequent cycles when data is read in the burst mode of the D-RAM.
The O-OPERATION command corresponds to this.

If a command accompanying the first command is necessary (S5, Yes), the verification pattern generation unit 25 reads a basic verification pattern corresponding to the command accompanying the first command from the basic verification pattern storage unit 21, and By confirming the input / output data of the basic verification pattern, a verification pattern of a cycle accompanying the cycle specified by the first command is generated and stored in the verification pattern storage unit 26 (S6), and the process proceeds to step S7. Also,
When a command accompanying the first command is not required (S
5, No), and proceed directly to step S7.

In step S7, the verification pattern generation unit 25 reads a basic verification pattern corresponding to the second command from the basic verification pattern storage unit 21 according to the type of memory specified by the verification conditions, and reads the basic verification pattern. By determining the second bank value, the second column address value, and the input / output data, a verification pattern for one cycle is generated and stored in the verification pattern storage unit 26 (S7).

Next, it is determined whether a command accompanying the second command is necessary (S8). If a command accompanying the second command is required (S8, Yes), the verification pattern generation unit 25 reads a basic verification pattern corresponding to the command accompanying the second command from the basic verification pattern storage unit 21, and performs the basic verification. By deciding the input / output data of the pattern, a verification pattern of a cycle accompanying the cycle specified by the second command is generated and stored in the verification pattern storage unit 26 (S9), and the process proceeds to step S10. If a command accompanying the second command is not required (S8, No), the process directly proceeds to step S10.

Next, the address generator 23 increments the second column address, and determines whether or not the second column address is equal to or less than the second column address end value (S10). If the second column address is equal to or less than the second column address end value (S10, Yes), step S4
Return to and repeat the subsequent processing. If the second column address is larger than the second column address end value (S1
0, No), and initialize the second column address value (S1).
1).

Next, the address generation unit 23 increments the first column address value and determines whether the first column address value is equal to or less than the first column address end value (S12). If the first column address value is equal to or smaller than the first column address end value (S12, Yes), the process returns to step S4 and the subsequent processes are repeated. If the first column address value is larger than the first column address end value (S12, No), the first column address value and the second column address value are initialized (S13).

Next, the bank value generator 24 increments the second bank value and determines whether or not the second bank value is equal to or less than the second bank end value (S14). If the second bank value is equal to or smaller than the second bank end value (S14, Ye
s), the process returns to step S4, and the subsequent processes are repeated. If the second bank value is larger than the second bank end value (S14, No), the second bank value is initialized (S1).
5).

Next, the bank value generator 24 increments the first bank value and determines whether or not the first bank value is equal to or less than the first bank end value (S16). If the first bank value is equal to or less than the first bank end value (S16, Ye
s), the process returns to step S4, and the subsequent processes are repeated. If the first bank value is larger than the first bank end value (S16, No), the process ends.

As described above, according to the verification pattern generation device of the present embodiment, a basic verification pattern is generated in advance for each type of memory, and the address value, bank value, and input / output data of the basic verification pattern are stored. Since the verification pattern is automatically generated while setting, the time required for generating the memory verification pattern can be significantly reduced, and a verification pattern without omission can be created.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0041]

According to the verification pattern generation device of the present invention, the verification pattern generation means reads the control signal pattern information from the storage means in accordance with the operation command information, and outputs the address generation means to the control signal pattern information. Since the verification pattern is generated by setting the address and the input / output data generated by the above, the verification pattern can be automatically generated, and the verification pattern without any omission can be created.

According to the verification pattern generation device of the present invention, the verification pattern generation means reads the control signal pattern information from the storage means in accordance with the operation command information and generates the control signal pattern information by the address generation means. The verification pattern is generated by setting the address, the bank value generated by the bank value generation means, and the input / output data, so that the verification pattern generation device according to claim 1 has an additional effect. Can also be generated.

According to the verification pattern generation method of the present invention, the stored control signal pattern information is read out according to the operation command information, and the generated address and input / output data are set to generate the verification pattern. So
A verification pattern can be automatically generated, and a verification pattern without omission can be created.

According to the verification pattern generation method, the stored control signal pattern information is read in accordance with the operation command information, and the generated address, the generated bank value, and the input / output data are set. Therefore, in addition to the effect of the verification pattern generation method according to the third aspect, generation of a verification pattern for each bank is also possible.

According to the verification pattern generation program recorded on the computer-readable recording medium according to the fifth aspect, the stored control signal pattern information is read out in accordance with the operation command information, and the generated address and input address are read. Since the verification pattern is generated by setting the output data, the verification pattern can be automatically generated, and the verification pattern without omission can be created.

According to the verification pattern generation program recorded on the computer-readable recording medium according to the present invention, the stored control signal pattern information is read out in accordance with the operation command information, and the generated address and the generated Since the verification pattern is generated by setting the obtained bank value and input / output data, it is possible to generate a verification pattern for each bank in addition to the effect of the verification pattern generation program according to the fifth aspect.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of an external appearance of a verification pattern generation device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a verification pattern generation device according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating a schematic configuration of a verification pattern generation device according to the embodiment of the present invention.

FIG. 4 is a flowchart (part 1) for describing a processing procedure of the verification pattern generation device according to the embodiment of the present invention.

FIG. 5 is a flowchart (part 2) for describing the processing procedure of the verification pattern generation device according to the embodiment of the present invention.

[Explanation of symbols]

1 Computer main body, 2 Graphic display device, 3 Magnetic tape device, 4 Magnetic tape, 5 Keyboard, 6 Mouse, 7 CD-ROM device, 8 CD
-ROM, 9 communication modem, 10 CPU, 11 RO
M, 12 RAM, 13 hard disk, 21 basic verification pattern storage unit, 22 verification condition input unit, 23 address generation unit, 24 bank value generation unit, 25 verification pattern generation unit, 26 verification pattern storage unit.

Claims (6)

[Claims] A storage unit for storing a plurality of operation command information corresponding to a type of a memory and control signal pattern information defined according to the operation command information and provided to a control terminal of the memory; An address generating means for generating an address of the memory; and a control signal pattern information read from the control signal pattern information storing means according to the operation command information, and the control signal pattern information is generated by the address generating means. A verification pattern generating device for generating a verification pattern by setting an address and input / output data. 2. The verification pattern generation device further includes a bank value generation unit for generating a bank value, wherein the verification pattern generation unit receives control signal pattern information from the storage unit in response to operation command information. 2. The verification pattern according to claim 1, wherein a verification pattern is generated by reading and setting an address generated by the address generation unit, a bank value generated by the bank value generation unit, and input / output data in the control signal pattern information. Generator. A step of storing a plurality of pieces of operation command information corresponding to a type of the memory, and control signal pattern information defined according to the operation command information and supplied to a control terminal of the memory; Generating an address; reading the stored control signal pattern information according to operation command information; and setting the generated address and input / output data in the control signal pattern information to generate a verification pattern. And a verification pattern generation method. 4. The method for generating a verification pattern further includes a step of generating a bank value, wherein the step of generating the verification pattern reads the stored control signal pattern information according to operation command information, 4. The verification pattern generation method according to claim 3, wherein a verification pattern is generated by setting the generated address, the generated bank value, and input / output data in control signal pattern information. 5. A step of storing a plurality of pieces of operation command information corresponding to a type of a memory, and control signal pattern information defined according to the operation command information and provided to a control terminal of the memory. Generating an address; reading the stored control signal pattern information according to operation command information; and setting the generated address and input / output data in the control signal pattern information to generate a verification pattern. And a computer-readable recording medium recording a verification pattern generation program including the following. 6. The verification pattern generation program further includes a step of generating a bank value, wherein the step of generating the verification pattern reads the stored control signal pattern information according to operation command information, 6. A computer-readable recording medium storing a verification pattern generation program according to claim 5, wherein a verification pattern is generated by setting the generated address, the generated bank value, and input / output data in control signal pattern information.