JP2001028548A - Device and method for error correction encoding, device and method for error correction decoding, information processor, radio communications equipment and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize plural types of error correction encoding algorithms or plural types of error correction decoding algorithms with a simple and also low-cost circuit configuration, without increasing circuit scale. SOLUTION: This error correction encoding circuit 500 is provided with a 1st encoding circuit 502 which performs error correction encoding of input data, an interleaver 501 for rearranging the input data into a prescribed order, and a 2nd encoding circuit 503 which performs error correction encoding of an output of the interleaver 501. Then, plural types of error correction encoding algorithms are realized, sharing the circuit 502.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction coding apparatus and method, an error correction decoding apparatus and method, an information processing apparatus, and a radio communication apparatus, and more particularly to a technique for correcting an error in digital information. It is.

[0002]

2. Description of the Related Art When digital information is received on a transmission line, or when digital information is reproduced from a recording medium such as a floppy (registered trademark) disk, compact disk, or magnetic tape, an error may occur in the digital information. is there.

One technique for preventing such digital information errors is an error correction technique. The error correction technology is a technology that applies redundant coding to digital information to be transmitted or recorded, and enables correct information restoration even when an error occurs in the digital information.

[0004]

Generally, there are a plurality of types of algorithms for realizing the error correction technique. These types include digital information types and their error characteristics, transmission line types and their error characteristics, recording media types and their errors. The selection was made according to characteristics and the like. Therefore, when configuring a system that selectively uses a plurality of error correction algorithms, it is necessary to separately provide an encoding circuit and a decoding circuit corresponding to each algorithm, increasing the circuit scale and increasing the cost. There was a problem.

[0005] From the above background, an object of the present invention is to realize a plurality of types of error correction coding algorithms or a plurality of types of error correction decoding algorithms with a simple and low-cost circuit configuration without increasing the circuit scale. It is an object of the present invention to provide an error correction encoding device and method, an error correction decoding device and method, an information processing device, and a wireless communication device.

[0006]

In order to achieve the above object, an error correction coding apparatus according to the present invention comprises: first coding means for performing error correction coding of input data; A rearranging unit for rearranging the data in a predetermined order; and a second encoding unit for error-correcting and encoding the output of the rearranging unit. Is realized by sharing.

[0007] The error correction encoding method of the present invention comprises the following steps:
A first encoding step of performing error correction encoding of input data using an encoding circuit, a reordering step of reordering the input data in a predetermined order, and the reordering using a second encoding circuit. And a second encoding step of performing error correction encoding on the output of the step, wherein a plurality of types of error correction encoding algorithms are realized by sharing the first encoding step.

Further, the storage medium of the present invention includes a first encoding procedure for error correction encoding of input data, a rearranging procedure for rearranging the input data in a predetermined order, and an output of the rearranging step. And a second encoding procedure for performing error correction encoding, wherein a program for realizing a plurality of types of error correction encoding algorithms by sharing the first encoding procedure is stored.

Further, the error correction coding apparatus of the present invention comprises: first coding means for performing error correction coding on input data; reordering means for rearranging the input data in a predetermined order;
A second encoding unit for performing error correction encoding on an output of the rearranging unit, wherein the first encoding unit and the second encoding unit
Implements a first error correction encoding algorithm using any one of the first encoding means and the second encoding means.
A second error correction coding algorithm is realized by using the coding means of (1).

The error correction encoding method according to the present invention further comprises a first encoding step of performing error correction encoding of input data;
A rearrangement step of rearranging the input data in a predetermined order; and a second encoding step of performing error correction encoding on an output of the rearrangement step, wherein the first encoding step and the second encoding step are performed. Implementing a first error correction encoding algorithm using any of the encoding steps,
And a second error correcting coding algorithm is realized by using the coding step and the second coding step.

Also, the storage medium of the present invention includes a first encoding procedure for error correction encoding of input data, a rearranging procedure for rearranging the input data in a predetermined order, and an output of the rearranging step. A second coding procedure for performing error correction coding, and implementing a first error correction coding algorithm using any of the first coding procedure and the second coding procedure; A program for realizing a second error correction coding algorithm using the first coding procedure and the second coding procedure is stored.

An error correction encoding apparatus according to the present invention further comprises a rearranging means for rearranging input data in a predetermined order, and an encoding means for error correcting and encoding at least one of the input data and the output of the rearranging means. Means for controlling the coding means to realize a plurality of types of error correction coding algorithms.

The error correction encoding method according to the present invention further comprises a rearranging step of rearranging input data in a predetermined order;
An encoding circuit for performing error correction encoding of at least one of the input data and the output of the rearranging step, wherein the encoding step is controlled to control a plurality of types of error correction encoding algorithms. Is realized.

Further, the storage medium of the present invention includes a rearrangement procedure for rearranging input data in a predetermined order, and an encoding procedure for error-correction encoding at least one of the input data and the output of the rearrangement step. And a program for controlling the coding procedure to realize a plurality of types of error correction coding algorithms.

The error correction decoding apparatus according to the present invention comprises a first decoding means for soft-output decoding input data, and a first reordering means for rearranging the output of the first decoding means in a predetermined order. Second decoding means for soft-output decoding the output of the first reordering means, and second reordering for reordering the output of the second decoding means in an order corresponding to the first reordering means. Means for implementing a plurality of types of error correction decoding algorithms by sharing the first decoding means.

Further, in the error correction decoding method according to the present invention, a first decoding step of soft-output decoding input data using a first decoding circuit, and an output of the first decoding step are arranged in a predetermined order. A first permutation step for permuting, a second decoding step for soft-output decoding the output of the first permutation step using a second decoding circuit, and an output of the second decoding step for the first permutation. And a second rearranging step for rearranging the data in an order corresponding to the rearranging step, wherein a plurality of types of error correction decoding algorithms are realized by sharing the first decoding step.

Further, the storage medium of the present invention includes a first decoding procedure for soft-output decoding input data, a first rearranging procedure for rearranging the output of the first decoding procedure in a predetermined order, A second decoding procedure for soft-output decoding the output of the first permutation procedure and a second permutation procedure for rearranging the output of the second decoding procedure in an order corresponding to the first permutation procedure. A program for realizing a plurality of types of error correction decoding algorithms by sharing the first decoding procedure.

Further, the error correction decoding apparatus of the present invention comprises a first decoding means for soft-output decoding input data, and a first reordering means for rearranging the output of the first decoding means in a predetermined order. Second decoding means for soft-output decoding the output of the first reordering means, and second reordering for reordering the output of the second decoding means in an order corresponding to the first reordering means. Means for implementing a first error correction decoding algorithm without using the second decoding means, and performing a second error correction using the first decoding means and the second decoding means.
Is realized.

Further, in the error correction decoding method according to the present invention, a first decoding step of soft-output decoding input data;
A first rearranging step of rearranging the output of the decoding step in a predetermined order, a second decoding step of soft-output decoding the output of the first rearranging step, and an output of the second decoding step. A second rearranging step for rearranging in an order corresponding to the first rearranging step, wherein a first error correction decoding algorithm is realized without using the second decoding step, A second error correction decoding algorithm is realized using the decoding step and the second decoding step.

Also, the storage medium of the present invention includes a first decoding procedure for soft-output decoding input data, a first rearranging procedure for rearranging the output of the first decoding procedure in a predetermined order,
A second decoding procedure for soft-output decoding the output of the first reordering procedure, and a second reordering procedure for reordering the output of the second decoding procedure into an order corresponding to the first reordering procedure A first error correction decoding algorithm is realized without using the second decoding procedure, and a second error correction decoding algorithm is realized using the first decoding procedure and the second decoding procedure. A program for realizing the above is stored.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) First, an error correction coding algorithm and an error correction decoding algorithm used in this embodiment will be described.

(1) Convolutional coding algorithm FIGS. 1A and 1B are diagrams for explaining an example of a convolutional coding algorithm.

The convolutional code is a coding system that outputs not only a bit string input at a certain point in time but also coded data affected by a bit string input before that point.

FIG. 1A is a block diagram showing an example of an error correction coding circuit necessary for realizing a non-recursive convolution coding algorithm. The circuit 100 includes delay circuits 101 and 102 for one unit time and addition circuits 103 and 104 for mod2.

The convolutional encoding circuit 100 supplies digital information input in a plurality of bits to the adders 103 and 104 as input data a. Adder circuit 103
Outputs the sum of the input data a and the output of the delay circuit 102 as encoded data b1, and the addition circuit 104 outputs the sum of the input data a and the output of the delay circuits 101 and 102 as encoded data b2.

FIG. 1B is a block diagram showing an example of an error correction coding circuit necessary for realizing a recursive convolution coding algorithm. The circuit 110 includes delay circuits 105 and 106 for one unit time and addition circuits 107 and 108 for mod2. This circuit 110
It is called a recursive convolutional coding circuit and is used in two coding circuits that implement a turbo coding algorithm described later.

The recursive convolutional encoding circuit 110 supplies digital information input in a plurality of bits to the adder circuit 107 as input data a. Adder circuit 107
Calculates the sum of the input data a and the output of the delay circuit 106 (that is, the feedback sum), and inputs the calculation result to the delay circuit 105 and the addition circuit 108. Addition circuit 1
08 adds the feedback sum of the addition circuit 107 and the outputs of the delay circuits 105 and 106, and outputs the result as encoded data b3.

(2) Soft Output Decoding Algorithm An example of the soft output decoding algorithm will be described with reference to FIG.

FIG. 2 is a block diagram showing an example of an error correction decoding circuit required to realize a soft output decoding algorithm. Hereinafter, the decoding circuit 200 will be described using a soft-input soft-output Viterbi decoding algorithm, which is one of the soft-output decoding algorithms, as an example.

The soft-output decoding circuit 200 includes an encoding circuit 20
1. a branch metric calculation circuit 202 for obtaining a branch metric which is a value indicating the strength of correlation between the code bit generated by the coding circuit 201 and the input data c;
(Add Compare Select) circuit 203, path metric memory 204 for storing path metrics of all paths, A
A path memory 205 for storing path selection information indicating a surviving path selected by the CS circuit 203; a traceback for generating the likelihood information of the maximum likelihood path by comparing the maximum likelihood path with a rival path opposing the maximum likelihood path It comprises a circuit 206.

Here, the ACS circuit 203 adds the branch metrics over a plurality of times to obtain the path metrics of the paths leading to each state. Then, the circuit compares path metrics of a plurality of paths leading to a certain state, and selects a path having a path metric with a stronger correlation (that is, a surviving path).

Next, the operation of the decoding circuit shown in FIG. 2 will be described.

The branch metric calculation circuit 202 outputs the output of the coding circuit 201 and the input data c every unit time.
To obtain a branch metric for each branch. The ACS circuit 203 adds the branch metrics over a plurality of times and calculates the path metrics of the paths leading to each state. This calculation result is stored in the path metric memory 204.

The ACS circuit 203 also compares the path metrics of a plurality of paths leading to each state, and selects a path estimated to have a stronger correlation with the input data c (that is, the path metric).
Survival path). The path metric of the surviving path selected at this time is stored in the path metric memory 204.
And the path selection information indicating the path is stored in the path memory 205. Here, the path metric memory 2
04 also stores the path metric of the path not selected at the same time as the surviving path. The ACS circuit 203 finally determines a path estimated to have the strongest correlation at a certain point in time (that is, the maximum likelihood path).

The trace-back circuit 206 traces the maximum likelihood path using the path selection information stored in the path memory 205, and calculates the path metric of the maximum likelihood path and the path metric of the opposing path corresponding to the maximum likelihood path. Then, the likelihood of the maximum likelihood path is calculated. Here, the likelihood is calculated by, for example, a sum of 差 of the difference between the path metrics at each time point. The traceback circuit 206 outputs the product of the maximum likelihood path and the likelihood as a decoding result d.

The soft output decoding circuit 200 shown in FIG. 2 is an example, and the present invention is not limited to this. For example, the encoding circuit 201 can be realized by a table in which inputs and outputs of the encoding circuit 201 are associated with each other.

(3) Turbo Coding Algorithm The turbo coding algorithm will be described with reference to FIG.

FIG. 3 is a block diagram showing an example of an error correction coding circuit necessary for realizing the turbo coding algorithm. The circuit 300 includes an interleaver 301 for rearranging input data x based on random or predetermined rules, and two convolutional encoding circuits 302 and 303. Here, the convolutional encoding circuit 30
For example, the recursive convolutional coding circuit 110 shown in FIG.

The turbo encoding circuit 300 converts the input digital information of a plurality of bits into three output data (x, y1, y2 in FIG. 3). The three output data are
The result of input data x output as it is (ie, output data x), the result of convolutional coding of input data x (ie, output data y1), and the convolutional coding of input data x whose bit order is rearranged by interleaver 301 (I.e., output data y2), and an information sequence including these three output data is turbo encoded data.

(4) Turbo decoding algorithm The turbo decoding algorithm will be described with reference to FIG.

FIG. 4 is a block diagram showing an example of an error correction decoding circuit necessary for realizing the turbo decoding algorithm. The circuit 400 includes soft-output decoding circuits 401 and 403 that soft-output decode input data using the above-described soft-output decoding algorithm or the like, and an interleaving interleave that rearranges the output of the soft-output decoding circuit 401 based on random or predetermined rules. Lever 402, Interleaver 402
, And an analog / digital conversion circuit (A / D conversion circuit) 405.

Here, the soft output decoding circuits 401 and 403
Performs a metric operation using an analog value or a digital value quantized to three or more values as input data, and for each decoded bit, a value indicating the likelihood that the bit is “1” (or “0”) (likelihood). Degree), and outputs a decoding result including the likelihood.

In FIG. 4, turbo coded data received or read from a recording medium (ie, input series X, Y
1, Y2) are input to the turbo decoding circuit 400. Here, the input sequences X, Y1, and Y2 respectively correspond to the output sequences x, y1, and y2 shown in FIG.

The input sequences X and Y1 are supplied to a soft output decoding circuit 40.
1 and decoded. Interleaver 402
Interleave the decoding result of the soft output decoding circuit 401,
The result is supplied to the soft output decoding circuit 403. Soft output decoding circuit 403 performs soft output decoding using the output of interleaver 402 and input sequence Y2, deinterleaves the decoding result, and supplies the result to soft output decoding circuit 401.

After repeating the above processing a predetermined number of times, the turbo decoding circuit 400 supplies the output of the deinterleaver 404 to the A / D conversion circuit 405. A / D conversion circuit 40
5 binarizes the input information and converts the result into an input sequence X, Y
1, Y2 (that is, turbo encoded data) and output as decoding results.

Next, a description will be given of an error correction coding circuit which realizes both the above-described convolution coding algorithm and turbo coding algorithm.

FIG. 5 is a block diagram showing an example of the error correction coding circuit according to this embodiment.

The error correction coding circuit 500 includes an interleaver 501, convolution coding circuits 502 and 503, switches 504 and 505 controlled by a selection signal, an input terminal 506 for inputting digital information, and controls the operation of the circuit 500. And an input terminal 507 for inputting a selection signal. Here, again, the convolutional encoding circuits 502,
Reference numeral 503 denotes a circuit that implements a recursive convolutional coding algorithm, and has the same configuration as, for example, the recursive convolutional coding circuit 110 illustrated in FIG.

When the selection signal is active, the switch 5
04, 505 are turned on, and the error correction coding circuit 500
Operate as an error correction coding circuit that implements the above-described turbo coding algorithm. Specifically, the error correction coding circuit 500 performs the same processing as the turbo coding circuit 300 shown in FIG. As a result, the error correction coding circuit 50
0 outputs turbo coded data concatenated by three output data x, y1, and y2.

Here, the output data x is the input data x, the output data y1 is the result of the convolutional coding of the input data x by the convolutional coding circuit 502, and the output data y2 is the result of the convolutional coding circuit 503 being interleaved. This is the result of convolutionally encoding the input data x.

When the selection signal is inactive, the switches 504 and 505 are turned off, and the error correction coding circuit 500 operates as an error correction coding circuit for realizing the above-described recursive convolution coding algorithm. As a result, the error correction encoding circuit 500 outputs only the output data y1 which is the convolutionally encoded data.

Here, the error correction coding circuit 500 may not only turn off the switches 504 and 505, but also cut off or significantly reduce the power supplied to the convolutional coding circuit 503. As a result, not only the circuit scale can be simplified, but also the power consumption can be reduced, and a higher effect can be obtained when the above-described error correction decoding circuit 500 is applied to a portable electronic device such as a mobile phone.

The switch 505 is connected to the interleaver 50.
1 may be connected to the preceding stage instead of the latter stage. in this case,
Since the power supplied to the interleaver 501 can also be cut off or reduced, the power consumption can be further reduced.

FIG. 6 is a block diagram showing another example of the error correction coding circuit of the present embodiment. The error correction coding circuit 600 shown in FIG. 6 can also realize both the convolution coding algorithm and the turbo coding algorithm described above. In FIG. 6, the same components as those in FIG. 5 are denoted by the same reference numerals.

The circuit 600 includes an interleaver 501,
The convolution coding circuits 502 and 503 and the selection circuit 601 are provided. Here, the selection circuit 601 selects necessary data from the data x, the data y1 generated by the convolutional coding circuit 502, and the data y2 generated by the convolutional coding circuit 503 according to the selection signal. Output.

When the selection signal is active, the error correction coding circuit 600 operates as an error correction coding circuit for realizing the above turbo coding algorithm. Specifically, the selection circuit 601 selects and outputs all three data x, y1, and y2. As a result, the error correction coding circuit 600 outputs turbo coded data including the three data x, y1, and y2.

When the selection signal is inactive, the error correction coding circuit 600 operates as an error correction coding circuit for realizing the above-described convolution coding algorithm. Specifically, the selection circuit 601 selects and outputs only the data sequence y1. As a result, the error correction coding circuit 600 outputs only the data y1 which is the convolutionally coded data.

As described above, in the first embodiment, since a part of the circuit is shared between the coding circuit for realizing the convolutional coding algorithm and the coding circuit for realizing the turbo coding algorithm, a plurality of types of error The correction encoding algorithm can be realized by one encoding circuit.
As a result, a plurality of types of error correction coding algorithms can be realized with a simple and efficient circuit configuration, and an increase in circuit scale and an increase in cost can be suppressed.

In the first embodiment, when the error correction coding circuit 500 or the error correction coding circuit 600 operates as a convolutional coding circuit, it outputs only the information sequence y1 and outputs the information sequence y1 as a turbo coding circuit. When operating, the information sequences x, y1, and y2 are configured to be output. However, the present invention is not limited to this, and other combinations may be used.

For example, when operating as a convolutional encoding circuit, it may be configured to output only the information sequence y2. In this case, error correction coding circuits 500 and 600
Has a configuration in which the interleaver 501 operates according to a predetermined rule, rearranges the input data x, and then performs convolutional coding. With such a configuration, it is also possible to enhance error resistance against burst errors of the encoded data.

As described above, the error correction coding circuit 500,
The 600 can implement both the convolutional coding algorithm and the turbo coding algorithm by sharing the interleaver 501 and the convolutional coding circuit 503.

(Second Embodiment) Next, the configuration and processing operation of a decoding circuit corresponding to the error correction coding circuits 500 and 600 described in the first embodiment will be described.

FIG. 7 is a block diagram showing an example of the error correction decoding circuit of this embodiment.

The circuit 700 comprises a soft output decoding circuit 701,
703, an interleaver 702 that rearranges the output of the soft-output decoding circuit 701 based on random or predetermined rules;
Deinterleaver 70 corresponding to interleaver 702
4, an analog / digital (A / D) conversion circuit 705,
Switches 706 and 708 that are turned on when the selection signal is active under the control of the selection signal, are connected to the B side when the selection signal is activated under the control of the selection signal, and are connected when the selection signal is inactive. A switch 707 connected to the A side, an input terminal 710 for inputting a selection signal for controlling the operation of the circuit 700, an input terminal 711 for inputting data X, an input terminal 712 for inputting data Y1, and an input terminal for inputting data Y2 713.

Here, the soft output decoding circuits 701 and 703
Performs a metric operation on input information in the same manner as the soft output decoding circuits 401 and 403 described above, and for each bit, a value indicating the likelihood that the bit is “1” (or “0”) (likelihood). ), And outputs the likelihood together with the decoding result.

When the selection signal is active, error correction decoding circuit 700 performs, for example, the same processing as turbo decoding circuit 400 in FIG. Hereinafter, the processing operation of the error correction decoding circuit 700 will be specifically described.

In FIG. 7, turbo coded data received or read from a recording medium (ie, input data X,
Y1, Y2) are input to the error correction decoding circuit 700. Here, the input data X, Y1, Y2 correspond to the output data x, y1, y2 shown in FIG. 5 or 6, respectively.

The input data X and Y1 are supplied to the soft output decoding circuit 7
01 and decoded. Interleaver 702
Interleaves the decoding result of the soft output decoding circuit 701 with the likelihood of each bit, and compares the result with the soft output decoding circuit
Supply 3 The soft output decoding circuit 703 performs soft output decoding using the output of the interleaver 702 and the input data Y2. The decoding result and the likelihood are calculated by the deinterleaver 7.
04 and deinterleaved. The output of the deinterleaver 704 is supplied to a soft output decoding circuit 701 via a switch 708.

After repeating the above processing a predetermined number of times, error correction decoding circuit 700 supplies the output of deinterleaver 704 to A / D conversion circuit 705 via switch 707. The A / D conversion circuit 705 binarizes the input information,
The result is output as a decoding result of the input data X, Y1, Y2 (that is, turbo encoded data).

When the selection signal is inactive, the error correction decoding circuit 700 is, for example, the soft output decoding circuit 2 shown in FIG.
The same processing as 00 is performed.

In this case, the switches 706 and 709 are turned off, and the error correction decoding circuit 700 supplies the input data Y1
Only is entered. The soft output decoding circuit 701 performs soft output decoding on the input data Y1 and supplies the decoding result to the switch 707. Here, the switch 707 is connected to the A side, and the output of the soft output decoding circuit 701 is A
/ D conversion circuit 705. A / D conversion circuit 70
5 is to binarize the input information and convert the result into input data Y1
Is output as a decryption result.

Here, the error correction decoding circuit 700 is the same as that shown in FIG.
However, the present invention is not limited to the configuration shown in FIG. For example, switch 70
6, 708, and 709 as well as the interleaver 702, the soft output decoding circuit 703, and the deinterleaver 7
The power supplied to the power supply 04 may be cut off or significantly reduced. Thus, not only the circuit scale can be simplified, but also the power consumption can be reduced.
In the case where is applied to a portable electronic device such as a mobile phone, a higher effect can be obtained.

As described above, in the second embodiment, a part of the circuit is shared between the decoding circuit for realizing the soft-output decoding algorithm and the decoding circuit for realizing the turbo decoding algorithm. Can be realized by one decoding circuit. As a result, a plurality of types of error correction decoding algorithms can be realized with a simple and efficient circuit configuration, and an increase in circuit scale and an increase in cost can be suppressed.

In the second embodiment, when the error correction decoding circuit 700 operates as a soft output decoding circuit, only the input data Y1 is decoded, and when the error correction decoding circuit 700 operates as a turbo decoding circuit, the input data X , Y1 and Y2 are decoded, but the present invention is not limited to this, and other combinations may be used.

For example, when operating as a soft output decoding circuit, it may be configured to decode only the input data Y2. In this case, error correction decoding circuit 700 decodes input data Y2 using soft output decoding circuit 703, rearranges the decoding result in the original order using deinterleaver 704, and outputs the decoding result from the output of deinterleaver 704. Generate This makes it possible to decode convolutionally encoded data after interleaving.

As described above, the error correction decoding circuit 700
Both the soft output decoding algorithm and the turbo decoding algorithm can be realized by sharing the soft output decoding circuit 703 and the deinterleaver 704.

(Third Embodiment) In the first embodiment, FIG.
The example of the error correction coding circuit that realizes both the convolution coding algorithm and the turbo coding algorithm using the error correction coding circuit 500 shown in FIG.

On the other hand, in the third embodiment, an error correction coding circuit capable of further improving the error correction capability of the convolutional coding algorithm and selectively switching the error correction capability of the convolutional coding algorithm. Will be described.

The third embodiment will be described below using the error correction coding circuit 500 shown in FIG.

In FIG. 5, error correction coding circuit 500
Operates as a circuit that implements the turbo coding algorithm, the circuit 500 turns on both the switches 504 and 505. As a result, the error correction coding circuit 50
0 is three output data x, y, as in the first embodiment.
1, and y2 are output as turbo encoded data.

When the error correction coding circuit 500 operates as a circuit for realizing a convolution coding algorithm, the circuit 500 switches the switch 50 according to the selection signal.
Both the switch 505 and the switch 505 are turned off.

When both the switches 504 and 505 are turned off, the error correction coding circuit 500 outputs only the data x as coded data, as in the first embodiment.

On the other hand, when only the switch 505 is turned off, the error correction encoding circuit 500 outputs encoded data composed of two output sequences x and y1. This makes it possible to output coded data having a high error correction capability, although the code length becomes long.

The switches 504 and 505 are controlled by a selection signal. The selection signal is supplied to the switch 50 in accordance with the status of the transmission path and the error characteristics and quality of the data to be transmitted.
4,505 on / off is adaptively controlled.

With this configuration, in the third embodiment, both the convolutional coding algorithm and the turbo coding algorithm can be realized by one coding circuit, and the error correction capability of the convolutional coding algorithm is required. It can also be selectively switched according to it. Thereby, a plurality of types of error correction coding algorithms can be realized with a simple and efficient circuit configuration.
It is also possible to selectively switch the error correction capability of a predetermined error correction coding algorithm as required while suppressing an increase in circuit scale and cost.

In the third embodiment, as in the first embodiment, the interleaver 501 and the convolution coding circuit 503 are used.
Can be implemented to implement a plurality of types of error correction coding algorithms. In this case, the error correction coding circuit 5
No. 00 can selectively switch the error correction capability of the convolutional coding algorithm by selecting whether to output coded data consisting only of data x or to output coded data consisting of data x and y2. it can.

(Fourth Embodiment) In the second embodiment, FIG.
The example of the error correction decoding circuit that realizes both the soft output decoding algorithm and the turbo decoding algorithm using the error correction decoding circuit 700 shown in FIG.

On the other hand, the fourth embodiment relates to an error correction decoding circuit capable of further improving the error correction capability of the soft output decoding algorithm and selectively switching the error correction capability of the soft output decoding algorithm. explain.

Hereinafter, a fourth embodiment will be described using the error correction decoding circuit 700 of FIG. The error correction decoding circuit according to the fourth embodiment is a decoding circuit corresponding to the error correction encoding circuit according to the third embodiment.

In FIG. 7, when the error correction decoding circuit 700 operates as a circuit for realizing the turbo decoding algorithm, the circuit 700 turns on both the switches 706 and 708. As a result, the error correction decoding circuit 700
As in the second embodiment, three input data X, Y1, Y
2 is decrypted.

When the error correction decoding circuit 700 operates as a circuit for realizing a soft output decoding algorithm, the circuit 700 switches 706 and 708 according to the selection signal.
, Or only the switch 708 is turned off.

When both the switches 706 and 708 are turned off, the error correction decoding circuit 700 decodes only the input data Y1, as in the second embodiment.

On the other hand, when only the switch 708 is turned off, the error correction decoding circuit 700 decodes the two input data X and Y1. As a result, decoding processing with high error correction capability can be executed.

The switches 706 and 708 are controlled by a selection signal. The selection signal is supplied to the switch 7 according to the state of the transmission path, the error correction coding method of the received data, and the like.
06,708 are controlled adaptively.

With this configuration, in the fourth embodiment, both the soft output decoding algorithm and the turbo decoding algorithm can be realized by one decoding circuit, and the error correction capability of the soft output decoding algorithm can be increased as required. It can also be selectively switched. As a result, a plurality of types of error correction decoding algorithms can be realized with a simple and efficient circuit configuration, and the error correction capability of a predetermined error correction decoding algorithm is required while suppressing an increase in circuit scale and cost. It can also be selectively switched according to it.

(Fifth Embodiment) FIG. 8 is a block diagram showing an example of an error correction coding circuit according to a fifth embodiment.

The error correction coding circuit 800 includes an interleaver 801, a coding circuit 802 for controlling a processing operation by a selection signal, a coding circuit 803, and an on / off control by a selection signal.
It is composed of switches 804 and 805 for controlling off, an input terminal 806 for inputting digital information, and an input terminal 807 for inputting a selection signal for controlling the operation of the circuit 800.

Here, the switches 804 and 805 are turned on when the selection signal is active. The coding circuit 803 operates as a coding circuit that implements the above-described recursive convolution coding algorithm.

Next, a block diagram showing an example of the encoding circuit 802 is shown in FIG.

In FIG. 9, an encoding circuit 802 controls its operation according to a selection signal input from the outside. Specifically, the number of valid delay circuits, the connection between the delay circuits and the adder circuit, the presence or absence of recursive processing, and the like are determined, and a plurality of error correction encoding algorithms having different error correction capabilities are realized.

The encoding circuit 802 includes a switch 901 for selecting one of two inputs, delay circuits 902 and 90
3, 904, mod 2 adder circuits 905, 906, 90
7, an NOT control element 908, an AND control element 909, and an output control circuit 910 that outputs one of two inputs C and D.

When the selection signal becomes active, the switch 901 is connected to the terminal on the A side in FIG.
2 operates as a circuit that implements the recursive convolutional coding algorithm described above. Specifically, the encoding circuit 80
Numeral 2 operates as a recursive convolutional coding circuit having a constraint length of 3 and a coding rate of 1/1.

In this case, the AND element 909 has a NOT
Since the selection signal inverted by the element 908 is input, A
The output of the ND element 909 is always “0”. Further, the output control circuit 910 selects only the output C of the adder circuit 906 and outputs this as the output sequence y1.

The input series x and the delay circuit 903 are input to the addition circuit 905, and the operation result is output to the switch 90.
1 is supplied. The addition circuit 906 includes an addition circuit 9
05, the output of the delay circuit 902, and the output of the delay circuit 903 are input, and the operation result (that is, the output signal C) is supplied to the output control circuit 910.

As described above, when the selection signal is active, encoding circuit 802 performs the same processing as the above-described recursive convolutional encoding circuit, and performs the same operation as encoding circuit 803. It will be. As a result, the error correction coding circuit 900 has the same configuration as the turbo coding circuit 300 shown in FIG. 3, for example, and implements the above-described turbo coding algorithm.

When the selection signal becomes inactive,
The switch 901 is connected to the terminal on the B side in the figure, and the encoding circuit 802 operates as a circuit that implements the above-described non-recursive convolutional encoding algorithm. Specifically, the coding circuit 802 operates as a non-recursive convolutional coding circuit having a constraint length of 4 and a coding rate of 1/2.

In this case, the AND element 909 supplies the output of the delay circuit 903 to the delay circuit 904 as it is.
Also, the output control circuit 910 determines the output C of the adder circuit 906.
And the output D of the adder circuit 907, and output both as an output sequence y1.

The input sequence x, the output of the delay circuit 902, and the output of the delay circuit 903 are input to the adder circuit 906, and the operation result (that is, the output signal C) is supplied to the output control circuit 910. The input series x, the output of the delay circuit 902, and the output of the delay circuit 904 are input to the adder circuit 907, and the operation result (that is, the output signal D) is supplied to the output control circuit 910.

As described above, when the selection signal becomes inactive, the encoding circuit 802 performs the same processing as the above-described convolutional encoding circuit. As a result, the error correction coding circuit 800 operates as a circuit that implements the above-described non-recursive convolution coding algorithm.

In the fifth embodiment, by controlling the selection signal, the encoding circuit 802 determines the number of delay circuits and the constraint length when the encoding circuit 802 operates as a non-recursive convolutional encoding circuit. The configuration is such that the number is increased as compared with the case of operating as a type convolutional coding circuit. With this configuration, the error correction coding circuit 800 can optimize the error correction capability and the amount of calculation in each error correction coding algorithm.

The encoding circuit 802 shown in FIG. 9 is an example, and the present invention is not limited to this. For example, it is possible to further increase the number of delay circuits that change with a change in the selection signal. Also, by using the second selection signal, even if the selection signal is in an inactive state, the number of delay circuits is selectively changed according to the state of the transmission line, the load on the device, and the like. You may.

As described above, in the fifth embodiment, a non-recursive convolutional coding algorithm can be realized by using one of the coding circuits necessary for realizing the turbo coding algorithm.

Further, the number of delay circuits which affect the error correction capability and the amount of operation can be switched between the turbo coding algorithm and the non-recursive convolutional coding algorithm. The amount of calculation can be adjusted optimally.

(Sixth Embodiment) In a fifth embodiment, an error correction coding circuit that realizes a plurality of types of error correction coding algorithms by sharing one of the two coding circuits 802 and 803 is used. Was explained.

On the other hand, in the sixth embodiment, an example will be described in which a plurality of types of error correction coding algorithms are realized by sharing a coding circuit in which the coding circuits 802 and 803 are integrated.

FIG. 10 is a block diagram showing an example of the error correction coding circuit according to the sixth embodiment. In FIG. 10, the same components as those in FIG. 8 are denoted by the same reference numerals.

The error correction coding circuit 1000 includes an interleaver 801, a coding circuit 801 for controlling a processing operation by a selection signal, switches 804 and 805 for controlling on / off by a selection signal, and an input terminal 806 for inputting digital information. , An input terminal 807 for inputting a selection signal for controlling the operation of the circuit 1000. here,
Switches 804 and 805 are turned on when the selection signal is active.

Next, a block diagram showing an example of the encoding circuit 1001 is shown in FIG.

In FIG. 11, an encoding circuit 1001 comprises:
The operation is controlled by a selection signal input from the outside. Specifically, the number of valid delay circuits, the connection between the delay circuits and the adder circuit, the presence or absence of recursive processing, and the like are determined, and a plurality of error correction encoding algorithms having different error correction capabilities are realized.

The encoding circuit 1001 includes a delay circuit 110
1, 1102, 1103, 1104, mod 2 adder circuits 1105, 1106, 1107, 1108, NOT element 1109, AND elements 1110, 1111, 111
2 and 1113, and an output control circuit 1114.

When the selection signal becomes active, the encoding circuit 1001 operates as two encoding circuits for realizing the above-described recursive convolution encoding algorithm. Specifically, the configuration 1115 shown in FIG. 11 operates as a first recursive convolutional coding circuit, and the configuration 1116 operates as a second recursive convolutional coding circuit.

In this case, AND circuits 1110 and 1111
Output the outputs of the delay circuits 1102 and 1104 as they are. The AND circuit 1112 always outputs “0”, and the AND circuit 1113 outputs
And outputs the data x ′ supplied from. As a result, the configuration 1115 encodes the data x with a recursive convolutional encoding algorithm, and the configuration 1116
Will encode the data x ′ with a recursive convolutional encoding algorithm.

The output control circuit 1114 is
7 is output as output data y1, and the addition circuit 1
The output B 108 is output as output data y2.

When the selection signal becomes active as described above, since the encoding circuit 1001 operates as two recursive convolutional encoding circuits, the error correction encoding circuit 1000
Can operate as a turbo encoding circuit as shown in FIG. Note that the first and second recursive convolutional coding circuits formed in the coding circuit 1001 are coding circuits having the same number of delay circuits and the same constraint length and coding rate.

When the selection signal becomes inactive,
The encoding circuit 1001 operates as one encoding circuit that implements the above-described non-recursive convolutional encoding algorithm.

In this case, AND circuits 1110 and 1111
Always outputs "0". The AND circuit 1112 outputs the output of the delay circuit 1102 as it is, and the AND circuit 1113 always outputs “0”. As a result, the output of the delay circuit 1102 is directly input to the delay circuit 1103.

The input series x, the output of the delay circuit 1101, and the output of the delay circuit 1102 are input to the addition circuit 1107, and the operation result (that is, the output signal A) is supplied to the output control circuit 1114. Further, the output of the delay circuit 1102, the output of the delay circuit 1103, and the output of the delay circuit 1104 are input to the addition circuit 1108, and the operation result thereof (that is,
The output signal B) is supplied to the output control circuit 1114.

The output control circuit 1114 is
7 and the output B of the adder circuit 1108 are output as output data y1. That is, the output control circuit 1114
Are input data x, delay circuits 1101, 1103, 11
04 will be output.

As described above, when the selection signal becomes inactive, the encoding circuit 1001 can operate as one non-recursive convolutional encoding circuit. Note that the number of delay circuits and the constraint length of one non-recursive convolutional coding circuit formed in the coding circuit 1001 are larger than those of the first and second recursive convolutional coding circuits described above. Become.

As described above, in the sixth embodiment, by controlling the selection signal, the number of delay circuits and the constraint length when the encoding circuit 1001 operates as one non-recursive convolutional encoding circuit can be reduced. The encoding circuit 1002 is configured to be larger than when it operates as two recursive convolutional encoding circuits. With this configuration,
The error correction coding circuit 1000 can optimize the error correction capability and the amount of calculation in each error correction coding algorithm.

The encoding circuit 1001 shown in FIG. 11 is an example, and the present invention is not limited to this. For example, it is possible to further increase the number of delay circuits that change with a change in the selection signal. Further, by using the second selection signal, even if the selection signal is in an inactive state,
The configuration may be such that the number of delay circuits is selectively changed according to the state of the transmission path, the load on the device, and the like.

As described above, in the sixth embodiment, two encoding circuits required to implement the turbo encoding algorithm can be implemented by one encoding circuit, and non- A recursive convolutional coding algorithm can also be performed.

Also, the number of delay circuits that affect the error correction capability and the amount of operation can be switched between the turbo coding algorithm and the non-recursive convolutional coding algorithm, and the error correction that is optimal for each algorithm is possible. Correction capability and calculation amount can also be set.

(Seventh Embodiment) FIG. 12 is a block diagram showing another example of the error correction decoding circuit of the present embodiment.

The error correction decoding circuit 1200 includes a soft output decoding circuit 1201, an interleaver 1202, a soft output decoding circuit 1203, and a deinterleaver 120 corresponding to the interleaver 1202, which control the processing operation by the selection signal.
4. Analog / digital (A / D) conversion circuit 120
5. Switch 12 for controlling on / off by selection signal
061, 1208, 1209, a switch 1207 connected to the terminal on the B side when the selection signal becomes active, and connected to a terminal on the A side when the selection signal becomes inactive,
Input terminal 121 for inputting a selection signal for controlling the operation of 0
0, input terminal 1211 for inputting data X, data Y1
And an input terminal 1213 for inputting data Y2.

Here, input data X, Y1, Y2 are output data x, y1, y corresponding to FIG. 8 or 10, respectively.
2.

When the selection signal is active, switch 1
206, 1208, and 1209 are turned on, and the switch 1
207 is connected to the terminal on the B side. As a result, the error correction decoding circuit 1200 has two soft output decoding circuits 1201,
It operates as a decoding circuit that decodes the input data X, Y1, Y2 using 1203. In this case, the error correction decoding circuit 1200 operates as a circuit that implements the turbo decoding algorithm described above.

When the selection signal is active, the two soft output decoding circuits 1201 and 1203 have a circuit configuration for realizing the same soft output decoding algorithm.

When the selection signal is inactive, the switches 1206, 1208, and 1209 are turned off, and the switch 1207 is connected to the terminal on the A side. As a result, the error correction decoding circuit 1200 operates as a decoding circuit that decodes the input data Y1 using only the soft output decoding circuit 1201. In this case, the error correction decoding circuit 1200 operates as a circuit that realizes the above-described soft output decoding algorithm.

Next, FIG. 13 is a block diagram showing an example of the soft output decoding circuit 1201.

A soft output decoding circuit 1201 includes an encoding circuit 1301 for changing the internal configuration according to the selection signal, a branch metric for obtaining the branch metric of the input data X and Y1 or the branch metric of the input data Y1 according to the selection signal. Arithmetic circuit 1302, ACS circuit 1303,
A path metric memory 1304 for storing path metrics of all paths, a path memory 1305 for storing path selection information indicating a surviving path selected by the ACS circuit 1303, and comparing a maximum likelihood path with a rival path against the maximum likelihood path And a traceback circuit 1306 that generates likelihood information of the maximum likelihood path.

Here, the coding circuit 1301 has a configuration corresponding to the above-described error correction coding circuit 800 or 1000. When each of the circuits 800 and 1000 operates as a convolutional coding circuit, the coding of the circuit is not performed. It is configured to generate a plurality of states to be obtained. When each of the circuits 800 and 1000 operates as a turbo encoding circuit, a plurality of states that the first convolutional encoding circuit of the circuit can take are generated. Specifically, the coding circuit 1301 changes the number of delay circuits that are enabled according to the selection signal, the connection between the delay circuits and the addition circuit, the presence or absence of recursion, and the like, and switches the error-correction coding algorithm that can be decoded. .

When the selection signal becomes active, the encoding circuit 1301 has a circuit configuration for generating code bits necessary for obtaining the branch metrics of the input data X and Y1, and the branch metric operation circuit 1302 outputs the input data X and Y1. , Y1 and the output of the encoding circuit 1301 to obtain a branch metric for each branch. Here, the input data X and Y1 are a part of the coded data generated when the error correction coding circuit 800 or 1000 implements the turbo coding algorithm.

When the selection signal becomes inactive,
The encoding circuit 1301 has a circuit configuration for generating a sign bit necessary for obtaining a branch metric of the input data Y1.
The input data Y1 is compared with the output of the encoding circuit 1301 to obtain a branch metric for each branch. Here, the input data Y1 is encoded data generated when the error correction encoding circuit 800 or 1000 implements a non-recursive convolutional encoding algorithm.

As described above, the seventh embodiment uses one of the soft-output decoding circuits necessary for realizing the turbo decoding algorithm to perform coding by the non-recursive convolutional coding algorithm. The data can be soft-output decoded.

The soft output decoding circuit 1201 shown in FIG. 13 is an example, and the present invention is not limited to this. For example, the encoding circuit 1301 can be realized by a plurality of types of tables in which inputs and outputs of the encoding circuit 1301 are associated. In this case, the soft output decoding circuit 1201 is configured to switch a decodable error correction encoding algorithm by selecting a predetermined table from a plurality of types of tables. With such a configuration, the configuration of the soft output decoding circuit 1201 can be further simplified.

(Eighth Embodiment) FIG. 14 is a block diagram showing an example of an electronic apparatus to which any one of the above-described error correction coding circuits 500, 600, 800, and 1000 is applied.
Here, the electronic device 1400 is a portable information terminal such as a mobile phone or a mobile computer capable of wireless communication.

In FIG. 14, a microphone 1401 receives an external voice and generates a predetermined voice file. The imaging unit 1402 generates a predetermined image file from an optical image of a subject. The external input terminal 1403 inputs an audio file, a text file, an image file, various data files, and the like from an external device.

The data processing unit 1404 includes the microphone 140
1, an audio file, a text file, an image file supplied from the imaging unit 1402 and the external input terminal 1403,
Various data files and the like are converted into a predetermined data format for wireless communication. Also, the data processing unit 1404
Has a function of converting various files into a data format that can be displayed and output.

The error correction coding section 1405 is composed of any one of the above-described error correction coding circuits 500, 600, 800 and 1000. The error correction coding unit 1405 performs error correction coding on various files by selectively using the above-described convolution coding algorithm and turbo coding algorithm.

The modulation section 1406 is provided with the error correction encoding section 14
05 output, for example, CDMA (Code Divis)
Digital modulation is performed using an ion multiple access (Io Multiple Access) communication method. Transmitting section 1407 converts the output of modulating section 1406 into a radio signal, and transmits the radio signal to a predetermined terminal or base station.

Control unit 1408 controls the operation of each unit of electronic device 1400 using a microcomputer.
Here, the control unit 1408 converts the above-described selection signal into an error-correction coding unit 1405 according to an instruction from the operation unit 1409.
To supply. The error correction coding unit 1 is selected by this selection signal.
Reference numeral 405 functions as a processing unit that implements either the convolutional coding algorithm or the turbo coding algorithm.

An operation unit 1409 is composed of numeric keys and the like.
Select the error correction coding algorithm, transmission destination and transmission data to be used. The display unit 1410 includes a liquid crystal monitor or the like, and displays data of various files. The storage medium 1411 stores a plurality of types of programs that can be read by the control unit 1408.

As described above, by adopting the error correction coding circuit of each embodiment for a portable telephone or a portable information terminal capable of wireless communication, an electronic device corresponding to a plurality of types of error correction coding algorithms can be provided. It can be realized at a small size and at low cost.

(Ninth Embodiment) FIG. 15 is a block diagram showing an example of an electronic apparatus to which any of the above-described error correction decoding circuits 700 and 1200 is applied. Here, the electronic device 1
Reference numeral 500 denotes a portable information terminal such as a mobile phone or a mobile computer capable of wireless communication.

Receiving section 1501 receives a radio signal transmitted from a predetermined terminal or base station. The demodulation unit 1502
The output of the receiving unit 1501 is demodulated using, for example, a CDMA communication system.

The error correction decoding section 1503 comprises one of the error correction decoding circuits 700 and 1200 described above.
The error correction decoding unit 1503 performs error correction decoding of various files by selectively using a soft output decoding algorithm and a turbo decoding algorithm.

The data processing section 1504 converts the error-corrected decoded data into various files. Various files are stored in the speaker 150 according to the instruction of the operation unit 1510.
5, display unit 1506, external output terminal 1507, recording unit 1
508.

[0160] Speaker 1505 decodes and outputs the audio file. The display unit 1506 decodes and outputs a text file, an image file, and various data files. The external output 1507 supplies a file specified by the operation unit 1510 among various files to an external device. The recording unit 1508 stores a file specified by the operation unit 1510 among various files in a recording medium such as a magnetic disk, a magnetic tape, and a semiconductor memory.

The control section 1509 controls the operation of each section of the electronic device 1500 using a microcomputer.
Here, the control unit 1509 supplies the above selection signal to the error correction decoding unit 1503 according to an instruction from the operation unit 1510. By this selection signal, error correction decoding section 150
Reference numeral 3 functions as a processing unit that implements either the soft output decoding algorithm or the turbo decoding algorithm.

The operation unit 1510 includes a numeric keypad and the like.
Select the error correction code algorithm, source and received data to be used. The storage medium 1511 includes a control unit 1509.
Are stored.

As described above, by adopting the error correction decoding circuit of each embodiment for a portable telephone or a portable information terminal capable of wireless communication, an electronic device corresponding to a plurality of types of error correction decoding algorithms can be reduced in size. , And at low cost.

(Other Embodiments) The above-described embodiment can be realized as follows.

For example, a recording medium in which software programmed to implement the first to seventh embodiments is recorded is stored in the control unit 1 provided in the electronic apparatus according to the eighth and ninth embodiments.
408 and 1509. And
The control units 1408 and 1509 store the storage media 1411, 1
The program stored in 511 is read and the operation of the electronic device is controlled to implement the above-described embodiment.

In this case, one of the two error correction coding program modules required to realize the above turbo coding algorithm can be a common program module. As a result, the program amount of the entire program can be reduced, and the development process can be shortened.

The recording media 1411 and 1511 for supplying software include, for example, floppy disks, hard disks, optical disks, magneto-optical disks,
A CD-ROM, CD-R, magnetic tape, nonvolatile memory card, ROM, or the like can be used.

Further, the above-mentioned software is stored in the recording medium 14.
11 or 1511 or may be recorded on recording media 1411 and 1511 after being supplied from the outside.

[0169]

As described above, according to the present invention, a plurality of types of error correction coding algorithms or decoding algorithms can be realized with a simple and low-cost circuit configuration without increasing the circuit scale. .

According to the present invention, both the convolutional coding algorithm and the turbo coding algorithm can be realized by one coding circuit, and the error correction capability of the convolutional coding algorithm is selectively switched as required. You can also. In addition, both the soft output decoding algorithm and the turbo decoding algorithm can be realized by one decoding circuit, and the error correction capability of the soft output decoding algorithm can be selectively switched as needed.

Further, according to the present invention, the number of delay circuits that affect the error correction capability and the amount of operation can be switched between the turbo coding algorithm and the non-recursive convolutional coding algorithm. It is also possible to set an error correction capability and a calculation amount that are optimal by the algorithm.

Further, according to the present invention, it is possible to realize a small-sized and low-cost electronic device such as a mobile phone or a portable information terminal capable of wireless communication, which supports a plurality of types of error correction coding algorithms. . In addition, electronic devices such as mobile phones and portable information terminals capable of wireless communication that support a plurality of types of error correction decoding algorithms can be realized in a small size and at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a circuit for realizing a convolutional coding algorithm.

FIG. 2 is a block diagram showing an example of a circuit for realizing a soft output decoding algorithm.

FIG. 3 is a block diagram illustrating an example of a circuit that implements a turbo coding algorithm.

FIG. 4 is a block diagram illustrating an example of a circuit that implements a turbo decoding algorithm.

FIG. 5 is a block diagram illustrating an example of an error correction encoding circuit according to the first embodiment.

FIG. 6 is a block diagram showing another example of the error correction coding circuit in the first embodiment.

FIG. 7 is a block diagram illustrating an example of a configuration of an error correction decoding circuit according to a second embodiment.

FIG. 8 is a block diagram illustrating an example of an error correction encoding circuit according to a fifth embodiment.

FIG. 9 is a block diagram showing an example of an encoding circuit 802 in FIG. 8;

FIG. 10 is a block diagram illustrating an example of an error correction encoding circuit according to a sixth embodiment.

FIG. 11 is a block diagram showing an example of an encoding circuit 1001 in FIG. 10;

FIG. 12 is a block diagram illustrating an example of an error correction decoding circuit according to a seventh embodiment.

13 is a block diagram showing an example of a soft output decoding circuit 1201 in FIG.

FIG. 14 is a block diagram illustrating an example of an electronic apparatus to which the error correction encoding circuit according to the embodiment is applied.

FIG. 15 is a block diagram illustrating an example of an electronic apparatus to which the error correction decoding circuit according to the embodiment is applied.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03M 13/27 H03M 13/27 13/41 13/41 H04L 1/00 H04L 1/00 BF term (reference) 5J065 AC03 AD10 AE02 AF03 AG05 AG06 AH02 AH04 AH07 AH23 5K014 AA01 AA05 BA10 BA11 FA16 GA00

Claims (49)

[Claims] A first encoding unit that performs error correction encoding of input data; a rearranging unit that rearranges the input data in a predetermined order; and a second encoding unit that performs error correction encoding on an output of the rearranging unit. An error correction coding apparatus comprising: a plurality of types of error correction coding algorithms implemented by sharing the first coding means. 2. The method according to claim 1, wherein the plurality of types of error correction coding algorithms are a first error correction coding algorithm that generates coded data using at least the first coding unit; An error correction encoding apparatus, comprising: a second error correction encoding algorithm that generates encoded data using the first encoding means, the rearrangement means, and the second encoding means. 3. The error correction coding device according to claim 2, wherein the first error correction coding algorithm is a recursive or non-recursive convolutional coding algorithm. 4. The error correction coding device according to claim 2, wherein the second error correction coding algorithm is a turbo coding algorithm. 5. The method according to claim 2, wherein the first encoding unit recursively converts the input data into a convolutional code when implementing the first and second error correction encoding algorithms. An error correction encoding device characterized in that the error correction encoding device performs encoding. 6. The method according to claim 2, wherein the first encoding unit non-recursively performs convolutional encoding of the input data when implementing the first error correction encoding algorithm. An error correction coding apparatus, wherein when the second error correction coding algorithm is realized, the input data is recursively convolutionally coded. 7. The encoding apparatus according to claim 2, wherein the first encoding unit performs the same encoding as the second encoding unit when the second encoding unit implements the second error correction encoding algorithm. An error correction coding device for performing processing. 8. An error correction coding apparatus according to claim 1, wherein said first coding means changes a constraint length in each error correction coding algorithm. 9. The method according to claim 8, wherein the first encoding unit sets a constraint length in the first error correction encoding algorithm to be longer than a constraint length in the second error correction encoding algorithm. An error correction coding device characterized by the above-mentioned. 10. An error correction coding apparatus according to claim 8, wherein said first coding means changes the constraint length of each error correction coding algorithm by controlling the number of delay circuits. . 11. The error correction coding apparatus according to claim 1, further comprising control means for controlling an output of said second coding means, wherein said control means controls an output of said second coding means. An error correction coding device for implementing one of the plurality of types of error correction coding algorithms. 12. An information processing apparatus which performs error correction coding of digital information using the error correction coding apparatus according to any one of claims 1 to 11. 13. A radio communication apparatus for performing error correction coding on digital information using the error correction coding apparatus according to any one of claims 1 to 11. 14. A first encoding step of performing error correction encoding of input data using a first encoding circuit, a rearranging step of rearranging the input data in a predetermined order, and a second encoding step. And a second encoding step of performing error correction encoding on the output of the rearranging step using a circuit, and implementing a plurality of types of error correction encoding algorithms by sharing the first encoding step. An error correction coding method characterized by the following. 15. A first method for performing error correction coding on input data.
An encoding procedure; a rearranging procedure for rearranging the input data in a predetermined order; and a second procedure for error correction encoding the output of the rearranging step.
And a program for implementing a plurality of types of error correction coding algorithms by sharing the first coding procedure. 16. A first method for performing error correction coding on input data.
And a rearrangement unit that rearranges the input data in a predetermined order; and a second encoding unit that performs error correction encoding on an output of the rearrangement unit. Means for implementing a first error correction encoding algorithm using one of the means and the second encoding means, and using the first encoding means and the second encoding means to implement a second error correction encoding algorithm. An error correction encoding device that implements an error correction encoding algorithm. 17. The method according to claim 16, wherein the first error correction coding algorithm is a recursive or non-recursive convolutional coding algorithm, and the second error correction coding algorithm is a turbo coding. An error correction encoding device, which is an algorithm. 18. The error correction coding device according to claim 16, wherein the error correction coding device realizes the first error correction coding algorithm and the second error correction coding algorithm with different constraint lengths. Error correction coding device. 19. The error correction encoding device according to claim 18, wherein the error correction encoding device changes the constraint length of each error correction encoding algorithm by controlling the number of delay circuits. 20. A first method for performing error correction coding on input data.
Encoding step; a rearranging step of rearranging the input data in a predetermined order; and a second step of performing error correction encoding on an output of the rearranging step.
A first error correction encoding algorithm is realized using one of the first encoding step and the second encoding step, and the first encoding step is performed. And a second encoding step for realizing a second error-correcting encoding algorithm. 21. A first method for performing error correction coding on input data.
An encoding procedure; a rearranging procedure for rearranging the input data in a predetermined order; and a second procedure for error correction encoding the output of the rearranging step.
And a first error correction coding algorithm is realized using one of the first coding procedure and the second coding procedure, and the first coding procedure is performed. A storage medium storing a program for realizing a second error correction coding algorithm using the first coding procedure and the second coding procedure. 22. A rearrangement unit for rearranging input data in a predetermined order; and an encoding unit for performing error correction encoding on at least one of the input data and an output of the rearrangement unit. An error correction encoding device characterized by realizing a plurality of types of error correction encoding algorithms by controlling the error correction encoding algorithm. 23. The error correction encoding algorithm according to claim 22, wherein the plurality of types of error correction encoding algorithms include: a first error correction encoding algorithm that performs error correction encoding on at least one of the input data and an output of the reordering unit; An error correction coding device, comprising: a second error correction coding algorithm for performing error correction coding on both the input data and the output of the reordering means. 24. The method according to claim 23, wherein the first error correction coding algorithm is a recursive or non-recursive convolutional coding algorithm, and the second error correction coding algorithm is a turbo coding. An error correction encoding device, which is an algorithm. 25. The method according to claim 22, wherein
The error correction coding device, wherein the first error correction coding algorithm and the second error correction coding algorithm are realized with different constraint lengths. 26. The error correction coding device according to claim 25, wherein the error correction coding device changes the constraint length of each error correction coding algorithm by controlling the number of delay circuits. 27. A rearranging step of rearranging input data in a predetermined order, and an encoding step of performing error correction encoding on at least one of the input data and an output of the rearranging step using an encoding circuit. An error correction encoding method comprising: controlling the encoding step to implement a plurality of types of error correction encoding algorithms. 28. A rearranging procedure for rearranging input data in a predetermined order; and an encoding procedure for error-correcting and encoding at least one of the input data and an output of the rearranging step. Characterized by storing a program for controlling a plurality of types of error correction coding algorithms by controlling the program. 29. A first decoding means for soft-output decoding input data, a first sorting means for sorting the output of the first decoding means in a predetermined order, and a first sorting means. A second decoding means for soft-output decoding the output; and a second sorting means for sorting the output of the second decoding means in an order corresponding to the first sorting means. An error correction decoding device, wherein an error correction decoding algorithm is realized by sharing said first decoding means. 30. The method according to claim 29, wherein the plurality of types of error correction encoding algorithms are a first error correction decoding algorithm for decoding the input data using the first decoding means, and the first decoding. And a second error correction decoding algorithm for decoding the input data using both the first means and the second decoding means. 31. The error correction decoding device according to claim 30, wherein when the first error correction decoding algorithm is realized, an output of the first decoding means is used as a decoding result, and An error correction decoding apparatus characterized in that when realizing a correction decoding algorithm, an output of the second rearranging means is used as a decoding result. 32. The error correction decoding device according to claim 30, wherein the first error correction decoding algorithm is a Viterbi decoding algorithm. 33. The error correction decoding device according to claim 30, wherein the second error correction decoding algorithm is a turbo decoding algorithm. 34. In any one of claims 30 to 33,
An error correction decoding device, wherein the first decoding means performs the same decoding processing as the second decoding means when implementing the second error correction decoding algorithm. 35. In any one of claims 30 to 34,
An error correction decoding device characterized in that the first error correction decoding algorithm and the second error correction decoding algorithm decode error correction codes having different constraint lengths. 36. The error correction decoding device according to claim 35, wherein the first error correction decoding algorithm decodes an error correction code having a longer constraint length than the second error correction decoding algorithm. 37. An error correction decoding apparatus according to claim 35, wherein said first decoding means realizes the plurality of types of error correction decoding algorithms by switching the contents of a table. 38. An error correction decoding apparatus according to claim 35, wherein said first decoding means realizes said plurality of types of error correction decoding algorithms by controlling the number of delay circuits. 39. The method according to claim 29, wherein
The error correction decoding device further includes control means for controlling an output of the second decoding means, and realizes one of the plurality of types of error correction decoding algorithms according to an operation of the control means. Error correction decoding device. 40. An information processing apparatus for decoding a predetermined error correction code using the error correction decoding apparatus according to any one of claims 29 to 39. 41. A wireless communication apparatus that decodes a predetermined error correction code using the error correction decoding apparatus according to claim 29. 42. A first decoding step of soft-output decoding input data using a first decoding circuit; a first rearranging step of rearranging the output of the first decoding step in a predetermined order; A second decoding step of soft-output decoding the output of the first reordering step using a second decoding circuit; and converting the output of the second decoding step into an order corresponding to the first reordering step. And a second rearrangement step of rearranging, wherein a plurality of types of error correction decoding algorithms are realized by sharing the first decoding step. 43. A first decoding procedure for soft-output decoding input data, a first sorting procedure for sorting the output of the first decoding procedure in a predetermined order, and an output of the first sorting procedure. A second decoding procedure for soft-output decoding, and a second rearranging procedure for rearranging the output of the second decoding procedure into an order corresponding to the first rearranging procedure. A storage medium storing a program for realizing a correction decoding algorithm by sharing the first decoding procedure. 44. A first decoding unit for soft-output decoding input data, a first rearrangement unit for rearranging the output of the first decoding unit in a predetermined order, and a first rearrangement unit. A second decoding unit for soft-output decoding the output; and a second rearranging unit for rearranging the output of the second decoding unit in an order corresponding to the first rearranging unit. Wherein the first error correction decoding algorithm is realized without using the decoding means, and the second error correction decoding algorithm is realized using the first decoding means and the second decoding means. Error correction decoding device. 45. The error correction decoding device according to claim 44, wherein the first error correction decoding algorithm is a Viterbi decoding algorithm, and the second error correction decoding algorithm is a turbo decoding algorithm. . 46. The error correction decoding according to claim 44, wherein the first error correction decoding algorithm and the second error correction decoding algorithm decode error correction codes having different constraint lengths. apparatus. 47. The method according to claim 46, wherein the first decoding means implements the plurality of types of error correction decoding algorithms by switching the contents of a table or controlling the number of delay circuits. Error correction decoding device. 48. A first decoding step of soft-output decoding input data, a first rearranging step of rearranging an output of the first decoding step in a predetermined order, and a first rearranging step of the first rearranging step. A second decoding step of soft-output decoding the output; and a second rearranging step of rearranging the output of the second decoding step in an order corresponding to the first rearranging step. A first error correction decoding algorithm is realized without using the decoding step, and a second error correction decoding algorithm is realized using the first decoding step and the second decoding step. Error correction decoding method. 49. A first decoding procedure for soft-output decoding input data, a first rearranging procedure for rearranging the output of the first decoding procedure in a predetermined order, and a first rearranging procedure for the first rearranging procedure. A second decoding procedure for soft-output decoding the output; and a second rearrangement procedure for rearranging the output of the second decoding procedure into an order corresponding to the first rearrangement procedure. A program for realizing the first error correction decoding algorithm without using the decoding procedure of the above and storing the program for realizing the second error correction decoding algorithm using the first decoding procedure and the second decoding procedure is stored. A storage medium characterized by the following.