JP2001094440A - Error correction decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error correction decoder where a configuration of the coder is simplified by eliminating the need for processing of adding a tail bit in a trellis termination processing and deterioration in a coding rate can be prevented. SOLUTION: The error correction decoder that applies error correction to a received sequence resulting from receiving a code sequence obtained through organized convolution coding via a transmission line with an error, is provided with an ACS path-metric difference arithmetic section 401 that applies processing to a received signal while going back to a past point of time to obtain a survival path, a path memory 402 that stores signals in the order from a signal resulting from data as to the obtained survival path to a signal received in the past in cross-reference with addresses, and an ML path trace hard decision section 403 and a contention path trace soft output calculation section 404 that use an address of a signal received at the easily time for a start point as to the stored survival path to apply trace processing in the order of the received sequence.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction decoder.

[0002]

2. Description of the Related Art When an information sequence generated from a predetermined information source is transmitted through a transmission line having an error, it is generally practiced to encode the information sequence by adding redundancy and transmit it. For coding, the information sequence is divided into blocks of a certain length, and the coding of each block is performed independently of the coding of other blocks. Involves tree coding.

In the tree coding, coding performed in consideration of the state σt of the encoder at an arbitrary time t is called trellis coding, and the transition state of a code sequence obtained by trellis coding is represented by a trellis diagram. It is known that it can be expressed. A linear trellis code is called a convolutional code.

By the way, a process of terminating a trellis code at the time of trellis encoding is performed so that the decoding side knows a starting point when decoding a convolutionally encoded code sequence.
The trellis termination process is a process of resetting the state of the encoder to an all-zero state. In the case of a non-recursive code, 0 is added to the information bits as tail bits by the number of shift registers in the encoder. Termination can be performed.

However, in the case of a recursive code, trellis termination processing cannot be performed simply by adding such a tail bit, and a complicated mechanism must be used as described below. Further, a turbo coder is known as a configuration in which two recursive encoders are connected. In such a turbo coder, the state of the two encoders needs to be set to zero, so that trellis termination processing is more complicated. Become.

FIG. 7 is a diagram showing the configuration of the above-mentioned turbo coder, in which a first encoder 10A and a second encoder 10B are connected via an interleave processing unit 11. The first encoder 10A includes a switch 12A,
It comprises adders 13A and 16A, and delay units (D) 14A and 15A composed of shift registers. Similarly to the first encoder 10A, the second encoder 10B has a switch 12B.
, Adders 13B and 16B, and a delay unit (D) 14B, 1
5B.

When the information bits I constituting the information sequence input to the first encoder 10A are encoded by adding a parity bit, the switch 12A is closed, but the encoding of the information bits I is completed. Sometimes, the switch 12A is opened and the number of the tail bits Y1,
Y2 is transmitted.

The information bit I is also input to an interleave processing unit 11, where data is rearranged based on a predetermined rule, and then input to a second encoder 10B to be input to a first encoder 10A. The same processing as described above is performed.

However, when such a configuration is used, the switches 12A, 12A
B needs to be switched at a predetermined timing,
Also, as can be seen from the figure, the encoded information bits and tail bits are output from different output positions,
A new circuit for combining these two bits is required, which complicates the configuration of the encoder.

It is also known to add a known information bit as a tail bit without performing the trellis termination processing of the turbo coder, thereby preventing performance degradation when the termination processing is not performed. However, in this case, it is necessary to add a sufficiently long tail bit, and as a result, there is a disadvantage that the coding rate is reduced.

[0011]

As described above, when performing trellis termination processing of a recursive code used in a turbo coder, it is sufficient to complicate the configuration of the encoder or to avoid trellis termination processing. There is a problem that a long tail bit is required and the coding rate is reduced.

The present invention has been made in view of such a problem, and an object of the present invention is to eliminate the need for a process of adding tail bits, simplify the configuration of an encoder, and reduce the coding rate. It is an object of the present invention to provide an error correction decoder capable of preventing a decrease in the error.

[0013]

In order to achieve the above object, an error correction decoder according to a first aspect of the present invention converts a code sequence obtained by performing systematic convolutional coding through a transmission path having an error. In an error correction decoder that performs error correction on a received reception sequence, an addition / comparison / selection unit that performs processing retroactively from a received signal to obtain a surviving path, and an addition / comparison / selection unit that obtains a surviving path. Storing means for storing the data on the surviving path in the order of signals received in the past from the signal received in the past in association with the address, and the signal received most recently in the surviving path stored in the storing means. And a tracing means for performing a tracing process in the order of the reception sequence starting from the address of (i).

In the error correction decoder according to a second aspect of the present invention, in the first aspect, the storage means stores data corresponding to a predetermined length of time, and stores the data corresponding to the stored predetermined time. Then, the tracing process by the tracing means is repeatedly performed to perform error correction on the entire reception sequence.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of a turbo decoder to which the error correction decoder of the present invention is applied.
As shown in FIG. 1, the turbo decoder has two soft-input soft-output decoders in order to improve error correction capability.
The first soft-input / soft-output decoder 305 includes a memory 301A for storing information bits I of a reception sequence received via a transmission path having an error, from a code sequence obtained by performing systematic convolutional encoding; First parity bit Y1 of the sequence
, And the output of the memory 310 for storing the external information likelihood is received as a soft input, the decoding process is performed, and the soft decision result is output to the adder 309. The adder 309 performs an addition operation by using the output of the memory 301A, the output of the soft-input soft-output decoder 305, and the output of the deinterleaver 304 for performing a process of returning the signals rearranged by the interleaver to the original arrangement. The result is output to an interleaver 303B for rearranging the signals.

The second soft-input soft-output decoder 306
Is a signal obtained by rearranging the output of the memory 301A by the interleaver 303A, a signal obtained by rearranging the output of the adder 309 by the interleaver 303B, and a memory 301C for storing the second parity bit Y2 of the received sequence. The output is received as a soft input, decoding processing is performed, and a soft decision result is output to the adder 307. The adder 307 includes an output of the second soft-input soft-output decoder 306, a signal obtained by rearranging the output of the memory 301A by the interleaver 303A, and an adder 3
An addition operation is performed by using as input the signal obtained by rearranging the output of the interleaver 09 in the interleaver 303B and outputting the result to the deinterleaver 304. Further, the hard-decision output unit 308 converts the soft-decision output (multi-valued data) of the second soft-input soft-output decoder 306 into a corresponding hard-decision output (binary data) and outputs it.

FIG. 2 is a diagram showing the configuration of the first soft-input soft-output decoder 305 and the second soft-input soft-output decoder 306 described above. In FIG. 2, ACS (Add Compare Sel
ect) A first output of the path metric difference calculation unit 401 is stored in a path memory 402 as a storage unit, and a second output is M
L (Most Likelihood) path trace / hard decision unit 403
The third output is a competing path trace / soft output calculator 40.
4 is connected. Further, the path memory 402 sends the ML (Most) directly to the competing path trace / soft output calculator 404.
Likelihood) is connected via a path trace / hard decision unit 403.

The ACS (Add Compare Select) / path metric difference calculation unit 401 calculates the path metric by cumulatively adding the branch metrics obtained for all the branches in the trellis diagram, and calculates the path metric of each path. And selects the path metric that gives the maximum likelihood as the surviving path. By calculating the difference Δ between the path metrics of the two paths flowing into each state, the difference between the path metrics is obtained for all surviving paths.

However, the ACS processing here is performed by SOVA (S
As shown in FIG. 3, data is input in the reverse order to the received sequence using the
Processing is performed. That is, as shown by → in FIG. 3, from the received signal received at the latest time point t, ACS processing is performed retroactively to time points t-1, t-2,. ing. As a result, the surviving path obtained by the ACS processing is stored in the path memory 402 in association with the address in the order from the most recently received signal to the previously received signal.

Next, the ML path trace / hard decision unit 403 and the competing path trace / soft output calculation unit 404 as tracing means determine the most recently received signal based on the surviving path stored in the path memory 403. The trace processing is executed in the order of the reception sequence starting from the address. Here, the conventional trace processing is called trace back, and trace processing is performed on a received signal in the past in the reverse order of the received sequence, that is, starting with the most recently received data as a start point. However, in the present embodiment, as indicated by → in the trellis diagram of FIG. 4, the trace processing is performed in the order of the reception sequence from the most recently received signal to time points 0, 1, 2, 3, to t−1, t. It is characterized by executing. Here, the state where the trace processing is started is performed from S0. This is because, since the initial state of the encoder is 0, when the trace processing is performed from the state S0, the reliability is improved.

The error correction decoder according to the present embodiment is constituted by a turbo decoder, and it is necessary to store a received sequence in the path memory 402 in order to perform an interleave process. On the other hand, since the received sequence is stored in this way, the address position (state S0) for starting the trace processing can be easily searched. further,
Since the trace processing only needs to be performed up to the end of the received data, the present embodiment can be applied regardless of whether a tail bit at the trellis end is added to the received sequence as in the related art.

In practice, the path memory 402 stores data corresponding to a predetermined length of time called a window,
The trace processing is repeated by the tracing means for each of the stored data for a predetermined time, thereby performing error correction on the entire reception sequence.

Further, the final state of the trace processing (S3)
Can increase the reliability by setting the trace length sufficiently long.

The tracing process of this embodiment will be described below in detail with reference to FIG. Trace processing unit 705
In the ML path trace processing, the path memory 40
2 is selected, and the conflicting path 702 is selected by the conflicting path trace processing. Next, the selected ML path 701 and the competing path 702 are compared with each other, and a soft output calculation unit 703 that performs a soft output calculation is notified of a trellis transition position that gives a different decoding result. The soft output calculation unit 703 determines the ACS / path metric calculation unit 4 for different bit positions of the ML path 701 and the contention path 702.
The difference between the path metric from 01 and the currently stored value is compared, and the smaller one is selected and stored. The output of the soft output calculator 704 and the code decoded by the ML path 701 are multiplied by the multiplier 704 and output as a soft decision output (multi-valued data).

FIG. 6 is a diagram showing a configuration of a turbo coder corresponding to the turbo decoder of the present embodiment. FIG.
As can be seen from the above, the use of the above-described decoding method eliminates the need to add tail bits, and thus eliminates the need for a switch that performs switching processing when adding tail bits, a circuit that combines information bits and tail bits, and the like. The configuration of the coder is simplified. The initial value of the turbo coder is all zero.

As described above, in the turbo decoder, the ACS processing is performed in the reverse order of the reception sequence, and the trace processing is performed in the reception sequence. Therefore, the configuration of the turbo coder is simplified, and the coding rate is reduced. Can be terminated without reducing.

[0027]

According to the present invention, in the decoding process in the error correction decoder, the ACS process is performed in the reverse order of the received sequence, and the trace process is performed in the received sequence order. It is not necessary to add a bit, thereby simplifying the configuration of the encoder and terminating the trellis code without reducing the coding rate.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a turbo decoder to which an error correction decoder according to the present invention is applied.

FIG. 2 is a diagram showing a configuration of a first soft-input soft-output decoder 305 and a second soft-input soft-output decoder 306 shown in FIG.

FIG. 3 is a trellis diagram for explaining a procedure of an ACS process according to the embodiment.

FIG. 4 is a trellis diagram for explaining a procedure of a trace process according to the embodiment;

FIG. 5 is a diagram illustrating a trace process according to the embodiment;

FIG. 6 is a diagram illustrating a configuration of a turbo coder corresponding to the turbo decoder of the present embodiment.

FIG. 7 is a diagram showing a configuration of a conventional turbo coder.

[Explanation of symbols]

 301A, 301B, 301C, 303A, 303B: interleaver, 304: deinterleaver, 305, 306: soft input / soft output decoder, 307: adder, 308: hard decision output unit, 309: adder, 310: memory, 401 ... ACS / path metric difference calculation unit, 402: path memory, 403: ML path trace / hard decision unit, 404: competitive path trace / soft output calculation unit.

Claims (2)

[Claims] An error correction decoder for correcting a code sequence obtained by systematic convolutional coding on a received sequence received via a transmission line having an error, comprising: Adding and selecting means for performing a process retroactively to obtain a surviving path, and storing the data on the surviving path obtained by the adding and comparing and selecting means in association with the address in the order of the received signal from the previously received signal. And a surviving path stored in the preserving means.
And a tracing means for performing a tracing process in the order of a received sequence starting from an address of a signal received most recently as a start point. 2. The storage means stores data corresponding to a predetermined length of time, and repeats the tracing process by the tracing means for each of the stored data for the predetermined time to correct an error in the entire reception sequence. 2. The error correction decoder according to claim 1, wherein the decoding is performed.