KR20020066759A - Processor and method for implementing MAP algorithm used in a turbo decoder - Google Patents

Abstract

PURPOSE: A MAP(Maximum A-Posteriori) algorithm embodying processor for a turbo decoder and a method for embodying the MAP algorithm are provided to process high speed data and reduce a complexity of a hardware by embodying the maximum normalized throughput instead of a full-speed architecture necessary for hardware and memory architecture of a low throughput. CONSTITUTION: In a MAP algorithm embodying processor for a turbo decoder for receiving a branch metric and outputting extrinsic information, the first ACS(Add-Compare-Select) block(10) performs a recursive Add-Compare-Select calculation and outputs a reverse state metric with respect to a sub frame which is sectioned into a plurality of sections from one flame of the branch metric. The second ACS block(20) performs a recursive Add-Compare-Select calculation and outputs a forward state metric. The third ACS block(30) makes the output of the first ACS block(10) as an initial value, performs a recursive Add-Compare-Select calculation, and outputs a reverse state metric with respect to the sub frame. A plurality of buffers(61-64) stores the sub frames being inputted successively and shifts the sub frames successively, and inputs the sub frames in the first, second, and third ACS blocks(10,20,30). An LLRE(Log Likelihood Ratio Evaluator) block(40) performs an Add-Compare-Select calculation with respect to an output of the second and third ACS blocks(20,30) and an output of the buffer for storing data being inputted in the third ACS block(30), and outputs extrinsic information.

Description

Processor and method for implementing MAP algorithm used in a turbo decoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor for implementing a map algorithm for a turbo decoder and a method for implementing the same. will be.

In general, in wireless digital communication, an error correction code is applied at a transmitter and a decoder is used to correct an error on a channel. One of such error-correctable coding schemes is turbo code. Turbocode has been adopted for channels that require high data rates in US CDMA2000 and W-CDMA for Europe. The turbo code is known to be very close to the Shannon limit, which is a theoretical limit by performing repeated decoding even at low reception power. The turbo code decoding methods include SOVA (Soft-Output Viterbi Algorithm) and MAP (Maximum A Posteriori). The MAP method is 0.3 dB in AWGN (Additive White Gaussian Noise), which has better channel environment than SOVA. In addition, it is known to have a coding gain of about 3 dB higher in a Rayleigh Fading environment where the channel environment is not good.

1 shows a turbo encoder for generating a general turbo code, and shows a turbo encoder with R = 1/3. The turbo encoder is composed of two parallel concatenated Recursive Systematic Convolutional (RSC) blocks (RSC1, RSC2) and one interleaver. The information bit sequence d _k is input to the first RSC block RSC1, and the RSC block RSC1 generates the first parity bit string Y _1k . The information bit sequence d _k is simultaneously input to an interleaver and stored in units of frames. The information bit sequence d _k input to the interleaver is interleaved by the interleaver, and the interleaved information bit sequence d _k ′ is input to the second RSC block RSC2. The RSC block RSC2 generates a second parity bit string Y _2k .

The input information bit sequence (d _k) is as the output X _k and the first and second parity bit stream Y _1k, Y _2k haphaejyeo code sequences _{(X 1, Y 11, Y} 21, X 2, Y 12, Y 22 , X ₃ , Y ₁₃ , Y ₂₃ ,...) Is generated, and the code rate R = 1/3. The code sequence is modulated by binary phase shift keying (BPSK) and transmitted on the channel. That is, the code sequences of 1 and 0 are transmitted on the channel after being changed to the transmission symbols of +1 and -1.

Various noises are added to the transmission symbol received through the channel. This can be expressed as a formula.

x _k = (2X _k -1) + P _k

y _k = (2Y _k -1) + Q _k

Where X _k and x _k are the transmitted information bit stream and the received information symbol stream, respectively, Y _k and y _k are the transmitted parity bit stream and the received parity symbol stream, respectively, and P _k and Q _k are independent of each other. Noise.

A general block diagram of a turbo decoder using the MAP method may be represented in the form of serial concatenated two map decoders Dec1 and Dec2 (MAP decoder) as shown in FIG. 2. The principle of such a turbo decoder is as follows.

Assume that the received symbol sequence of one frame is R ^N ₁ . At this time,

R ^N ₁ = (R ₁ , ....., R _k , ...., R _N )

It can be expressed as

Where R _k = (x _k , y _k ) and receive symbols at time k.

The likeligood ratio λ _k associated with the decoded d _k is defined as follows.

λ _k = P (d _k = 1 | R ^N ₁ ) / (P (d _k = 0 | R ^N ₁ )

Here, i = 0,1 and P (d _k = i | R ^N ₁ ) is APP (A Posteriori Probability) of the information bit d _k . The MAP method is a method in which this APP selects the information bit _dk that is maximum.

The first map decoder (Dec1) has a priori probability ratio L _a (d _k ) of the information bits d _k , a value L (x _k ) for the received information symbol, and parity by the first encoder (RSC1). Extrinsic Information of the information bit d _k is generated with the value L (y _1k ) for the reception symbol. In a first iteration, L _a (d _k ) of the first map decoder Dec1 becomes zero. Because the value of d _k consists of 1 or 0, the ratio is (1/2) / (1/2) because the transmit probability of 1 and the prior probability of 0 can be assumed to be equal 1/2. This is because log1 = 0 is calculated in the log domain. L (x _k ) and L (y _1k ) are the product of x _k and y _1k multiplied by Channel Reliability (L _c ). With this input value, the output L ₁ (d _k ) of the first map decoder Dec1 has a combination of terms as shown in the following equation.

L ₁ (d _k ) = L _a (d _k ) + L (x _k ) + L _e1 (d _k )

Here, L _a (d _k ) and L (x _k ) terms are input terms. If the terms are subtracted from the output, external information generated by the first map decoder Dec1 is L _e1 (d _k ). do. This term is a term related to each d _k and is used as a prior probability ratio of information bits in the second map decoder Dec2.

A priori probability ratio L _a (d _k) of a look at the input of the second map decoders (Dec2) of the first repetition information bit (d _k) becomes the L _e1 (d _k) obtained from the first map decoder (Dec1), the receiving The value L (x _k ) for the information symbol and the value L (y _2k ) for the reception symbol of parity by the second RSC block (RSC2) are input. In this case, since the reception parity symbol L (y _2k ) is obtained from the interleaved state at the transmitter, the external information L _e1 (d _k ) and the information symbol value L (x) of the first map decoder Dec1 used as a pre-probability ratio value are used. _k ) is decoded by interleaving. The output L ₂ (d _k ) of the second map decoder Dec2 is a combination of the following terms.

L ₂ (d _k ) = L _a (d _k ) (= L _e1 (d _k )) + L (x _k ) + L _e2 (d _k )

L _e2 (d _k ) is external information generated by the second map decoder Dec2 and used as a prior probability ratio value of the first map decoder Dec1 in the second iteration.

And, the equation required to implement the MAP algorithm for the iterative turbo decoding as described above is as follows. The following equation is expressed in the log-domain.

D _k =-(z _k + L _c x _k ) d _k -L _c y _k c _k

A _{k, m} = min * (A _{k-1, b (0, m)} + D _{k-1, b (0, m)} , A _{k-1, b (1, m)} + D _{k-1, b (1, m)} )

B _{k, m} = min * (B _{k + 1, f (0, m)} + D _{k, f (0, m)} , B _{k + 1, f (1, m)} + D _{k, f (1, m )} )

L _k = min * (A _{k, m} + D _{k, f (0, m)} + B _{k + 1, f (0, m)} | ∀ _m )-min * (A _{k, m} + D _{k, f ( 1, m)} + B _{k + 1, f (1, m)} ｜ ∀ _m )

min * (A, B) = min (A, B) log _e (1 + e- ^{| AB |} )

The terms used above are as follows.

Let k be the time, m be the status, d _{k be the} information bits, and c _{k be the} corresponding parity bits,

b (d _k , m) and f (d _k , m) are the reverse and forward state values,

L _c is channel reliability = 2 / σ ² (σ ² is noise variance in AWGN),

D _k , A _{k, m} and B _{k, m} are branch, forward, and reverse state metrics, and

∀ _m means all states m.

This can only be achieved with one receive symbol received. This requires a large amount of memory because it must store both forward and reverse state metrics. For example, if a frame is 5000 bits, the number of states is 8, and 8 bits are used to represent a state, 320,000 bits of memory are required, and all receive symbols to implement the state metrics of a frame. This requires a large amount of time to decode, resulting in a long decoding delay.

In order to solve such a problem, the sliding window method has been proposed in the form of the forward state metric as before and reducing the calculation direction of the reverse state metric. It is known that this scheme has only about 0.1 to 0.2 dB of degradation compared to the case where the entire frame is decoded with all the received frames. A conventional MAP decoder implemented using this scheme is shown in FIGS. 3 and 4.

FIG. 3 illustrates a MAP algorithm implementation processor (corresponding to the map decoders Dec1 and Dec2 described above) for a turbo decoder in a full-speed architecture. One frame size of the reception symbol is referred to as N, and a subframe size obtained by dividing one frame into a predetermined size is referred to as N _sub . In FIG. 3, L (x _k ) and L (y _k ) required to calculate the branch metric are input with a buffer having a length of 2N _sub . The forward state metric is calculated through the time delay during 2N _sub , and the backward state metric corresponding to one forward state metric is finally calculated after 2N _sub . The soft output for the first decoding bit is calculated. Subsequently, the soft output of all decoded bits is calculated in this way. When calculating the reverse state metric, the initial values of all states are kept the same. This architecture requires a large amount of computation (to calculate the reverse state metric) to calculate the soft output of one decoding bit, and also requires a large number of Add-Compare-Select (ACS) blocks. In other words, the number of states × 2 × N _sub backward Add-Compare-Select (ACS) blocks are required. If N _sub = 16 and the number of states = 8, 256 ACS blocks are required. .

As another example of the prior art, a processor for implementing a map algorithm for a turbo decoder of a memory architecture is shown in FIG. 4. In the example shown in FIG. 4, using three branch metric storage RAMs (each capacity is N _sub , i.e., a capacity of 3N _sub total length) and as many forward state metric storage RAMs as the number of states, You can reduce the amount of health metrics and the number of ACS. The operation steps are as follows.

In the first step, the first block of length N _sub is stored in RAM1, and the second block of length N _sub is stored in RAM2.

In the second step, a third block of length N _sub is stored in RAM3, and at the same time, the reverse state metric is calculated in reverse order using the branch metric in RAM2 (beta 1), and the forward state using the branch metric in RAM1. Calculate the metric and store it in aRAM (alpha).

The third step is to read the forward state metric in aRAM in reverse, calculate the reverse state metric using the branch metric in RAM1 (Beta 2), and apply the LLR for the associated decoded bit. Find the Log-Likelihood Rate (AP) or A Posteriori Probability (APP) value. At the same time, a fourth block of length N _sub is stored in RAM1. This approach has tremendous and complex control because it requires a read read-modify-write to read and store branch metrics to compute the reverse state metric. Of course, this is the case for RAM1, RAM2, RAM3, and aRAM. The RAM2 reads to calculate the forward state metric (alpha) and the RAM3 reverse state metric (beta1).

In the fourth step, the same as in the third step, except that the RAM you store and read is different.

However, such a structure has low processing efficiency (read & write) at the same address in controlling aRAM (forward state metric storage memory) and RAMs 1, 2, and 3. low throughput) and control complexity.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a full-speed architecture that requires a large amount of hardware and a complex structure thereof, and low work processing. Unlike memory architecture, where high speed data processing is difficult due to low thruoghput, the turbo algorithm's map algorithm reduces hardware complexity while maximizing normalized throughput. An implementation processor and a map algorithm implementation method are provided.

1 is a block diagram of a conventional turbo encoder,

2 is a block diagram of a conventional turbo decoder;

3 is a block diagram showing an example of a conventional map algorithm implementation processor for a turbo decoder;

4 is a block diagram showing another example of a map algorithm implementing processor of a conventional turbo decoder;

5 is a block diagram of a map algorithm implementing processor for a turbo decoder according to the present invention;

FIG. 6 is a diagram illustrating an operation sequence for each subframe in one frame performed by the turbo decoder implementation algorithm for map decoder shown in FIG. 5.

Explanation of symbols on the main parts of the drawings

10, 20, 30, 40: ACS block 11, 21, 31: multiplexer

61, 62, 63, 64: Buffer 50, 70: LIFO block

The above object is a recursive Add-Compare-Select in a turbo decoder MAP algorithm implementation processor which receives a branch metric and calculates extrinsic information according to the present invention. A first ACS block for performing reverse arithmetic operation to calculate a reverse state metric for a subframe in which one frame of the branch metric is divided into a plurality of frames; A second ACS block for performing a recursive add-compare-select operation to calculate a forward state metric for the subframe; A third ACS block configured as an initial value of the output of the first ACS block, and performing a recursive add-compare-selection operation to calculate a reverse state metric for the subframe; A plurality of buffers for storing the subframes sequentially input and shifting the subframes sequentially and inputting the subframes to the first to third ACS blocks; And performing an add-compare-selection operation on the outputs of the second and third ACS blocks and the output of the buffer for storing data input to the third ACS block, thereby calculating the LLRE block. It is achieved by a MAP algorithm implementation processor for a turbo decoder.

Here, the initial value of the first ACS block takes the same value for all states, and the initial value of the second ACS block takes 1 (0 on the road domain) for the '0' state and the non-zero state. Takes 0 (-∞ on road domain). The output of the LLRE block is last-in-first-out by the second LIFO block, so that the external information is output.

According to the present invention, there is provided a turbo decoder having a smaller circuit size, simpler control, and higher throughput than a conventional MAP architecture.

On the other hand, according to the present invention, there is provided a MAP algorithm implementation method performed by the MAP algorithm implementation processor for a turbo decoder as described above.

Hereinafter, with reference to the drawings will be described the present invention in more detail. The present invention will be described with reference to the turbo encoder and turbo decoder shown in FIGS. 1 and 2 together.

5 is a block diagram showing the structure of a MAP algorithm implementation processor for a turbo decoder according to the present invention. The MAP algorithm implementation processor according to the present invention is a part corresponding to the first map decoder Dec1 or the second map decoder Dec2 in the turbo decoder as shown in FIG. 2. Thus, in the processor according to the present invention, the prior probability ratio L _a (d _k ) of the information bits in the received turbo code, the received information symbol L (x _k ), and the received parity symbol L (y _1k ) or L (y _2k )), and as described above in the description of the prior art, which is Extrinsic Information,

L ₁ (d _k ) = L _a (d _k ) + L (x _k ) + L _e1 (d _k ) or output (for Dec 1),

L ₂ (d _k ) = L _a (d _k ) (= L _e1 (d _k )) + L (x _k ) + L _e2 (d _k ) is output (in Dec 2).

As shown in FIG. 5, the MAP algorithm implementation processor according to the present invention includes a first ACS block 10 and a third ACS block 30 for obtaining a reverse state metric, and a second ACS block for obtaining a forward state metric. (20), first to fourth buffers 61, 62, 63, and 64 for sequentially providing subframes to the first to third ACS blocks 10, 20, and 30, and the second ACS block 20; External information using the first LIFO block 50, the output of the first LIFO block 50, the output of the fourth buffer 64, and the output of the third ACS block 30, which are inputted to the output of the first-in-first-out. A Log Likelihood Ratio Evaluator (LLRE) block 40 for calculating Information, and a second LIFO block 70 for inputting-out the output of the LLRE block 40.

Each of the first to third ACS blocks 10, 20, and 30 includes one multiplexer 11, 21, 31, and one ACS operator 11, 21, 31.

The multiplexer 11 in the first ACS block 10 is input with a predetermined initial value for obtaining the reverse state metric and the feedback of the output of the ACS operator 13, and the multiplexer 11 selects one of these inputs for ACS. It is input to the calculator 13. The multiplexer 11 selects an initial value (all '0') at the first operation of the first ACS block 10 and inputs it to the ACS operator 13, and at the subsequent operation, the value returned from the ACS operator 13 Is selected and input to the ACS operator 13. Accordingly, a recursive add-compare-select operation is performed to calculate a state metric for the input branch metric.

That is, one ACS operator 13 adds two previous backward state values and a branch metric value related to the state values, compares the added values with each other, and selects an appropriate value therefrom. The reverse state value is continually improved by performing an Add-Compare-Select operation.

The configuration and operation of the second ACS block 20 and the third ACS block 30 are also the same as the configuration and operation of the first ACS block 10 as described above. However, the first and third ACS blocks 10 and 30 are used to obtain a reverse state metric as described below, and the second ACS block 20 obtains a forward state metric. Used to get

The Log Likelihood Ratio Evaluator (LLRE) block 40 is a block for calculating a log likelihood ratio, and may include, for example, one ACS operator, one compare-select (CS) operator, and one subtractor. The LLRE block 40 performs an operation of maximizing the APP of one decoded bit in the load domain.

If a map processor is implemented in state-parallel form, the required number of first ACS block 10 and third ACS block 30 to obtain the reverse state metric is twice the number of states. The required number of second ACS blocks 20 for obtaining the forward state metric is equal to the number of states.

Also, when the symbol size of one frame of the input signal is N and the symbol size of the subframe obtained by dividing one frame into a predetermined size is N _sub , the capacity of each buffer 61, 62, 63, and 64. Is N _sub × 4 × 2 × [number of bits of branch metric], and the capacity of the first LIFO block 50 is N _sub × [number of states] × [number of bits of state metric], and the second LIFO block ( The capacity of 70) is N _sub x [the number of bits of the state metric].

Input signals are stored in the first buffer 61 in subframe units, and when the first subframe is stored in the first buffer 61, the data stored in the first buffer 61 is parallel to the second buffer 62. Is shifted and loaded. Similarly, the third and fourth buffers 63 and 64 are shifted sequentially in one subframe unit. Accordingly, the input signal is sequentially shifted and loaded from the first buffer 61 to the second, third, and fourth buffers 62, 63, and 64 in subframe units.

In addition, the data stored in the second buffer 62 is input to the ACS operator 13 in the first ACS block 10 in a reverse direction with respect to the input direction of the data entered into the first buffer 61. An operation for calculating a reverse state metric of the first ACS block 10 is performed on the data stored in 62. The data stored in the third buffer 63 is forwarded to the ACS operator 23 in the second ACS block 20 to perform a forward state metric calculation operation by the second ACS block 20. The data stored in 64 is input in the reverse direction to the ACS operator 33 in the third ACS block 30 so that the reverse state metric calculation operation by the third ACS block 30 is performed.

FIG. 6 illustrates, in stages, the order of calculating the forward state metric and the reverse state metric for each subframe when the MAP algorithm executed by the turbo decoder MAP algorithm processor as shown in FIG. 5 is performed. Drawing. The number shown in each stage in FIG. 6 is the number of the subframe processed in the stage. For example, N0 represents a first input subframe and N1 represents a second input subframe. In addition, a bar indication on a subframe indicates that a backward state metric is obtained, and a subframe number without a bar indicates that a forward state metric is obtained for the subframe. In addition, the 'alpha' column indicates a subframe that calculates the forward state metric in the second ACS block 20, and the 'beta-1' and 'beta-2' columns correspond to the first ACS block 10 and the second, respectively. 3 In the ACS block 30, a subframe for calculating the reverse state metric is indicated. The 'input' column outputs the subframe input to the first buffer 61, the 'lambda' column outputs the subframe output from the LLRE block 40, and the 'output' column outputs the second LIFO block 70. Indicates a subframe.

Hereinafter, a process of implementing the MAP algorithm according to the present invention will be described for each stage.

First stage:

The D _k value in the above-described equation, that is, the branch metric of the reception symbol is input to the first buffer 61. That is, since d _k and c _k are '0' or '1', the value obtained by multiplying the received parity bit (y _k ) by the channel reliability (L _c ), and the received channel reliability (x _k ) by the channel reliability ( L _c ) is multiplied and a value obtained by adding -z _k as described above is input in combination. Thus, possible inputs are '0' (where c _k and d _k are all '0'), '-(z _k + L _c x _k )' (c _k is '1' and d _k is '0' ), '-L _c y _k ' (where c _k is '0' and d _k is '1'), or '-(z _k + L _c x _k )-L _c y _k ' (c _k and d _k are both '0'). The branch metric of the first subframe N0 of this input is stored in the first buffer 61.

2nd stage:

The branch metric of the next subframe N1 is input to the first buffer 61, and the entire data (branch metric of N0) previously stored in the first buffer 61 is loaded into the second buffer 62 ( load).

Third stage:

The branch metric of the next subframe N2 is input to the first buffer 61, and the entire data (the branch metric of N1) previously stored in the first buffer 61 is loaded into the second buffer 62. The entire data (branch metric of N0) stored in the second buffer 62 is loaded into the third buffer 63.

The data (branch metric of N0) loaded in the third buffer 63 is input to the second ACS block 20 in the forward direction, and the data (branch metric of N1) loaded in the second buffer 62 is generated in the reverse direction. 1 is input to the ACS block 10. Accordingly, the forward state metric for the first subframe N0 is calculated by the second ACS block 20, and the backward state metric for the second subframe N1 is calculated by the first ACS block 10. do.

At this time, the same value is input to all states as the initial value of the first ACS block 10. In principle, the value of the last state of the entire frame determined by the forward state metric should be used as an initial value, but this requires a large amount of memory. Accordingly, assuming that the value of the last state of one subframe has approximately the same value, the same value is given as an initial value for all states as described above. In addition, as the initial value of the second ACS block 20, a value of '1' (zero value in the log area) is assigned to a state of '0', and '0' (Log) for a state other than '0'. Area is assigned a value of -∞). This is because when generating turbo code in the turbo encoder, the first state starts from '0', so the probability that the state is '0' is '1' and the probability of having a state other than '0' is '0'. . When the multiplexers 11 and 21 perform the first operation (i.e., add-compare-select operation) using the values input to the ACS blocks 10 and 20, the initial values are assigned to the ACS operators 13 and 23. The initial value is selected to be inputted, and when the subsequent add-compare-selection operation is performed, the selection operation is performed such that the output value of each ACS operator 13, 23 is fed back to itself.

4th stage:

The branch metric of the next subframe N3 is input to the first buffer 61, and the entire data (the branch metric of N2) previously stored in the first buffer 61 is loaded into the second buffer 62. The entire data (branch metric of N1) stored in the second buffer 62 is loaded into the third buffer 63. In addition, the entire data (branch metric of N0) previously stored in the third buffer 63 is loaded into the fourth buffer 64.

The data (branch metric of N0) loaded in the fourth buffer 64 is input to the third ACS block 30 in the reverse direction, and the data (branch metric of N1) loaded in the third buffer 63 is generated in the forward direction. 2 is input to the ACS block 20, and the data (branch metric of N2) loaded in the second buffer 62 is input to the first ACS block 10 in the reverse direction. Accordingly, the backward state metric of the first subframe N0 is calculated by the third ACS block 20, and the forward state metric of the second subframe N1 is calculated by the second ACS block 20. The reverse state metric for the third subframe N2 is calculated by the first ACS block 10.

At this time, the output of the first ACS block 10 is used as the initial value of the third ACS block 30. In addition, the initial value of the first ACS block 10 and the initial value of the second ACS block 20 are the same as described above. Each multiplexer (11, 21, 31), as in the third stage, has an initial value for the first add-compare-select operation, and the output of each ACS operator (13, 23, 33) for subsequent add-compare-select operations. This feeds back to itself and operates.

In addition, the output of the second ACS block 20 is input to the first LIFO block 50, the first LIFO block 50 is a second ACS block (Last-In, First-Out) method The output of 20) is output in reverse. The LLRE block 40 adds-compares-outputs to the output of the first LIFO block 50, the data stored in the fourth buffer 64 (the branch metric of N0) and the final output of the third ACS block 30. A selection operation is performed, whereby external information of the first subframe N0 (Extrinsic Information: corresponding to L ₁ (d _k in the above equation)) is reciprocally output from the LLRE block 40.

5th stage:

The branch metric of the next subframe N4 is input to the first buffer 61, and the entire data (branch metric of N3) previously stored in the first buffer 61 is loaded into the second buffer 62. The entire data (branch metric of N2) stored in the second buffer 62 is loaded into the third buffer 63. In addition, the entire data (branch metric of N1) previously stored in the third buffer 63 is loaded into the fourth buffer 64.

The data (branch metric of N1) loaded in the fourth buffer 64 is input to the third ACS block 30 in the reverse direction, and the data (branch metric of N2) loaded in the third buffer 63 is generated in the forward direction. 2 is input to the ACS block 20, and the data (branch metric of N3) loaded in the second buffer 62 is input to the first ACS block 10 in the reverse direction. Accordingly, the backward state metric of the second subframe N1 is calculated by the third ACS block 20, and the forward state metric of the third subframe N2 is calculated by the second ACS block 20. The reverse state metric for the fourth subframe N3 is calculated by the first ACS block 10.

In this case, as in the fourth stage, the output of the first ACS block 10 is used as the initial value of the third ACS block 30, and the initial value of the first ACS block 10 and the second ACS block ( The initial value of 20) is also the same as described above. As described above, each multiplexer 11, 21, 31 returns the initial value in the first add-compare-select operation and the output of each ACS operator 13, 23, 33 in the subsequent add-compare-select operation. To be input.

In addition, as in the fourth stage, the output of the second ACS block 20 is input to the first LIFO block 50, and the first LIFO block 50 is a last-in, first-out scheme. As a result, the output of the second ACS block 20 is reversely output. The LLRE block 40 adds, compares, and compares the output of the first LIFO block 50, the data stored in the fourth buffer 64 (the branch metric of N1) and the final output of the third ACS block 30. A selection operation is performed, whereby external information of the second subframe N1 is output inverse from the LLRE block 40.

On the other hand, the output of the fourth stage of the LLRE block 40 is input to the second LIFO block 70, the second LIFO block 70 outputs the output of the LLRE block 40 in the fifth stage according to the last-in first-out method. Reversed from Accordingly, the external information of the first subframe N0 is output by the second LIFO block 70 in the fifth stage.

Similarly, in the next stage, external information of the second subframe N1 is output through the same process as described above, and this process is repeated until all external information of the entire frame is output.

5 and 6 have been described based on a map algorithm implementing processor corresponding to the first map decoder Dec1 of the turbo decoder shown in FIG. 2, but the second map decoder of the turbo decoder shown in FIG. Dec2) is also applied to each map decoder corresponding to the multiple columns when the parity bit string L (y _k ) is composed of multiple columns. However, for example, when applied to the second map decoder Dec2 of FIG. 2, its input is L _e1 (d _k ) through the interleaver, L (x _k ) and the second parity through the interleaver as shown in FIG. 2. It will be a bit string L (y _2k ).

According to the present invention, there is provided a turbo decoder having a smaller circuit size, simpler control, and higher throughput than a conventional MAP architecture. Therefore, there is an advantage that it is suitable for decoding high speed turbo codes.

Claims (8)

A processor for implementing a MAP algorithm for a turbo decoder that receives branch metrics and calculates extrinsic information, Performing a recursive Add-Compare-Select operation to calculate a reverse state metric for a subframe in which a frame of the branch metric is divided into a plurality; 1 ACS block; A second ACS block for performing a recursive add-compare-select operation to calculate a forward state metric for the subframe; A third ACS block configured as an initial value of the output of the first ACS block and performing a recursive add-compare-selection operation to calculate a reverse state metric for the subframe; A plurality of buffers for storing the subframes sequentially input and shifting the subframes sequentially and inputting the subframes to the first to third ACS blocks; And And an LLRE block configured to perform an add-compare-selection operation on the outputs of the second and third ACS blocks and the output of the buffer for storing data input to the third ACS block. MAP algorithm implementation processor for a turbo decoder, characterized in that the. The method of claim 1, And the initial value of the first ACS block takes the same value for all states. The method of claim 1, And an initial value of the second ACS block takes 1 for a '0' state and a 0 for a state other than '0'. The method of claim 1, And a first LIFO block configured to provide a last-in first-out output of the second ACS block to the LLRE block. The method of claim 4, wherein And a second LIFO block for performing a last-in first-out output of the LLRE block. In a method of implementing a turbo decoder MAP algorithm for receiving branch metrics and calculating extrinsic information, A first step of sequentially receiving a plurality of subframes partitioning one frame of the branch metric; A second step of sequentially calculating a forward state metric for each subframe; A third step of sequentially calculating backward state metrics with respect to a next subframe of a subframe that is a calculation target in the second step while performing the second step; A fourth step of sequentially calculating backward state metrics with respect to the immediately preceding subframe of the subframe that is the calculation target in the third step using the value calculated in the third step as an initial value; And And a fifth step of sequentially calculating the external information by using the output of the second step, the output of the fourth step, and data of a subframe that is an operation target in the fourth step. Implementation method of MAP algorithm for decoder. The method of claim 6, In the second step, the MAP algorithm for turbo decoder, wherein 1 is set as '0' and '0' is set as an initial value. The method of claim 6, In the third step, the MAP algorithm for turbo decoder, characterized in that the same value is taken as an initial value for all states.