JP2001127648A - Information processor and method, and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a plurality of error correction coding algorithms and a plurality of error correction decoding algorithms with a simple and inexpensive circuit. SOLUTION: The information processor of this invention is provided with a 1st coding circuit 702 that applies error correction coding to input data, an interleaver 702 that rearranges the input data in a prescribed sequence, and a 2nd coding circuit 703 that applies error correction coding to an output of the interleaver 701 and the 1st coding circuit 702 applies parallel processing to a plurality of the error correction coding algorithms.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction coding apparatus and method, an error correction decoding apparatus and method, an information processing apparatus, and a radio communication apparatus, and more particularly to a technique for correcting an error in digital information. It is.

[0002]

2. Description of the Related Art When digital information is received on a transmission line, or when digital information is reproduced from a recording medium such as a floppy (registered trademark) disk, compact disk, or magnetic tape, an error may occur in the digital information. is there.

One technique for preventing such digital information errors is an error correction technique. The error correction technology is a technology that applies redundant coding to digital information to be transmitted or recorded, and enables correct information restoration even when an error occurs in the digital information.

[0004]

Generally, there are a plurality of types of algorithms for realizing the error correction technique. These types include digital information types and their error characteristics, transmission line types and their error characteristics, recording media types and their errors. The selection is made according to characteristics and the like. Therefore, when constructing a system that selectively uses a plurality of error correction coding algorithms, coding circuits and decoding circuits corresponding to each algorithm must be prepared individually, and as a result, the circuit scale of the entire system And the cost increases.

In a system for performing error correction coding on a plurality of types of digital information using a plurality of error correction coding algorithms, each digital information must be sequentially coded using an algorithm corresponding thereto. There is also a problem that it is difficult to increase the speed. Similarly, in the case of error correction decoding, similarly, it is necessary to sequentially decode each of the error-correction-coded digital information using an error correction decoding algorithm corresponding thereto, and it is difficult to increase the speed.

[0006] In view of the above background, it is an object of the present invention to provide an information processing apparatus and method, and a storage medium that realize a plurality of error correction coding algorithms with a simple and low-cost circuit configuration.

It is another object of the present invention to provide an information processing apparatus and method for realizing a plurality of error correction decoding algorithms with a simple and low-cost circuit configuration, and a storage medium.

[0008]

In order to achieve the above object, an information processing apparatus according to claim 1 of the present invention comprises: first encoding means for performing error correction encoding of input data; A rearranging unit that rearranges the input data in a predetermined order; and a second encoding unit that performs error correction encoding on an output of the rearranging unit. It is characterized in that processing is performed in parallel using an encoding means.

The information processing method according to a twelfth aspect of the present invention includes a first encoding step of performing error correction encoding of input data, a rearranging step of rearranging the input data in a predetermined order, A second encoding step of performing error correction encoding on the output of the rearranging step, wherein a plurality of error correction encoding processes are performed in parallel using the first encoding step. .

According to a thirteenth aspect of the present invention, in the storage medium, a first encoding procedure for performing error correction encoding of input data; a rearranging procedure for rearranging the input data in a predetermined order; A second encoding procedure for performing error correction encoding on the output of the rearranging step, and a program for processing a plurality of error correction encoding processes in parallel using the first encoding procedure is stored. It is characterized by the following.

According to a fourteenth aspect of the present invention, there is provided an information processing apparatus comprising: a first decoding means for performing error correction decoding of input data; and a first decoding means for rearranging an output of the first decoding means in a predetermined order. , A second decoding unit for performing error correction decoding on the output of the first rearranging unit, and rearranging the output of the second decoding unit in an order corresponding to the first rearranging unit. A second rearranging unit, wherein a plurality of error correction decoding processes are performed in parallel using the first decoding unit.

The information processing method according to claim 27 of the present invention provides a first decoding step of performing error correction decoding of input data and a first decoding step of rearranging an output of the first decoding step in a predetermined order. , A second decoding step of performing error correction decoding on the output of the first rearranging step, and rearranging the output of the second decoding step in an order corresponding to the first rearranging step. And a second rearranging step, wherein a plurality of error correction decoding processes are performed in parallel using the first decoding step.

A storage medium according to a twenty-eighth aspect of the present invention includes: a first decoding procedure for performing error correction decoding of input data;
A first reordering procedure for reordering the output of the first decoding procedure in a predetermined order, a second decoding procedure for error-correcting decoding of the output of the first reordering procedure, and a second reordering procedure. A second rearrangement procedure for rearranging outputs in an order corresponding to the first rearrangement procedure, and a plurality of error correction decoding processes being performed in parallel using the first decoding procedure. Is stored.

An information processing apparatus according to a twenty-ninth aspect of the present invention includes an encoding unit that shares a part of circuits and implements a plurality of error correction encoding processes, and an error correction code of the encoding unit. Control means for selecting the conversion process in accordance with the type of data transmitted wirelessly.

An information processing method according to a thirty-seventh aspect of the present invention is directed to an information processing method which shares a part of circuits and implements a plurality of error correction encoding processes; Characterization processing is selected according to the type of data transmitted wirelessly.

An information processing apparatus according to a thirty-eighth aspect of the present invention has a decoding means which shares a part of circuits and realizes a plurality of error correction decoding processes, and a decoding means for decoding wirelessly transmitted data. And control means for controlling the plurality of error correction decoding processes to operate in parallel.

[0017] In the information processing method according to claim 47 of the present invention, a decoding step which shares a part of circuits and realizes a plurality of error correction decoding processes, and a method for decoding wirelessly transmitted data. And a control step of controlling the plurality of error correction decoding processes to operate in parallel.

The information processing apparatus according to claim 48 of the present invention provides a first decoding means for performing error correction decoding of input data and a first decoding means for rearranging the output of the first decoding means in a predetermined order. , A second decoding unit for performing error correction decoding on the output of the first rearranging unit, and rearranging the output of the second decoding unit in an order corresponding to the first rearranging unit. A second sorting means, wherein the first
Is characterized in that the information representing the state metric is normalized.

Also, in the information processing method according to claim 53 of the present invention, a first encoding step of performing error correction encoding of input data; a rearranging step of rearranging the input data in a predetermined order; And a second encoding step of performing error correction encoding on an output of the rearranging step, wherein the first encoding step normalizes information representing a state metric.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a diagram showing an example of a wireless communication system of the present embodiment in which a plurality of error correction coding algorithms and a plurality of error correction decoding algorithms are selectively used.

In FIG. 1, 101 is a radio base station, 10
2 is a mobile terminal A, and 103 is a mobile terminal B.

Each of the radio base station 101, the mobile terminal A102, and the mobile terminal B103 has a common radio interface 212, and each radio interface 212 is based on a code division multiple access (CDMA) system. Wireless communication can be performed.

The CDMA system is one of the radio communication systems used in mobile communication systems. It has excellent confidentiality and interference resistance, and can realize an increase in user capacity and an improvement in speech quality as compared with the conventional system. . In the CDMA system, the transmitting side performs spread spectrum modulation on a modulated wave of the same carrier frequency using a unique spreading code assigned to each line. On the other hand, the receiving side identifies the line by synchronizing each code and realizes multiple access.

In the CDMA system, there are a plurality of types of functional channels, and the types of digital information to be transmitted and the functions of the digital information to be transmitted are different. The function channels include a user packet channel (hereinafter, UPCH), a communication channel (hereinafter, TCH), a control channel (hereinafter, CCH)
CH) and the like, which are wirelessly transmitted in a time-division manner.

The UPCH is a function channel used for transmitting control information and user information defined by a user. The TCH is a function channel used to transmit real-time user information such as audio information and image information, text information, and various types of program information. The CCH is a function channel for transmitting and receiving control information, and is a broadcast channel (hereinafter referred to as BCH).
CCH), a common control channel (hereinafter, CCCH), and an accompanying information channel (hereinafter, ACCH).

The BCCH is a downlink channel for broadcasting control information such as channel structure information and system information from the radio base station 101 to the mobile terminals A 102 and B 103. The CCCH is a channel for transmitting and receiving control information necessary for connection in a link channel establishment process between the radio base station 101 and the mobile terminal A102 (or B103).

The CCCH further includes a paging channel (hereinafter, PCH) and a dedicated cell channel (hereinafter, SCCH).
Consists of The PCH is a channel for the base station to simultaneously transfer the same information to a plurality of mobile terminals in a call area. The SCCH is a channel for transferring information necessary for call connection with a mobile terminal to be called.

The ACCH is a bidirectional channel attached to the TCH, and transmits control information required for call connection, control information required for handoff control, and user packet data. The ACCH is a low-speed associated control channel (hereinafter, SACCH) and a high-speed associated control channel (hereinafter, FA).
CCH).

The various types of digital information transmitted by the above-mentioned functional channels are encoded using a different error correction encoding algorithm for each functional channel after adding a CRC bit, and are converted into one or more radio frames. After that, it is wirelessly transmitted in a time-division manner. This coding algorithm includes a convolutional coding algorithm and a turbo coding algorithm, which will be described later. In particular, digital information transmitted by the ACCH is
The digital information transmitted by the CH is turbo coded.

Next, referring to FIG.
An example of the configuration of 103 will be described. Here, the mobile terminal A1
02 and B103 are portable information terminals such as mobile phones and mobile computers.

Reference numeral 201 denotes a microphone, which inputs an external voice and generates voice information in a predetermined format.
An imaging unit 202 generates image information in a predetermined format from an optical image of a subject. A speaker 203 decodes and outputs various types of audio information. A display unit 204 converts a data format capable of displaying and outputting text information, image information, and the like, and displays the converted data. An external interface 205 includes text information, image information,
It manages input / output of voice information, program information, etc. to the outside. 206 is an input / output terminal.

A data processing unit 207 includes a microphone 201, an imaging unit 202, and an external interface 205.
The digital information such as audio information, image information, text information, and program information supplied from the control unit 213 and various control information supplied from the control unit 213 are set in the above function channels, and a CRC bit is added to each function channel. .
The data processing unit 207 converts one or more function channels supplied from the error correction decoding circuit 209 into audio information, image information, text information, program information, and control information, and outputs the information to the speaker 203, the display unit 204, The interface 205 and the control unit 213 are selectively supplied.

An error correction coding circuit 208 executes a plurality of error correction coding algorithms including a convolutional coding algorithm and a turbo coding algorithm in parallel, and performs error correction coding on the above-mentioned functional channels. 209
Is an error correction decoding circuit, a soft output decoding algorithm,
A plurality of error correction decoding algorithms including a turbo decoding algorithm are executed in parallel to perform error correction decoding on the above-described functional channels. The detailed configurations and processing operations of the error correction encoding circuit 208 and the error correction decoding circuit 209 will be described later.

Reference numeral 210 denotes a modulator, which digitally modulates the output of the error correction coding circuit 208 using the CDMA system. Reference numeral 211 denotes a demodulation unit,
2 is demodulated using the CDMA method. A wireless interface 212 transmits and receives wireless signals to and from the wireless base station 101.

A control unit 213 including a microcomputer controls the operation of each unit constituting the mobile terminal A102 (or B103). In particular, the control unit 213 controls the error correction coding circuit 208 to implement parallel processing of a plurality of error correction coding algorithms, and controls the error correction decoding circuit 209 to perform parallel processing of the plurality of error correction decoding algorithms. To achieve. An operation unit 214 includes a numeric keypad and the like. Reference numeral 215 denotes a storage medium, and the control unit 213
Are stored.

Next, the operation of the mobile terminals A102 and B103 will be described.

First, the operation on the transmitting side will be described.

After adding a CRC bit to each function channel, the data processing unit 207 supplies each function channel to the error correction coding circuit 209. The error correction coding circuit 208 codes each functional channel by selectively using any one of a plurality of error correction coding algorithms. The error correction coding algorithm used by the error correction coding circuit 208 is selected by the control unit 213. Control unit 21
3 selects whether to activate or deactivate the selection signal supplied to the error correction coding circuit 208 according to the transmission rate of the digital information transmitted by each functional channel.

The transmission capacity per unit time is high (that is,
When coding a functional channel for transmitting digital information (at a high transmission rate), the control unit 213 activates the selection signal and selects an error correction coding algorithm that can obtain a high correction capability even in a short decoding process. Such a functional channel includes, for example, a TCH for transmitting digital information (image information, audio information, etc.) having real-time properties.
There is. One of the error correction coding algorithms selected here is a turbo coding algorithm described later, and a corresponding error correction decoding algorithm is a turbo decoding algorithm described later.

On the other hand, when encoding a functional channel for transmitting digital information having a small transmission capacity per unit time (ie, a low transmission rate), the control unit 213 deactivates the selection signal and sets a complicated decoding. Select an error correction encoding algorithm that does not require processing. Such functional channels include, for example, CCH for transmitting control information.
(In particular, ACCH). One of the error correction coding algorithms selected here is a convolution coding algorithm described later, and a corresponding error correction decoding algorithm is a soft output decoding algorithm described later.

The error correction coding circuit 208 switches the internal configuration according to the selection signal and executes a plurality of error correction coding algorithms in parallel. The error correction coded function channel is formed into one or more radio frames in the modulation unit 210 and the radio interface 212, and is then transmitted wirelessly in a time-division manner.

Next, an example of the operation on the receiving side will be described.

The demodulation section 211 checks the frame length of the radio frame forming one function channel, and notifies the control section 213 of the check result. The control unit 213 selects an error correction decoding algorithm for decoding the function channel according to the frame length, and controls the error correction decoding circuit 20
9 is selected to be active or inactive. The error correction decoding circuit 209
The internal configuration is switched according to the selection signal, a plurality of error correction decoding algorithms are executed in parallel, and a plurality of functional channels are simultaneously decoded in a time-division manner. For example, when decoding the ACCH that is one of the CCHs, the control unit 213 makes the selection signal inactive and selects the soft output decoding algorithm. When decoding the TCH, the control unit 213
Activate the selection signal and select the turbo decoding algorithm.

The data processing unit 207 checks the CRC bit of the decoding result, and the control unit 213 uses the check result to determine whether the decoding result is correct. If not, the error correction decoding circuit 209 decodes the function channel again by another error correction decoding algorithm.

By performing such control, it is possible to correctly decode a functional channel which has been encoded by any of a plurality of error correction encoding algorithms and wirelessly transmitted.

Next, another example of the operation on the receiving side will be described.

The demodulation section 211 holds a function channel composed of one or more radio frames in a buffer, and sequentially supplies each function channel to the error correction decoding circuit 209. The error correction decoding circuit 209 switches the internal configuration according to the selection signal from the control unit 213, and decodes one function channel in parallel using a plurality of error correction decoding algorithms. The result of decoding by each decoding algorithm is
7 is supplied. The data processing unit 207 calculates C
The RC bit is checked, and the control unit 213 uses the check result to determine which decoding result is correct. If it is determined that all the decoding results are incorrect, the control unit 2
13 judges that the function channel has not been correctly received, and issues a retransmission request to the base station 101.

For example, after one functional channel is decoded in parallel using both the Viterbi decoding algorithm and the turbo decoding algorithm, the data processing unit 207 checks the CRC result for the decoding result of each decoding algorithm. The decoding result by the Viterbi decoding algorithm is correct,
When it is determined that the decoding result by the turbo decoding algorithm is incorrect, the decoding result by the Viterbi decoding algorithm is selected. By performing such control, it is possible to correctly decode a wireless packet that has been encoded by any of a plurality of error correction encoding algorithms and wirelessly transmitted.

Next, the error correction encoding circuit 20 of this embodiment
8 will be described, and a plurality of error correction decoding algorithms realized by the error correction decoding circuit 209 of the present embodiment will be described.

(1) Convolutional Coding Algorithm FIGS. 3A and 3B are diagrams for explaining an example of a convolutional coding algorithm which is one of error correction coding algorithms.

The convolutional code is a coding method for outputting not only a bit string input at a certain time but also coded data affected by a bit string input before that time.

FIG. 3A is a block diagram showing an example of an error correction coding circuit necessary for realizing a non-recursive convolution coding algorithm. The circuit 300 includes delay circuits 301 and 302 for one unit time and addition circuits 303 and 304 for mod2.

The convolutional encoding circuit 300 supplies digital information input in a plurality of bits to the adders 303 and 304 as input data a. Adder circuit 303
Outputs the sum of the input data a and the output of the delay circuit 302 as encoded data b1, and the adder circuit 304 outputs the sum of the input data a and the outputs of the delay circuits 301 and 302 as encoded data b2.

FIG. 3B is a block diagram showing an example of an error correction coding circuit necessary for realizing a recursive convolution coding algorithm. The circuit 310 includes delay circuits 305 and 306 for one unit time and addition circuits 307 and 308 for mod2. This circuit 310
It is called a recursive convolutional coding circuit and is used in two coding circuits that implement a turbo coding algorithm described later.

The recursive convolutional encoding circuit 310 supplies digital information input in a plurality of bits to the addition circuit 307 as input data a. Adder circuit 307
Calculates the sum of the input data a and the output of the delay circuit 306 (that is, the feedback sum), and inputs the calculation result to the delay circuit 305 and the addition circuit 308. Addition circuit 3
08 adds the feedback sum of the addition circuit 307 and the outputs of the delay circuits 305 and 306, and outputs the result as encoded data b3.

(2) Soft Output Decoding Algorithm FIG. 4 is a block diagram showing an example of an error correction decoding circuit required to realize a soft output decoding algorithm which is one of error correction decoding algorithms. Hereinafter, the configuration and operation of the decoding circuit 400 will be described using a soft-input soft-output Viterbi decoding algorithm, which is one of the soft-output decoding algorithms, as an example.

The soft output decoding circuit 400 includes an encoding circuit 40
1. a branch metric operation circuit 402 for obtaining a branch metric which is a value indicating the strength of correlation between the code bit generated by the coding circuit 401 and the input data c;
(Add Compare Select) circuit 403, path metric memory 404 storing path metrics of all paths, A
A path memory 405 for storing path selection information indicating a surviving path selected by the CS circuit 403, and a traceback for generating the likelihood information of the maximum likelihood path by comparing the maximum likelihood path with a rival path opposing the maximum likelihood path. It comprises a circuit 406.

Next, the operation of the decoding circuit shown in FIG. 4 will be described.

The branch metric operation circuit 402 outputs the output of the encoding circuit 401 and the input data c every one unit time.
To obtain a branch metric for each branch. The ACS circuit 403 adds a branch metric of a branch from a certain past state to a certain present state to a state metric of a certain past state, and obtains a path metric of a path to the present certain state. This calculation result is stored in the path metric memory 404.

The ACS circuit 403 also compares the path metrics of a plurality of paths leading to each state, and selects a path which is estimated to have a stronger correlation with the input data c (ie, the path metric).
Survival path). The path metric of the surviving path selected at this time is stored in the path metric memory 404.
And the path selection information indicating the path is stored in the path memory 405. Here, the path metric memory 4
04 also stores the path metric of the path not selected at the same time as the surviving path. The ACS circuit 403 finally determines a path that is estimated to have the strongest correlation at a certain time (that is, the maximum likelihood path).

The traceback circuit 406 traces the maximum likelihood path using the path selection information stored in the path memory 405, and calculates the path metric of the maximum likelihood path and the path metric of the opposing path corresponding to the maximum likelihood path. Then, the likelihood of the maximum likelihood path is calculated. Here, the likelihood is calculated by, for example, a sum of 差 of the difference between the path metrics at each time point. The traceback circuit 406 outputs the product of the maximum likelihood path and the likelihood as a decoding result d.

The soft output decoding circuit 400 shown in FIG. 4 is an example, and the present invention is not limited to this. For example, the encoding circuit 401 can be realized by a table in which inputs and outputs of the encoding circuit 401 are associated.

(3) Turbo Coding Algorithm FIG. 5 is a block diagram showing an example of an error correction coding circuit necessary to realize a turbo coding algorithm which is one of the error correction coding algorithms. This circuit 50
0 is the input data x based on random or predetermined rules
, And two convolutional encoding circuits 502 and 503. Here, the convolutional encoding circuits 502 and 503 include, for example,
A recursive convolutional encoding circuit 310 shown in FIG. 3B is used.

The turbo encoding circuit 500 converts the input digital information of a plurality of bits into three output data (x, y1, y2 in FIG. 5). The three output data are
The result of outputting the input data x as it is (ie, the output data x), the result of convolutionally encoding the input data x (ie, the output data y1), and the convolutional encoding of the input data x whose bit order is rearranged by the interleaver 501 (I.e., output data y2), and an information sequence including these three output data is turbo encoded data. The turbo coding algorithm is strong in a state in which the intensity of radio waves fluctuates drastically (that is, fading), and is an optimum coding algorithm for a mobile communication system such as the wireless communication system of the present embodiment.

(4) Turbo decoding algorithm FIG. 6 is a block diagram showing an example of an error correction decoding circuit required to realize a turbo decoding algorithm which is one of the error correction decoding algorithms. This circuit 600
Soft output decoding circuits 601 and 603 for soft output decoding of input data using the above-described soft output decoding algorithm and the like, an interleaver 602 and an interleaver 602 for rearranging the outputs of the soft output decoding circuit 601 based on random or predetermined rules. The corresponding deinterleaver 604, analog /
A digital conversion circuit (A / D conversion circuit) 605 is provided.

Here, the soft output decoding circuits 601 and 603
Performs a metric operation using an analog value or a digital value quantized to three or more values as input data, and for each decoded bit, a value indicating the likelihood that the bit is “1” (or “0”) (likelihood). Degree), and outputs a decoding result including the likelihood.

In FIG. 6, turbo coded data received or read from a recording medium (ie, input series X, Y
1, Y2) are input to the turbo decoding circuit 600. Here, the input sequences X, Y1, and Y2 correspond to the output sequences x, y1, and y2 shown in FIG. 5, respectively.

The input sequences X and Y1 are supplied to the soft output decoding circuit 60.
1 and decoded. Interleaver 602 is
Interleave the decoding result of the soft output decoding circuit 601;
The result is supplied to the soft output decoding circuit 603. Soft output decoding circuit 603 performs soft output decoding using the output of interleaver 602 and input sequence Y2, deinterleaves the decoding result, and supplies the result to soft output decoding circuit 601.

After repeating the above process a predetermined number of times, the turbo decoding circuit 600 supplies the output of the deinterleaver 604 to the A / D conversion circuit 605. A / D conversion circuit 60
5 binarizes the input information and converts the result into an input sequence X, Y
1, Y2 (that is, turbo encoded data) and output as decoding results.

Next, the configuration of the error correction encoding circuit 208 of this embodiment will be described with reference to FIG.

The error correction coding circuit 208 controls the operation of the interleaver 701, the coding circuits 702 and 703, the switches 704 and 705 controlled by the selection signal, the input terminal 706 for inputting digital information, and the operation of the circuit 208. It is constituted by an input terminal 707 for inputting a selection signal.

When the selection signal is active, the switch 7
04 and 705 are turned on, the internal configuration of the coding circuit 702 is switched, and the error correction coding circuit 208 operates as an error correction coding circuit that implements the turbo coding algorithm shown in FIG. As a result, the error correction coding circuit 2
08 outputs turbo coded data including three output data x, y1, and y2. The internal configuration of the encoding circuit 702 will be described later.

Here, the output data x is the input data x, and the output data y1 is the input data x
And the output data y2 is the result of the convolutional coding of the interleaved input data x by the coding circuit 703.

When the selection signal is inactive, the switches 704 and 705 are turned off, the internal configuration of the encoding circuit 702 is switched, and the error correction encoding circuit 208 performs the non-recursive convolutional encoding shown in FIG. It operates as an error correction coding circuit that realizes a coding algorithm. Thereby, the error correction coding circuit 208 outputs only the output data y1 which is the convolutionally coded data.

FIG. 8 shows an error correction encoding circuit 2 of this embodiment.
It is a block diagram which shows another example of 08. The error correction coding circuit 208 shown in FIG. 8 can also realize both the turbo coding algorithm and the convolution coding algorithm described above. In FIG. 8, the same components as those in FIG. 7 are denoted by the same reference numerals.

The circuit 208 includes an interleaver 701,
It is composed of encoding circuits 702 and 703 and a selection circuit 801. Here, the selection circuit 801 selectively selects necessary data from the data x, the data y1 generated by the encoding circuit 702, and the data y2 generated by the encoding circuit 703 according to the selection signal. Output.

When the selection signal is active, the internal configuration of the encoding circuit 702 switches, and the error correction encoding circuit 2
08 operates as an error correction coding circuit that realizes the above-described turbo coding algorithm. Specifically, the selection circuit 8
01 selects and outputs all three data x, y1, and y2. As a result, the error correction encoding circuit 208
It outputs turbo encoded data composed of two pieces of data x, y1, and y2.

When the selection signal is inactive, the internal configuration of the coding circuit 702 switches, and the error correction coding circuit 208 operates as an error correction coding circuit for realizing the above-described convolution coding algorithm. Specifically, the selection circuit 801 selects and outputs only the data sequence y1. As a result, the error correction coding circuit 208 outputs only the data y1 which is the convolutionally coded data.

Next, an example of the internal configuration of the encoding circuit 702 will be described with reference to FIG.

The encoding circuit 702 comprises a switch 901 controlled by a selection signal, two addition circuits 902 and 905
And a first block including two delay circuits 903 and 904, an adder circuit 905, and three delay circuits 906 and 9
07, 908.

When the selection signal is active, the switch 9
01 is connected to the A side terminal, and the input sequence x is
2 is input. The input series x and the output of the delay circuit 904 are input to the addition circuit 902, and the operation result is supplied to the delay circuit 903 and the addition circuit 905. Delay circuit 9
03 supplies the input data to the delay circuit 904 and the addition circuit 905 after delaying the input data by a predetermined unit time. Similarly, the delay circuit 904 supplies the input data to the adders 902 and 905 after delaying the input data by a predetermined unit time. The adder circuit 905 includes an adder circuit 902, delay circuits 903 and 904
And outputs the addition result as output data y1.

As described above, when the selection signal is active,
The encoding circuit 702 operates as a circuit that implements a recursive convolutional encoding algorithm, as shown in FIG. At this time, the encoding circuit 702
Has the same circuit configuration as Here, the encoding circuit 702
Results in a constraint length of 3 and a coding rate of 1/1. Note that the constraint length and the coding rate are not limited to these, and the coding circuit 702 may be configured to take other values.

When the selection signal is inactive, the switch 901 is connected to the B-side terminal, and the input sequence x is input to the delay circuit 906 and the addition circuit 905. Delay circuit 9
06 supplies the input data to the delay circuit 907 and the addition circuit 905 after delaying the input data by a predetermined unit time. The delay circuit 907 delays the input data by a predetermined unit time,
The signal is supplied to the delay circuit 908. The delay circuit 908 supplies the input data to the addition circuit 905 after delaying the input data by a predetermined unit time. The addition circuit 905 adds the input sequence x and the outputs of the delay circuits 906 and 908, and outputs the addition result as output data y1.

As described above, when the selection signal is inactive, the encoding circuit 702 operates as a circuit for realizing a non-recursive convolutional encoding algorithm as shown in FIG. Here, the encoding circuit 702 determines that the constraint length is 4,
The coding rate becomes 1/2. Note that the constraint length and the coding rate are not limited to those described above, and the coding circuit 70 is set so as to take other values.
2 may be configured.

With such a configuration, the encoding circuit 70
2 implements a plurality of types of error correction coding algorithms having different correction capabilities according to the state of the selection signal.

Next, the processing operation of the error correction coding circuit 208 will be described with reference to FIG.

FIG. 10A is a diagram showing an operation state of the coding circuit 702 when the selection signal is active, and FIG. 10B is a diagram showing the interleaver 701 and the coding circuit 7.
It is a figure which shows the operation state of 03. FIG. 10C shows the encoding circuit 702 when the selection signal is inactive.
FIG. 6 is a diagram showing an operation state of FIG.

When the selection signal is active, the switch 901 inside the encoding circuit 702 is connected to the A-side terminal, and the encoding circuit 702 encodes the input data x according to a recursive convolutional encoding algorithm (first Error correction coding processing (1001 in FIG. 10). At this time, the interleaver 701 rearranges the input data x according to a predetermined rule,
The result is supplied to the encoding circuit 703. The encoding circuit 703 encodes the output of the interleaver 701 according to a recursive convolutional encoding algorithm (second error correction encoding processing; 1002 and 1003 in FIG. 10).

After the first error correction encoding process is completed,
The selection signal switches to inactive, and the encoding circuit 70
2 switch 901 is connected to the B-side terminal, and the internal configuration of the encoding circuit 702 changes. And the encoding circuit 7
02 encodes the input data x according to the non-recursive convolutional encoding algorithm during the period when the encoding circuit 703 performs the second error correction encoding process (third error correction encoding process).
Error correction coding processing. 1004 in FIG. 10).

After the third error correction encoding process is completed,
The selection signal switches to active, the switch 901 is connected to the A-side terminal, and the encoding circuit 702 executes the first error correction encoding process again.

According to the above procedure, the error correction coding circuit 208 of this embodiment operates as an error correction coding circuit for realizing the above turbo coding algorithm when the selection signal is active, and when the selection signal is inactive, Operate as an error correction coding circuit for realizing a non-recursive convolutional coding algorithm and have two different error correction capabilities.
One encoding algorithm can be processed in parallel (in other words, time division simultaneously), and various functional channels can be efficiently and quickly error-correction-encoded.

Next, the configuration of the error correction decoding circuit 209 of this embodiment will be described with reference to FIG.

This circuit 209 comprises decoding circuits 1101, 11
03, the decoding circuit 11 based on a random or predetermined rule
01, and a deinterleaver 110 corresponding to the interleaver 1102
4. Analog / digital (A / D) conversion circuit 110
5. Switches 1107 and 1108 which are turned on when the selection signal is active under the control of the selection signal, and connected to the B side when the selection signal becomes active under the control of the selection signal and when it becomes inactive Is a switch 1107 connected to the A side, an input terminal 1109 for inputting a selection signal for controlling the operation of the circuit 209, an input terminal 1110 for inputting data X, an input terminal 1111 for inputting data Y1, and inputting data Y2. Input terminal 1112
It consists of.

Here, the decoding circuits 1101 and 1103 are
Similarly to the above-described soft output decoding circuits 601 and 603, a metric operation is performed on input information, and for each bit, a value indicating the likelihood that the bit is “1” (or “0”) (likelihood) And outputs the likelihood together with the decoding result.

When the selection signal is active, the decoding circuit 1
The internal configuration of the error correction decoding circuit 20 is switched.
9 operates as an error correction decoding circuit for realizing the turbo decoding algorithm shown in FIG. In this case, the error correction decoding circuit 209 decodes the turbo coded data generated by the error correction coding circuit 208.

When the selection signal is inactive, the internal configuration of the decoding circuit 1101 is switched, and the error correction decoding circuit 209 operates as an error correction encoding circuit for realizing the soft output decoding algorithm shown in FIG. In this case, the error correction decoding circuit 209 decodes the convolutionally encoded data generated by the error correction encoding circuit 208.

Next, an example of the internal configuration of the decoding circuit 1101 will be described with reference to FIG.

The decoding circuit 1101 is
1, 1202; a branch metric operation circuit 1203 for obtaining a branch metric which is a value indicating the strength of correlation between the code bits generated by the encoding circuits 1201 and 1202 and the input data; an ACS (Add Compare Select) circuit 1
204, path metric memories 1205 and 1206 for storing path metrics of all paths, ACS circuit 120
Path memories 1207 and 1208 for storing path selection information indicating the surviving path selected by step 4, traceback for generating the likelihood information of the maximum likelihood path by comparing the maximum likelihood path with the opposing path opposing the maximum likelihood path It comprises a circuit 1209.

When the selection signal is active, the decoding circuit 1
101 is an encoding circuit 1201, path metric memory 1
205, decodes the input data using the path memory 1207, and operates as one of the soft output decoding circuits constituting the turbo decoding circuit. At this time, the decoding circuit 1101 has the same circuit configuration as the decoding circuit 1103. When the selection signal is inactive, the decoding circuit 1101
2. Path metric memory 1206, path memory 120
For example, the input data is subjected to Viterbi decoding, for example. Here, each of the branch metric calculation circuit 1203, the ACS circuit 1204, and the traceback circuit 1209 is shared by a plurality of error correction decoding algorithms.

With such a configuration, the decoding circuit 110
1 implements a plurality of types of error correction decoding algorithms having different correction capabilities according to the state of the selection signal.

Next, the error correction decoding circuit 2 will be described with reference to FIG.
The processing operation of 09 will be described.

FIG. 13A is a diagram showing the operation state of the decoding circuit 1101 and the operation state of the interleaver 1102 when the selection signal is active, and FIG. 13B is a diagram showing the operation state of the decoding circuit 1103 and the deinterleaver. 1104
FIG. 5 is a diagram showing an operation state of FIG. FIG. 13C is a diagram showing an operation state of the decoding circuit 1101 when the selection signal is inactive.

When the selection signal is active, the error correction decoding circuit 209 outputs the turbo coded data (ie, input data X, Y) received or read from the recording medium.
1, Y2). Here, the input data X, Y1,
Y2 is the output data x, y shown in FIG.
1, y2.

The input data X and Y1 are supplied to the decoding circuit 1101
And is decoded (first error correction decoding process; 1301 in FIG. 13). Interleaver 1102 interleaves the decoding result of decoding circuit 1101 and the likelihood for each bit, and supplies the result to decoding circuit 1103 (FIG. 1).
3 1302). The decoding circuit 1103 performs soft output decoding using the output of the interleaver 1102 and the input data Y2 (second error correction decoding processing; 130 in FIG. 13).
3). The decoding result and the likelihood are calculated by the deinterleaver 11
04 and deinterleaved (13 in FIG. 13).
04). The output of the deinterleaver 1104 is supplied to the decoding circuit 1101 via the switch 1108.

After repeating the above process a predetermined number of times,
The D conversion circuit 1105 binarizes the output of the deinterleaver 1104 and converts the result into input data X, Y1, Y2
(Ie, turbo encoded data) as a decoding result.

When the selection signal is inactive, the error correction decoding circuit 209, for example, outputs the soft output decoding circuit 4 shown in FIG.
The same processing as 00 is performed.

In this case, the switch 1106 is turned off, and only the input data Y1 is input to the error correction decoding circuit 209. The decoding circuit 1101 includes the interleaver 11
02, while the decoding circuit 1103 and the deinterleaver 1104 operate, the input data Y1 is soft-output decoded and the decoding result is supplied to the switch 1107 (third error correction decoding processing; 1305 to 130 in FIG. 13).
7). Here, the switch 1107 is connected to the A side, and the output of the decoding circuit 1101 is connected to the A / D conversion circuit 1105.
Supplied to The A / D conversion circuit 1105 includes the decoding circuit 1
The output of 101 is binarized, and the result is output as a decoding result of the input data Y1.

According to the above procedure, the error correction decoding circuit 209 of this embodiment operates as an error correction encoding circuit for realizing the above turbo decoding algorithm when the selection signal is active, and when the selection signal is inactive, , Operates as an error correction decoding circuit that realizes a soft output decoding algorithm, and can process two decoding algorithms having different error correction capabilities in parallel (in other words, at the same time in a time-division manner). Good and high-speed error correction decoding can be performed.

(Second Embodiment) In the first embodiment, a part of the error correction coding circuit 208 is shared and the information sequence y1 is used.
An example has been described in which the convolutional encoding algorithm that outputs only the information and the turbo encoding algorithm that outputs the information sequences x, y1, and y2 are processed in parallel. However, the error correction encoding circuit 208 efficiently processes in parallel. The encoding algorithm is not limited to this combination.

For example, by turning on the switch 704 of the error correction coding circuit 208 at all times, when the selection signal is active, the same turbo coding algorithm as in the first embodiment is realized, and the selection signal is In the case of inactivity, a coding circuit for realizing a second convolutional coding algorithm that outputs information sequences x and y1 (having a different correction capability from the convolutional coding algorithm of the first embodiment) is configured. You can also. At this time, the turbo encoding algorithm is processed at the timings shown in FIGS. 10A and 10B, and the second convolutional encoding algorithm is as shown in FIG.
The processing is performed at the timing shown in FIG.

As a result, the error correction coding circuit 208
Can achieve a convolutional coding algorithm with a longer code length but improved correction capability, and can execute the coding algorithm in parallel with the turbo coding algorithm (in other words, the two coding algorithms). Can be processed simultaneously in a time-division manner), and various functional channels can be efficiently and quickly error-correction-coded.

Further, in the first embodiment, a soft output decoding algorithm for decoding only the information sequence Y1 and a turbo decoding algorithm for decoding the information sequences X, Y1, Y2 by sharing a part of the error correction decoding circuit 209. Has been described in parallel, but the decoding algorithm that the error correction decoding circuit 209 processes in parallel is not limited to this combination.

For example, by turning on the switch 1106 of the error correction decoding circuit 209 at all times, when the selection signal is active, a turbo decoding algorithm similar to that of the first embodiment is realized, and the selection signal becomes inactive. In the case of (1), a decoding circuit for realizing a second soft-output decoding algorithm for decoding the information sequences X and Y1 (having a different correction capability from the soft-output decoding algorithm of the first embodiment) can be configured. At this time, the turbo decoding algorithm is shown in FIG.
13 (a) and (b), and the second soft output decoding algorithm is processed at the timing shown in FIG. 13 (c).

Thus, the error correction decoding circuit 209
A soft-output decoding algorithm for decoding the information sequences X and Y1 can be realized, and the decoding algorithm can be implemented in parallel with the turbo decoding algorithm (in other words, those 2
One decoding algorithm can be simultaneously processed in a time-division manner, and various functional channels can be efficiently and quickly error-corrected decoded.

(Third Embodiment) In a third embodiment, another example of the decoding circuit 1101 described in the above embodiment will be described.

FIG. 14 shows the error correction decoding circuit 2 of this embodiment.
FIG. 10 is a block diagram showing another example of the decoding circuit 1101 included in 09.

In FIG. 14, reference numerals 1401 and 1402 denote encoding circuits. Reference numeral 1402 denotes a branch metric calculation circuit which obtains a branch metric which is a value indicating the strength of correlation between the code bits generated by the coding circuits 1401 and 1402 and input data. 1404 is ACS (Add
Compare Select) circuit. Reference numerals 1405 and 1406 denote path metric memories, which store path metrics of all paths. Reference numerals 1407 and 1408 denote path memories, which store path selection information indicating the surviving path selected by the ACS circuit 1404. A 1409 traceback circuit compares the maximum likelihood path with an opposing path that opposes the maximum likelihood path, and generates likelihood information of the maximum likelihood path. here,
The encoding circuits 1401 and 1402 can also be realized by a table in which inputs and outputs are associated.

In FIG. 14, reference numeral 1410 denotes a normalization circuit that normalizes the state metrics of each state selected by the ACS circuit 1404 so as not to overflow. Reference numeral 1411 denotes a delay circuit that delays a part of the state metric of each state. 141
Reference numeral 2 denotes a state metric memory, which stores normalized state metrics.

When the selection signal is active, the decoding circuit 1
101 is an encoding circuit 1401, path metric memory 1
405, decodes the input data using the path memory 1407, and operates as one of the soft output decoding circuits constituting the turbo decoding circuit. At this time, the decoding circuit 1101 has the same circuit configuration as the decoding circuit 1103. When the selection signal is inactive, the decoding circuit 1101
2. Path metric memory 1406, path memory 140
For example, the input data is subjected to Viterbi decoding, for example. Here, the branch metric operation circuit 1403, the ACS circuit 1404, the traceback circuit 1409, the normalization circuit 1
Each of 410, delay circuit 1411, and state metric memory 1412 is shared by a plurality of error correction decoding algorithms.

With such a configuration, the decoding circuit 110
1 implements a plurality of types of error correction decoding algorithms having different correction capabilities according to the state of the selection signal.

Next, the operation of the decoding circuit 1101 will be described with reference to FIG.

The branch metric calculation circuit 1402 is
For each unit time, the output of the encoding circuit 1401 (or the encoding circuit 1402) is compared with the input data, and a branch metric for each branch is obtained. ACS circuit 1
Reference numeral 404 denotes a state metric of a certain past state read from the state metric memory 1412, a branch metric of a branch from a certain past state to a certain present state is added to the state metric, and a path of a certain state to the present state is added. Find the metric.

Next, the ACS circuit 1404 compares the path metrics of a plurality of paths leading to the same state, and selects a path estimated to have a stronger correlation with the input data (that is, a surviving path). . This surviving path becomes the new state metric of the current state, and the path metric of the next state is calculated using this state metric. The path metric of the surviving path selected at this time is stored in the path metric memory 1405 (or path metric memory 1406), and the path selection information indicating the path is stored in the path memory 1407 (or
Path memory 1408). Here, the path metric memory 1405 (or the path metric memory 1)
406) also stores the path metric of the path not selected at the same time as the surviving path.

The upper m bits of the state metric of each state are supplied to a normalization circuit 1410, and the lower n bits of the state metric are supplied to a delay circuit 1411. For example, the information amount of the state metric is 16 bits (m + n = 16), the number of bits supplied to the normalization circuit 1410 is 2 bits (m = 2), and the number of bits supplied to the delay circuit 1411 is 14 bits (n = 14) will be described.

The normalization circuit 1410 obtains the minimum value from the upper two bits of the state metric of each state, subtracts the minimum value from all input values, and normalizes them. The normalized upper 2 bits are combined with the lower 14 bits delayed by the delay circuit 1411 and stored in the state metric memory 1412.

As described above, by normalizing the state metric of each state, the storage capacity of the state metric memory 1412 and the number of wires required for the calculation of the state metric can be significantly reduced, and the power consumption can be suppressed. . Further, the state metric and the path metric can be accurately evaluated without increasing the information amount of the state metric.

The number m of bits supplied to the normalization circuit 1410 is not limited to 2 bits (m = 2). m
Is larger than 2, the amount of state metric information can be made smaller, and at the same time, the probability of failure in normalization processing (that is, normalization but overflow) can be made extremely small.
Also, the value of m can be selected so as to be optimal according to the coding rate of the error correction coding algorithm that has coded the input data. For example, the value of the branch metric per unit time increases as the coding rate decreases. Therefore, the lower the coding rate of the input data, the more m
By increasing the value of, it is possible to prevent an increase in the amount of information of the state metric, and at the same time, to extremely reduce the probability of failure in the normalization processing.

By repeating the above procedure, A
The CS circuit 1404 obtains a state metric of each state at each time point, and finally determines a path estimated to have the strongest correlation at a certain time point (that is, a maximum likelihood path).

The trace-back circuit 1409 traces the maximum likelihood path using the path selection information stored in the path memory 1407 (or the path memory 1408), and corresponds to the path metric of the maximum likelihood path and the maximum likelihood path. The path metric of the opposing path is compared, and the likelihood of the maximum likelihood path is calculated. Here, the likelihood is calculated by, for example, a sum of 差 of the difference between the path metrics at each time point. The traceback circuit 1409 outputs the product of the maximum likelihood path and the likelihood as a decoding result.

Next, the internal structure of the normalizing circuit 1410 of this embodiment will be described with reference to FIG. In this embodiment, a case will be described in which the decoding circuit 1101 operates as a circuit that decodes 4-state encoded data. The number of states differs depending on the encoding algorithm of the encoded data to be decoded.

In FIG. 15, 1501, 1503, 1
Reference numeral 505 denotes a comparison circuit.
6 is a selector circuit. 1507 to 1511 are subtraction circuits. Each of Inputs 0 to 3 is the upper 2 bits of the state metric of each state at a certain point in time.
Outputs 0 to 3 are results obtained by normalizing the upper 2 bits of the state metric of each state, and these values are combined with the lower 14 bits of the state metric of each state output from the delay circuit 1411 to form a state metric. It is stored in the memory 1412.

Top 2 state metrics for the first state
The bit (Input 0) and the upper two bits (Input 1) of the state metric of the second state are compared with the comparison circuit 1
501 and a selector circuit 1502. The selector circuit 1502 selects the smaller value according to the output of the comparison circuit 1501, and compares the selected result with the comparison circuit 1505,
This is supplied to the selector circuit 1506.

On the other hand, the upper two bits (Input 2) of the state metric in the third state and the upper two bits (Input 3) of the state metric in the fourth state are supplied to the comparison circuit 1503 and the selector circuit 1504. The selector circuit 1504 selects the smaller value according to the output of the comparison circuit 1503, and compares the result of the selection with the comparison circuit 1503.
05, and supply it to the selector circuit 1506.

The selector circuit 1506 includes the comparison circuit 150
5, the smaller value of the output of the selector circuit 1502 and the output of the selector circuit 1504 is selected. As a result, the selector circuit 1506 outputs Inpu
The smallest value among t0 to t3 is output.

The output of the selector circuit 1506 is supplied to each of the subtraction circuits 1507 to 1501. Each subtraction circuit 1
507 to 1501 subtract the output of selector circuit 1506 (ie, the minimum input value) from Inputs 0 to 3,
The result is output as Output 0-3.

With this configuration, the normalization circuit 1410 of this embodiment can not only significantly reduce the number of wires required for calculating the state metric, but also reduce power consumption.

Although the present embodiment has been described with respect to an example in which each of Inputs 0 to 3 is input in parallel, they may be input in series.

(Other Embodiments) The above-described embodiments can be realized as follows.

For example, software programmed to implement the first and second embodiments is recorded on a recording medium 215, and supplied to a control unit 213 provided in the mobile terminals A102 and B103. Then, the control unit 213 reads out the program stored in the storage medium 215 and controls the operations of the mobile terminals A102 and B103 to realize the above-described embodiment.

In this case, a part of a plurality of program modules necessary for realizing the above-described plurality of error correction coding algorithms is shared, and the coding processing by the plurality of error correction coding algorithms is performed in parallel. It can be carried out. Further, a part of a plurality of program modules necessary for realizing the above-described plurality of error correction decoding algorithms can be shared, and decoding processing by the plurality of error correction decoding algorithms can be performed in parallel. As a result, it is possible to reduce the program amount of the entire program and shorten the development process, and it is also possible to efficiently and quickly realize a plurality of error correction encoding algorithms and a plurality of error correction decoding algorithms.

As the storage medium 215 for supplying software, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-RO
M, CD-R, magnetic tape, nonvolatile memory card,
A ROM or the like can be used.

The software described above is stored in the storage medium 21.
5 or may be recorded on the storage medium 215 after being supplied from the outside.

It should be noted that the present invention can be implemented in various forms without departing from the spirit or main features thereof.

In the above embodiment, the error correction coding circuit 2
08 and the error correction decoding circuit 209 are connected to the mobile terminal A102,
Although the example applied to B103 has been described, it may be applied to wireless communication terminals such as base stations and fixed stations.

In the above-described embodiment, an example has been described in which a part of the error correction coding circuit 208 is shared and two error correction coding algorithms having different correction capabilities are performed in parallel. It is also possible to configure so that two or more different error correction coding algorithms are performed in parallel. For example, a plurality of convolutional coding algorithms having different correction capabilities and a plurality of turbo coding algorithms having different correction capabilities can be configured to be performed in parallel.

In the above-described embodiment, an example has been described in which a part of the error correction decoding circuit 209 is shared and two error correction decoding algorithms having different correction capabilities are performed in parallel. It is also possible to configure so that one or more error correction decoding algorithms are performed in parallel. For example, a plurality of soft-output decoding algorithms having different correction capabilities and a plurality of turbo decoding algorithms having different correction capabilities may be configured to be performed in parallel.
The MAP decoding (ma
It is also possible to configure to perform a maximum likelihood decoding algorithm such as an ximum a posteriori probability decoding algorithm.

[0148]

As described above, according to the present invention, a plurality of error correction coding algorithms can be realized by a simple and low-cost circuit configuration.

According to the present invention, a plurality of error correction coding algorithms including a convolutional coding algorithm and a turbo coding algorithm are processed in parallel, so that a plurality of error correction coding algorithms are processed efficiently and at high speed. be able to.

According to the present invention, a plurality of decoding algorithms can be realized by a simple and low-cost circuit configuration.

According to the present invention, a plurality of error correction decoding algorithms including a soft output decoding algorithm and a turbo decoding algorithm are processed in parallel, so that a plurality of error correction decoding algorithms can be processed efficiently and at high speed. .

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a wireless communication system according to an embodiment;

FIG. 2 is a block diagram illustrating an example of a configuration of a mobile terminal according to the embodiment.

FIG. 3 is a block diagram illustrating an example of a circuit that implements a convolutional coding algorithm.

FIG. 4 is a block diagram showing an example of a circuit for realizing a soft output decoding algorithm.

FIG. 5 is a block diagram illustrating an example of a circuit that implements a turbo encoding algorithm.

FIG. 6 is a block diagram illustrating an example of a circuit that implements a turbo decoding algorithm.

FIG. 7 is a block diagram showing an example of an error correction encoding circuit according to the embodiment.

FIG. 8 is a block diagram showing another example of the error correction encoding circuit according to the embodiment.

FIG. 9 is a block diagram illustrating an example of an encoding circuit included in the error correction encoding circuit according to the embodiment.

FIG. 10 is a view for explaining the processing operation of the error correction encoding circuit of the embodiment.

FIG. 11 is a block diagram showing an example of an error correction decoding circuit according to the embodiment.

FIG. 12 is a block diagram illustrating an example of a decoding circuit included in the error correction decoding circuit according to the present embodiment.

FIG. 13 is a view for explaining the processing operation of the error correction decoding circuit of the embodiment.

FIG. 14 is a block diagram showing another example of the decoding circuit provided in the error correction decoding circuit according to the embodiment.

FIG. 15 is a block diagram illustrating an example of a normalization circuit.

Claims (54)

[Claims] A first encoding unit that performs error correction encoding of input data; a rearranging unit that rearranges the input data in a predetermined order; and a second encoding unit that performs error correction encoding on an output of the rearranging unit. An information processing apparatus, comprising: a plurality of error correction encoding processes, wherein a plurality of error correction encoding processes are performed in parallel using the first encoding device. 2. The plurality of error correction encoding processes include: a first error correction encoding process for generating encoded data using at least the first encoding unit; The information processing apparatus according to claim 1, further comprising a second error correction encoding process that generates encoded data using the rearrangement unit and the second encoding unit. 3. The information processing apparatus according to claim 2, wherein the first error correction coding processing is an error correction coding processing for realizing convolutional coding. 4. The information processing apparatus according to claim 2, wherein the second error correction coding processing is an error correction coding processing for implementing turbo coding. 5. When the first error correction encoding process is performed, the first encoding unit non-recursively performs convolutional encoding on the input data, and executes the second error correction encoding. The information processing apparatus according to any one of claims 2 to 4, wherein when processing is performed, the input data is recursively convolutionally coded. 6. The apparatus according to claim 1, wherein said first encoding means performs the same encoding processing as said second encoding means when implementing said second error correction encoding processing. The information processing apparatus according to any one of claims 2 to 5. 7. The information processing apparatus according to claim 1, wherein the first encoding unit changes a constraint length in each error correction encoding process. 8. The apparatus according to claim 1, wherein said first encoding means makes a constraint length in said first error correction encoding process longer than a constraint length in said second error correction encoding process. Item 8. The information processing device according to item 7. 9. The information processing apparatus according to claim 8, wherein the first encoding unit changes the constraint length of each error correction encoding process by controlling the number of delay circuits. 10. The information processing apparatus according to claim 1, wherein the information processing apparatus selects the error correction encoding processing according to a type of the input data. 11. The information processing device according to claim 1, wherein the information processing device is a wireless communication device. 12. A first method for performing error correction coding on input data.
Encoding step; a rearranging step of rearranging the input data in a predetermined order; and a second step of performing error correction encoding on an output of the rearranging step.
An information processing method comprising: performing a plurality of error correction encoding processes in parallel using the first encoding step. 13. A first method for performing error correction coding on input data.
An encoding procedure; a rearranging procedure for rearranging the input data in a predetermined order; and a second procedure for error correction encoding the output of the rearranging step.
And a program for processing a plurality of error correction coding processes in parallel using the first coding procedure. 14. A first decoding unit for performing error correction decoding of input data, a first rearranging unit for rearranging an output of the first decoding unit in a predetermined order, and a first rearranging unit. 2nd error correction decoding of output
And a second rearranging unit for rearranging the output of the second decoding unit in an order corresponding to the first rearranging unit. An information processing apparatus for performing parallel processing using a decoding unit. 15. The multiple error correction decoding process according to claim 1, wherein the first decoding unit decodes the input data using the first decoding unit.
Error correction decoding processing, the first decoding means and the second
The information processing apparatus according to claim 14, further comprising a second error correction decoding process of decoding the input data using both of the decoding means. 16. The error correction decoding device, when realizing the first error correction decoding process, realizes the second error correction decoding process by using an output of the first decoding means as a decoding result. 16. The information processing apparatus according to claim 15, wherein when performing the processing, the output of the second rearranging unit is used as a decoding result. 17. The information processing apparatus according to claim 15, wherein the first error correction decoding process is an error correction decoding process that implements maximum likelihood decoding. 18. The information processing apparatus according to claim 15, wherein said second error correction decoding process is an error correction decoding process for realizing turbo decoding. 19. The apparatus according to claim 15, wherein said first decoding means performs the same decoding processing as said second decoding means when realizing said second error correction decoding processing.
19. The information processing device according to any one of 18. 20. The method according to claim 15, wherein the first error correction decoding processing and the second error correction decoding processing can decode error correction codes having different constraint lengths.
An information processing device according to any one of the above. 21. The information processing apparatus according to claim 20, wherein the first error correction decoding process decodes an error correction code having a longer constraint length than the second error correction decoding process. 22. The information processing apparatus according to claim 14, wherein the information processing apparatus decodes the input data using each of the plurality of error correction decoding processes. 23. The information processing apparatus according to claim 14, wherein the information processing apparatus selects an error correction decoding process for decoding the input data according to a data length of the input data.
2. The information processing device according to claim 1. 24. The information processing apparatus according to claim 14, wherein said first decoding means normalizes information representing a state metric. 25. The information processing apparatus according to claim 24, wherein the first decoding unit normalizes a plurality of upper bits of information representing a state metric. 26. The information processing device according to claim 14, wherein the information processing device is a wireless communication device. 27. A first decoding step for performing error correction decoding of input data, a first rearranging step for rearranging an output of the first decoding step in a predetermined order, and a first rearranging step. A second decoding step of performing error correction decoding of the output; and a second rearranging step of rearranging the output of the second decoding step into an order corresponding to the first rearranging step. An information processing method, wherein a correction decoding process is performed in parallel using the first decoding step. 28. A first decoding procedure for error-correcting decoding of input data, a first rearranging procedure for rearranging the output of the first decoding procedure in a predetermined order, and an output of the first rearranging procedure. Error correction decoding
And a second permutation procedure for rearranging the output of the second decoding procedure into an order corresponding to the first permutation procedure. A storage medium storing a program for performing parallel processing using a decoding procedure. 29. An encoding unit that shares a part of circuits and implements a plurality of error correction encoding processes, and performs an error correction encoding process of the encoding unit in accordance with a type of data wirelessly transmitted. An information processing apparatus comprising: a control unit for selecting. 30. The information processing apparatus according to claim 29, wherein the plurality of error correction coding processes include error correction coding processes having different error correction capabilities. 31. The information processing apparatus according to claim 30, wherein the plurality of error correction coding processes include an error correction coding process for implementing turbo coding. 32. The information processing apparatus according to claim 30, wherein the plurality of error correction coding processes include an error correction coding process for implementing convolutional coding. 33. The encoding device according to claim 29, wherein the encoding unit performs the plurality of error correction encoding processes in parallel.
33. The information processing apparatus according to any one of claims to 32. 34. The encoding apparatus according to claim 29, wherein said encoding means has a plurality of encoding circuits, and one of said plurality of encoding circuits is shared by said plurality of error correction encoding processes.
An information processing apparatus according to any one of claims 33. 35. The information according to claim 34, wherein the control unit selects the error correction encoding process of the encoding unit according to a transmission rate of wirelessly transmitted data. Processing equipment. 36. The information processing apparatus according to claim 29, wherein the information processing apparatus has a wireless communication function conforming to a CDMA system. 37. An encoding step that shares a part of circuits and implements a plurality of error correction encoding processes, and the error correction encoding process of the encoding step is performed according to the type of wirelessly transmitted data. An information processing method characterized by selecting. 38. A decoding means which shares a part of circuits and realizes a plurality of error correction decoding processes, and operates the plurality of error correction decoding processes in parallel in order to decode wirelessly transmitted data. An information processing apparatus, comprising: a control unit for controlling the information processing. 39. The information processing apparatus according to claim 38, wherein said plurality of error correction decoding processes include a process of decoding error correction encoded data having different error correction capabilities. 40. The information processing apparatus according to claim 39, wherein the plurality of error correction decoding processes include an error correction decoding process for implementing turbo decoding. 41. The information processing apparatus according to claim 39, wherein said plurality of error correction decoding processes include an error correction decoding process for realizing maximum likelihood decoding. 42. The information processing apparatus according to claim 38, wherein said decoding means decodes said wirelessly transmitted data by using each of said plurality of error correction decoding processes. . 43. The apparatus according to claim 38, wherein said decoding means has a plurality of decoding circuits, and one of said plurality of decoding circuits is shared by said plurality of error correction coding processes. An information processing device according to any one of the above. 44. The information processing apparatus according to claim 42, wherein said decoding means includes said plurality of decoding circuits and two interleavers. 45. An apparatus according to claim 38, wherein said control means selects an error correction decoding process for decoding said wirelessly transmitted data according to a data length of said data.
5. The information processing device according to any one of 4. 46. The information processing apparatus according to claim 38, wherein the information processing apparatus has a wireless communication function conforming to a CDMA system. 47. A decoding step of sharing a part of circuits and implementing a plurality of error correction decoding processes, and operating the plurality of error correction decoding processes in parallel to decode wirelessly transmitted data. And a control step of controlling the information processing. 48. A first decoding unit for performing error correction decoding of input data, a first rearranging unit for rearranging an output of the first decoding unit in a predetermined order, and a first rearranging unit. 2nd error correction decoding of output
And a second rearranging unit for rearranging the output of the second decoding unit in an order corresponding to the first rearranging unit. An information processing apparatus for normalizing information to be represented. 49. The information processing apparatus according to claim 48, wherein said first decoding means normalizes a part of information indicating said state metric. 50. The information processing apparatus according to claim 49, wherein said first decoding means normalizes upper bits of information representing said state metric. 51. The first decoding means according to an error correction encoding algorithm which encodes the input data,
The information processing apparatus according to any one of claims 48 to 50, wherein a normalization process for information representing the state metric is changed. 52. The method according to claim 48, wherein the first decoding unit normalizes information representing another state metric using a minimum value of the information representing the state metric. An information processing apparatus according to claim 1. 53. The information processing device according to claim 48, wherein the information processing device is a wireless communication device. 54. A first method for performing error correction coding on input data.
Encoding step; a rearranging step of rearranging the input data in a predetermined order; and a second step of performing error correction encoding on an output of the rearranging step.
An information processing method, wherein the first encoding step normalizes information representing a state metric.