JP2001028409A - Method of dimpling semiconductor package and semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable press molding at a low cost and a mass production reliability by forming press-engraved marks on a dimpled peripheral edge. SOLUTION: A semiconductor package 1 is composed of one or more metal foil layers laminated on the surface 2 or backside 3 of a metal base and a dimpled part 4 having rectangular corners 4a, 4b formed by the dimpling method using a press die. To keep a flatness accuracy of the surface 2 at the front side of the dimpled part 4 to be a mounting surface for semiconductor devices, specified regions are burnished to form press-engraved marks or worked by the press die to form press-squeezed parts, i.e., a plurality of press-squeezed steps 7 are formed on the front side of the semiconductor package 1. On the surface 2 or backside 3 of the dimpled peripheral part D1, press-squeezed parts 5, 6 are formed by pressing in the dimpling process using the press die or thereafter, or on a bottom portion D2 of the dimpled part 4, a plurality of press- squeezed parts 8 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package dimple processing method and a semiconductor package obtained by the processing method.

[0002]

2. Description of the Related Art A semiconductor package is used not only to take out an electric terminal as a container of a semiconductor device but also to shut out outside air from a semiconductor chip to prevent a failure or deterioration. That is, the semiconductor package is made of a metal plate mainly composed of stainless steel (SUS), copper or aluminum, and has a metal base substrate having a predetermined circuit pattern shape and at least one or both surfaces of the metal base substrate. An insulator made of an organic insulator formed on the insulator, a thin-film wiring pattern made of a metal foil having a predetermined circuit pattern shape formed on the insulator, and further, a film is formed on the wiring pattern. And a cover insulator made of an organic insulator formed. In a part of the semiconductor package, a cavity (recess) exposing the metal base substrate at a predetermined position for mounting a semiconductor chip by removing the insulator, the wiring pattern, and the cover insulator described above. The dimple (working) portion is formed by drawing using a press die arranged in a press machine.
When the above-mentioned wiring pattern is formed to extend to the bottom of the dimple portion, the metal base substrate,
The insulator, the wiring pattern and the like are simultaneously drawn by a press die to form a dimple portion.

For example, as shown in FIG. 9 of the accompanying drawings, this type of semiconductor package 1 is formed by pressing a metal plate 30 having an electrically insulating layer 35 formed on its front surface 2 and back surface 3 by using a press die. To form a housing concave portion (a dimple-processed portion) 4 for mounting the semiconductor device, a mounting surface 31 for mounting an external connection terminal, and a step surface 33. On the surface 2 side of the mounting surface of the metal base material (metal plate), a resin layer such as a sealing resin stop frame 34, an inner lead 32, a connection pad 36, a metal plating resist layer 37, and a metal foil layer And the like are stacked one or more times (for example, see Japanese Patent Application Laid-Open No. H10-321761).
Reference). Therefore, extremely high flatness accuracy is required for the dimple processing portion on which the semiconductor device is mounted and the mounting surface.

[0004]

However, when a metal plate formed by laminating one or more resin layers and metal foil layers on such a metal substrate is subjected to dimple processing to form a semiconductor package, In many cases, the flatness of the mounting surface of the semiconductor package does not satisfy a predetermined requirement due to distortion or the like of the material.

That is, copper or a copper alloy having a thickness of about 0.1 to 0.4 mm is often used for a base substrate of a semiconductor package, and these metals have a low bending rigidity and a laminated structure. Since the semiconductor package is drawn at the time of dimple processing, the processing accuracy of the dimple processing part and the entire surface of the package decreases due to the difference in the shape of these layers and the variation in the total thickness of the layers, making the dimple processing depth unsuitable for semiconductor mounting. Is formed by narrowing down to a depth equal to or greater than the thickness of the semiconductor chip (semiconductor device) (for example, about 0.3 to 0.6 mm). In the case of processing, twisting, twisting, etc. occur in the diagonal direction of the semiconductor package, causing external changes, and the entire package centering on that diagonal line Easily distorted phenomenon occurs,
In addition, as the size of the semiconductor chip increases, the area of the bottom of the dimple portion on which the semiconductor chip is mounted also increases, and in drawing by a press die, the center of the bottom of the dimple portion bulges and warps. There is a problem that a contact area between the semiconductor device and the bottom portion is reduced, and a problem occurs in a process of assembling the semiconductor device.

The dimple processing method for a semiconductor package and the semiconductor package according to the present invention have been made in order to solve the problems of the conventional dimple processing method for a semiconductor package. A stamping part around the periphery, a so-called push-out part, is formed separately after a certain process during dimple processing with a press die, and a semiconductor package with extremely good dimple flatness and package flatness is produced at low cost and mass production reliability. It is an object of the present invention to provide a dimple processing method of a semiconductor package and a semiconductor package which can be press-formed by using the method.

[0007]

SUMMARY OF THE INVENTION The present invention relates to a dimple processing method for a semiconductor package, and more particularly to a processing method for forming an embossed portion around the dimple processing and a semiconductor package processed by the processing method.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor package of the present invention (so-called metal BGA (abbreviation for Ball Grid Alley))
An embodiment of a dimple processing method and a semiconductor package processed by the method will be described with reference to the accompanying drawings.

As shown in FIG. 1, a semiconductor package 1 to be subjected to a dimple processing method according to the present invention has an insulating layer and a metal foil layer on a front surface 2 and a back surface 3 of a metal substrate 30. The layers are laminated as described above, and are formed by forming dimples (housing recesses, cavities) 4 having right-angled corners 4a and 4b by dimple processing using a press die. Then, in order to maintain the flatness of the surface 2 on the surface side of the dimple processing portion 4 which is the mounting surface of the semiconductor device, a stamping (crushing) portion such as a burnishing process at a predetermined location, that is, pressing by a so-called press die process. Killing parts are formed.

That is, first, in order to secure the flatness of the package, the semiconductor package 1 shown in FIG.
As shown in the perspective view of FIG. 1A, a plurality of, for example, four pressing steps 7 are formed on the surface side (circuit pattern side) of the semiconductor package 1 on a diagonal line thereof.
As shown in the longitudinal sectional view in (b), pushes killing unit 5,6 which is formed separately pressed after dimple machining or during machining by a press die working on the surface 2 and the back 3 side of the dimple machining periphery D ₁ further, as shown in the partial enlarged longitudinal sectional view of FIG. 1 (c), the adapted to a plurality of push killing portion 8 on the bottom D ₂ of the dimple processing portion 4 is formed.

FIGS. 2A and 2B and FIG. 3A
As shown in FIG. 2A with the back surface 3 side (the side opposite to the circuit pattern side) facing upward, in the semiconductor package 1, the dimple-processed peripheral portion D ₁ is provided within the range not affecting the package characteristics as shown in FIG. As shown in FIG. 2, a concave pressing portion 5 (for example, having a width of 0.3
mm or more, depth 0.03 mm or more) or FIG.
A step 9 as shown in FIG. By this dimple processing, the elongation of the dimple slope (4a) is utilized,
The generation of press-drawing pressure on the entire surface of the semiconductor package 1 is minimized. As a result, diagonal twists and the like generated in the diagonal direction of the semiconductor package 1 are suppressed, and the flatness of the semiconductor package 1 is extremely high. Get better.

When the insulating layer, the wiring pattern, and the like are removed from the metal base (base metal) 31 on the circuit pattern side of the semiconductor package 1 and the metal base 31 is exposed, the formed push-down is performed. If the width of the portion 5 is set to a width that allows wire bonding (for example, 0.35 mm or more), the pushing portion can be used as an earth ring of the semiconductor chip.

Further, as shown in FIG. 2A, when using a pressing die, a slight flat difference portion 7 is formed on the entire surface of the semiconductor package 1 by using a split die or a piece, for example, on a diagonal line. It is also possible to adjust the required flatness accuracy by reducing the press drawing stress generated during the press working.

Furthermore, as shown in FIG. 3 (b), the back surface side of the dimple machining perimeter D ₁ (the opposite side of the circuit pattern)
In this case, a convex (stepped) pressing portion 10 is formed on the semiconductor package 1 so that the flatness of the entire surface of the semiconductor package 1 can be adjusted. In addition, the formation of the pushing portion 10 causes the semiconductor package 1 to have a so-called step-drawing shape, thereby significantly improving the rigidity of the package.

Further, as shown in FIG. 3 (c), the circuit pattern P and the like formed on the semiconductor package 1 are extended to the bottom of the dimple processing part 4. If the body is damaged due to the characteristic and the reliability is not preferable, or if the required flatness accuracy of the package is not obtained, a concave (groove-shaped) pushing-out portion 11 (for example, from the back surface side of the semiconductor package 1). , Width 0.3mm or more, depth 0.03mm
Above). As a result, the occurrence of press drawing stress on the entire surface of the semiconductor package 1 is minimized, and the occurrence of diagonal torsion of the package and the like are suppressed. As a result, the flatness of the package is improved, and the entire surface of the package is improved. Can be adjusted.

[0016] In the above-described push-out formation,
As shown in FIG. 3D, it is preferable that the right-angle corners R ₁ and R ₂ of the dimple processing portion 4 be as small as possible within an appropriate range.

As shown in FIG. 3E, in the dimple processing of the above-described embodiment, the dimple processing corner 4c formed on the back surface side of the semiconductor package 1 is
Within a range that does not affect the characteristics of the pattern and the like, a break portion 12 having a slightly stepped shape (for example, a step difference of 0.01 mm or more) is formed. It can also be reduced by dispersing it in the processing section 4 and the entire surface of the package.

As shown in FIG. 5A, for example, an organic insulating layer 35 is formed on the back surface of the semiconductor package 1 and cracks C may be generated in the insulating layer 35 by dimple processing. Then, the bottom corner 4b of the dimple processing part 4 is chamfered (for example, chamfer of 0.1 mm) to prevent cracks on the back surface of the package 1.

Next, in order to secure the flatness of the bottom of the dimple, that is, the semiconductor chip mounting portion, FIG.
As shown in (g), the bottom part 4d of the dimple processing part 4
In addition, the pressing portions 13 and 14 which are concave from the front side (semiconductor chip mounting side) within a range that does not affect the package characteristics.
(For example, a depth of 0.03 mm or more) is formed at the corner or the center.

Due to the formation of the concave pushing portions 13 and 14, the stretching of the bottom portion 4d of the dimple portion 4 is utilized, and the flatness of the bottom portion 4d of the dimple portion 4 is extremely improved. The circuit pattern P and the like are shown in FIG.
As shown in (g), the bottom part 4d of the dimple processing part 4
In the case where it is extended to the extent, the pressing portion 14 is formed only on the semiconductor chip mounting surface.

Further, as shown in FIG. 4 (h), when the pushing killing unit 5 described above in the shape of its bottom portion 4d with dimples periphery D ₁ formed of 14 is not preferable, the dimple processing slope A pressing portion 15 is formed on the back side or both sides of 4a. The formation of the push-out portion 15 makes use of the elongation of the dimple slope 4a, thereby minimizing the occurrence of press drawing stress.

Apparatus used for dimple processing The apparatus used for the dimple processing method for a semiconductor package according to the present invention described above comprises a press die 20 provided in a press machine as shown in FIG.

That is, the left half of FIG. 6 shows a state in which the base material of the semiconductor package 1 before dimple processing is set between the die plate 21 and the stripper plate 22 of the press die 20, and the right half of FIG. , The punch 25 is lowered, and the head 25a is press-drawn to form a dimple-processed portion.

The press die 20 is provided with a die holder 27.
Die plate 21 placed on top of this die plate 2
1, the stripper plate 22, the stopper block 23, and the punch holder 24 are urged by a spring member, for example, a coil spring 28, and guided by two or four diagonal guide posts 29 to move up and down. I have. The head 25 is located at the center of the punch holder 24.
The punch 25 having a is inserted and lowered toward a press die set on the die plate 21 so as to press the pressure pad 26 inserted into the center of the die plate 21 to perform dimple processing on the semiconductor package 1. It is designed to be applied to metal substrates.

Then, the head 2 of the punch 25 is formed to form a pressing portion (pressed portion) on the base material of the semiconductor package 1.
A convex portion or a concave portion for forming a pressing portion is provided at a predetermined position of the press die set on 5a or the die plate 21.

According to the dimple processing method for a semiconductor package of the present invention, in order to form a depressed portion at a predetermined place at the same time as or after the dimple processing, the metal base material of the semiconductor package is formed one by one or several at a time. The strips are sequentially fed into a press die 20 to be subjected to only dimple processing or pressing processing.

FIGS. 7A and 7B are partially enlarged views of a punch 25 of a press die used in the dimple processing method of the present invention, and FIG. FIG. 7B shows a state after dimple processing.

As shown in FIG. 5B, in order to chamfer the corners of the bottom surface 4d of the dimple processing portion 4, the head 25a of the punch 25 as shown in FIG. 8 is chamfered 25c. Use something.

[0029]

According to the dimple processing method for a semiconductor package of the present invention, an embossed portion, a so-called pushing portion, is formed around the dimple processed portion of the package, so that the dimple flatness and the package flatness are extremely good. The semiconductor package can be processed at low cost and with high reliability in mass production.

[Brief description of the drawings]

FIG. 1 shows a semiconductor package processed by a dimple processing method for a semiconductor package according to the present invention, and FIG.
1 (a) is a perspective view, FIG. 1 (b) is a longitudinal sectional view, and FIG. 1 (c) is a partially enlarged longitudinal sectional view of the dimple processing portion.

FIG. 2 is a diagram showing the semiconductor package shown in FIG. 1 with the back surface side (the side opposite to the circuit pattern) facing upward, and FIG. 2A is a perspective view thereof, FIG. b) shows a longitudinal sectional view thereof.

3A and 3B show a form of a so-called pushing portion formed in a dimple-processed portion of the semiconductor package shown in FIG. 2; FIG. 3A shows a surface side (a circuit pattern side) of the dimple-processed portion; 3) shows an embodiment in which a pressing portion (step portion) is provided, and FIG. 3 (b) shows an embodiment in which a pressing portion (step portion) is provided on the back side of the dimple processing portion. )
FIG. 3D shows an embodiment in which R (roundness) is added to the right corners of the four corners of the dimple processing part, and FIG. 3E shows an embodiment of the dimple processing part. An embodiment in which a break portion is provided on the back surface side will be described.

FIG. 4 shows a so-called pushing portion formed in the dimple-processed portion of the semiconductor package, similarly to FIG. 3 described above, and FIG. FIG. 4 shows an embodiment in which a portion (groove) is provided.
(G) shows a pressing part (recess) on the front side of the dimple processing part, and FIG. 4 (h) shows an embodiment in which a pressing part is provided on the front side and the back side of the dimple processing part. Shown respectively.

5 shows a dimple-processed portion of a semiconductor package, similarly to FIG. 4 described above. FIG. 5 (a) shows an insulator (for example, an insulator (for example, FIG. 5 (b) is a partially broken longitudinal sectional view showing a crack in the organic insulator), and FIG. 5 (b) shows C ( (Chamfer) Each shows a partially broken longitudinal sectional view with chamfering.

FIG. 6 is a front view of a press die used for dimple processing of the semiconductor package of the present invention, the left half of which is before dimple processing, and the right half thereof is a dimple processing where a punch descends. This shows the state after performing.

7 is a partially enlarged front view of a punch portion of the press die shown in FIG. 6; FIG. 7 (a) shows a state before dimple processing, and FIG. 7 (b) shows a dimple This shows the state after processing.

FIG. 8 shows a head of a punch used for performing the C-chamfering process shown in FIG. 5 (b).

FIG. 9 is a longitudinal sectional view of a conventional semiconductor package.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor package 2 Front side (circuit pattern) side of semiconductor package 3 Back side of semiconductor package 4 Dimple processing part 4a Dimple processing slope 4b Bottom corner part of dimple processing part 4c Dimple processing corner part 4d Bottom part of dimple processing part 5-15 Pressing part (pressing part) 20 Press die 21 Die plate 22 Stripper plate 23 Stopper block 24 Punch holder 25 Punch 26 Pressure pad 27 Die holder 28 Spring member 29 Guide post D ₁ Dimple processing peripheral part D ₂ Dimple processing bottom part R ₁ , R ₂ right side corner C crack occurrence part

Claims (10)

[Claims] 1. A dimple processing method for a semiconductor package, wherein a stamped portion is formed around the dimple processing. 2. The processing method according to claim 1, wherein the embossed portion is a plurality of steps formed on a diagonal line on a circuit pattern side of the semiconductor package. 3. The processing method according to claim 1, wherein the embossed portion is formed on one or both of the circuit pattern side and the opposite side of the dimple processing peripheral portion. 4. The processing method according to claim 1, wherein the embossed portion is formed on a bottom surface of the dimple processing portion. 5. The processing method according to claim 1, wherein the embossed portion is a step formed on a circuit pattern side around a dimple process. 6. The method according to claim 1, wherein the embossed portion is a step formed on the back surface side of the periphery of the dimple processing.
The processing method described in 1. 7. The processing method according to claim 1, wherein the embossed portion is a groove formed on a back surface side of a peripheral portion of dimple processing. 8. The processing method according to claim 1, wherein the embossed portion is a broken portion obtained by breaking a processing corner portion around a dimple processing stepwise. 9. The processing method according to claim 1, wherein the embossed portion is formed on the back side of the dimple processing slope or on both the back side and the front side. 10. A semiconductor package processed by the processing method according to any one of claims 1 to 9.