JP2001022685A - Device and method for transferring data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for transferring data with which series of data can be transferred to any arbitrary register while changing the order of each data. SOLUTION: By referring to an address translation look-up table storing the corresponding relation of an index address and a physical address, the index address designating the transfer destination of vertex data is translated to the physical address and the vertex data are transferred to a register existent in the space of that physical address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device and a data transfer method for transferring a series of data to a register built in an I / O control LSI using a DMA controller or the like.

[0002]

2. Description of the Related Art In a conventional data transfer device, when a series of data stored in a storage device is transferred to a group of registers built in an LSI, a DMA controller reads the series of data from the storage device and increments an address. While updating the transfer destination register, a series of data is transferred to the register group. The above data transfer device is applied to a graphics LSI, for example, as described in U.S. Pat. S. Patent 5,777,629.

[0003]

Since the conventional data transfer device is configured as described above, a series of data read from the storage device is built in the LSI without changing the order of the data. Is transferred to the register group. Therefore, when a series of data is stored in the storage device, there is a problem that it is necessary to store the data in consideration of the arrangement of the registers constituting the register group.

[0004] The present invention has been made to solve the above-described problems, and changes the order of a series of data,
An object of the present invention is to provide a data transfer device and a data transfer method capable of transferring each data to an arbitrary register.

[0005]

A data transfer device according to the present invention refers to an address conversion table for storing a correspondence between an index address and a physical address, and converts an index address output from a transfer request unit to a physical address. And a data transfer means for transferring data output from the storage device to a register existing in the space of the physical address.

A data transfer device according to the present invention converts an index address output by a transfer request unit into an intermediate address with reference to an address conversion table, and adds a base address to the intermediate address to convert a physical address. Data transfer means for generating and transferring data output from the storage device to a register existing in the space of the physical address is provided.

[0007] The data transfer device according to the present invention is provided with changing means for changing the correspondence stored in the address conversion table.

The data transfer method according to the present invention converts an index address designating a data transfer destination into a physical address with reference to an address conversion table storing a correspondence between an index address and a physical address. The data output from the storage device is transferred to a register existing in the space of the physical address.

The data transfer method according to the present invention converts an index address designating a data transfer destination into an intermediate address with reference to an address conversion table, and adds a base address to the intermediate address to add a physical address. Is generated, and data output from the storage device is transferred to a register existing in the space of the physical address.

In the data transfer method according to the present invention, a change of the correspondence stored in the address conversion table is permitted.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a data transfer device according to a first embodiment of the present invention. In the drawing, 1 is a storage device for storing vertex data, 2 is a core logic for controlling the transfer of vertex data, and 3 is PCI and AGP (Ac
An I / O bus such as "Certified Graphics Port", and a source address I of the vertex data
A DMA control unit (transfer request unit) that outputs data to the / O bus 3 to request data transfer and outputs an index address designating a transfer destination of the data to the address conversion unit 6.

Reference numeral 5 denotes an address conversion look-up table (address conversion table) for storing the correspondence between index addresses and physical addresses, and reference numeral 6 denotes an address conversion look-up table 5 which is output by the DMA controller 4. An address conversion unit (data transfer means) for converting an index address into a physical address and transferring vertex data to a register existing in the space of the physical address; 7 is a register group including a plurality of registers;
Reference numeral 8 denotes a rendering processing unit that obtains vertex data from the register group 7 and performs a drawing process. Reference numeral 9 denotes a CPU (change unit) that changes the correspondence stored in the address conversion lookup table 5. FIG. 2 is a flowchart showing a data transfer method according to the first embodiment of the present invention.

Next, the operation will be described. In the first embodiment, as shown in FIG. 3, among the vertex data stored in the storage device 1, X,
A case where vertex data stored in the order of A, Y, R, G, B, and Z is transferred to the register group 7 will be described. Here, X and Y are screen coordinates, Z is a depth value, R, G,
B and A indicate the red, green, blue, and alpha values of the pixel, respectively.

First, when the DMA controller 4 requests the transfer of vertex data by outputting the source address of the vertex data to the I / O bus 3 (step ST1),
Logic 2 receives the source address of the vertex data from I / O bus 3. Thus, the core logic 2
The vertex data stored with the source address as the head address is read from the storage device 1, and the vertex data is output to the I / O bus 3, and the DMA control unit 4
The vertex data is received from the bus 3 (step ST2).

When outputting the source address to the I / O bus 3, the DMA controller 4 outputs the index address to the address converter 6 (step ST).
1) Output the vertex data received from the I / O bus 3 to the address conversion unit 6.

When receiving the index address from the DMA control unit 4, the address conversion unit 6 refers to the address conversion look-up table 5 and reads the index address.
The address is converted to a physical address (step ST3),
The vertex data is transferred to the register existing in the space of the physical address (step ST4).

In the example of FIG. 3, since data X is first transferred to the register, address 0 is used as a physical address corresponding to the index address.
The data X is read from the table 5 and transferred to the register at the address 0 in the register group 7.

Next, in order to transfer the data A to the register, when the source address and the index address are incremented, the address 6 is read from the address conversion look-up table 5 as a physical address corresponding to the index address. Then, the data A is transferred to the register at the address 6 in the register group 7. Hereinafter, the data Y, R, G, B, and Z are similarly transferred to the registers of the register group 7.

When it is necessary to change the arrangement of the vertex data or the arrangement of the registers constituting the register group 7, the CPU 9 outputs a change command to the address conversion look-up table 5 to change the address conversion look-up table. The correspondence stored in the up table 5 can be changed.

As is clear from the above, the first embodiment
According to the reference, the address conversion lookup table 5 storing the correspondence between the index address and the physical address is referred to, the index address specifying the transfer destination of the vertex data is converted into the physical address, and the physical address of the physical address is converted. Since the configuration is such that the vertex data is transferred to the registers existing in the space, the order of the series of vertex data can be changed, and each data can be transferred to an arbitrary register. When a series of vertex data is stored in the device, there is an effect that it is not necessary to store the data in consideration of the arrangement of the registers constituting the register group.

Thus, in particular, OpenGL and Dir
3D graphics driver S / W such as ect3D
Can prepare data on the storage device 1 and transfer it to a graphics LSI or the like by the most efficient method without depending on the H / W register array, so that the processing can be speeded up. it can.

Embodiment 2 FIG. In the first embodiment, the case where the address conversion look-up table 5 and the address conversion unit 6 are provided independently has been described. However, the address conversion unit 6 may include the address conversion look-up table 5. Thus, the same effect as in the first embodiment can be obtained.

In the first embodiment, the DMA controller 4 receives the vertex data from the I / O bus 3 and outputs the data to the address converter 6, but the address converter 6 directly receives the I / O data. The vertex data may be received from the O bus 3, and the same effect as in the first embodiment can be obtained.

Further, in the first embodiment, the case where the vertex data stored in the storage device 1 is transferred to the register group 7 has been described. However, the present invention is not limited to the vertex data, and other series of data may be transferred. You may make it.

Embodiment 3 FIG. 4 is a configuration diagram showing a data transfer device according to a third embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 denote the same or corresponding parts, and a description thereof will not be repeated. Reference numeral 11 denotes an address conversion look-up table (address conversion table) for storing the correspondence between index addresses and intermediate addresses, and reference numeral 12 denotes a DMA by referring to the address conversion look-up table 11.
An address conversion unit (data transfer unit) for converting an index address output by the control unit 4 into an intermediate address;
Reference numeral 3 denotes a base address generation unit (data transfer means) for generating a base address of the register group 7, and 14 adds a base address to the intermediate address converted by the address conversion unit 12 to generate a physical address. An adder (data transfer means) for transferring vertex data to a register existing in the space.

Next, the operation will be described. In the first embodiment, an example in which the order of a series of vertex data is changed and each data is transferred to an arbitrary register has been described.
When a plurality of register groups having the same configuration are installed like a vertex register used in three-dimensional graphics,
A series of vertex data may be transferred as follows.

In the third embodiment, as shown in FIG. 5, among the vertex data stored in the storage device 1, X1, A1, Y1, R1, G
1, B1, Z1, X2, A2, Y2, R2, G2, B
The case where vertex data stored in the order of 2, 2 is transferred to the register group 7 will be described. However, register group 7
Is a register group for storing the vertex data of vertex 1 and vertex 2
And a register group for storing the vertex data.

Specifically, when the address conversion unit 12 receives the index address and the vertex data from the DMA control unit 4 in the same manner as in the first embodiment, the address conversion unit 12 refers to the address conversion lookup table 11 and The index address is converted into an intermediate address, and the base address generator 13 outputs the base address of the register group 7. As will be described in detail later, when transferring the vertex data of vertex 1, for example, address 10 is output, and when transferring the vertex data of vertex 2, address 20 is output.

When the address converter 12 outputs the intermediate address and the base address generator 13 outputs the base address, the adder 14 generates a physical address by adding the base address to the intermediate address. The vertex data is transferred to the register existing in the space.

In the example of FIG. 5, the data X1
To the register, address 0 is read from the address conversion look-up table 11 as an intermediate address corresponding to the index address, and address 10 is output from the base address generator 13 as the base address related to vertex 1. . As a result, the physical address that is the result of adding the intermediate address and the base address becomes address 10, so that the data X1 of vertex 1 is transferred to the register at address 10 in the register group 7.

Next, in order to transfer the data A1 of the vertex 1 to the register, when the source address and the index address are incremented, the address 6 is used as an intermediate address corresponding to the index address. From vertex 1
Is output from the base address generation unit 13 as the base address according to. As a result, the physical address which is the addition result of the intermediate address and the base address is 1
Since the address is 6, the data A1 at the vertex 1 is transferred to the register at the address 16 in the register group 7. Hereinafter, similarly, data Y1, R1, G1, B1, Z1 of vertex 1
Is transferred to the registers of the register group 7.

When the vertex data of the vertex 1 is transferred in this way, the data X2 of the vertex 2 is transferred to the register. The source address is incremented and the index address is reset. The address 0 is read from the address conversion look-up table 11 as an intermediate address corresponding to the index address, and the address 20 is output from the base address generator 13 as the base address related to the vertex 2. As a result, the physical address that is the result of the addition of the intermediate address and the base address becomes address 20, so that the data X2 of vertex 2 is transferred to the register at address 20 in the register group 7.

Next, in order to transfer the data A2 at the vertex 2 to the register, when the source address and the index address are incremented, address 6 is used as an intermediate address corresponding to the index address. From vertex 2
Is output from the base address generation unit 13 as the base address according to. As a result, the physical address that is the result of adding the intermediate address and the base address is 2
Since the address is 6, the data A2 at the vertex 2 is transferred to the register at the address 26 in the register group 7. Hereinafter, similarly, the data Y2, R2, G2, B2, Z2 of the vertex 2
Is transferred to the registers of the register group 7.

When it is necessary to change the arrangement of the vertex data and the arrangement of the registers constituting the register group 7, the CPU 9 outputs a change command to the address conversion look-up table 11 so that the address conversion look-up table 11 is output. The correspondence stored in the up table 11 can be changed.

As is clear from the above, this embodiment 2
According to the method, the index address specifying the data transfer destination is converted into an intermediate address with reference to the address conversion look-up table 11, and the base address is added to the intermediate address to generate a physical address. Since the configuration is such that vertex data is transferred to registers existing in the space of the physical address, even when a plurality of register groups having the same configuration are prepared like a three-dimensional graphics LSI, a series of vertex data is stored. By changing the order, each data can be transferred to an arbitrary register. As a result, when a series of vertex data is stored in the storage device, the data is stored in consideration of the arrangement of the registers constituting the register group. This has the effect of eliminating the need to do so.

Thus, in particular, OpenGL and Dir
3D graphics driver S / W such as ect3D
Can prepare data on the storage device 1 and transfer it to a graphics LSI or the like by the most efficient method without depending on the H / W register array, so that the processing can be speeded up. it can.

[0037]

As described above, according to the present invention, the index address output by the transfer request means is converted into the physical address by referring to the address conversion table storing the correspondence between the index address and the physical address. The data transfer means for transferring the data output from the storage device to the register existing in the space of the physical address is provided. Therefore, the order of the series of data is changed, and each data is stored in an arbitrary register. As a result, when a series of data is stored in the storage device, there is an effect that it is not necessary to store the data in consideration of the arrangement of the registers constituting the register group.

According to the present invention, by referring to the address translation table, the index address output by the transfer request means is translated into an intermediate address, and the base address is added to the intermediate address to generate a physical address. Since the data transfer means for transferring the data output from the storage device to the register existing in the space of the physical address is provided, the three-dimensional graphics LS
Even if a plurality of register groups having the same configuration are prepared as in I, the order of a series of data can be changed and each data can be transferred to an arbitrary register.
As a result, when storing a series of data in the storage device, there is an effect that it is not necessary to store the series of data in consideration of the arrangement of the registers constituting the register group.

According to the present invention, since the changing means for changing the correspondence stored in the address conversion table is provided, it is necessary to change the array of a series of data and the array of registers constituting the register group. Occurs,
There is an effect that can be easily dealt with.

According to the present invention, the index address specifying the data transfer destination is converted into the physical address with reference to the address conversion table storing the correspondence between the index address and the physical address. Since the data output by the storage device is transferred to the registers existing in the space, the order of a series of data can be changed, and each data can be transferred to an arbitrary register. As a result, when a series of data is stored in the storage device, there is an effect that it is not necessary to store the series of data in consideration of the arrangement of the registers constituting the register group.

According to the present invention, the index / designation of the data transfer destination is performed with reference to the address conversion table.
The address is converted to an intermediate address, a base address is added to the intermediate address to generate a physical address, and data output from the storage device is transferred to a register existing in the space of the physical address. Therefore, even when a plurality of register groups having the same configuration are prepared like a three-dimensional graphics LSI, the order of a series of data can be changed and each data can be transferred to an arbitrary register. As a result, when storing a series of data in the storage device, there is an effect that it is not necessary to store the series of data in consideration of the arrangement of the registers constituting the register group.

According to the present invention, since the change of the correspondence stored in the address conversion table is permitted, it is necessary to change the arrangement of a series of data and the arrangement of the registers constituting the register group. However, there is an effect that can be easily dealt with.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a data transfer device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a data transfer method according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram illustrating address conversion.

FIG. 4 is a configuration diagram showing a data transfer device according to a third embodiment of the present invention.

FIG. 5 is an explanatory diagram illustrating address conversion.

[Explanation of symbols]

1 storage device, 4 DMA control unit (transfer request means),
5, 11 Address conversion lookup table (address conversion table), 6, 12 Address conversion unit (data transfer means), 7 register group (register), 9 CP
U (change means), 13 base address generator (data transfer means), 14 adder (data transfer means).

Claims (6)

[Claims] Transfer request means for outputting a source address of data stored in a storage device, requesting data transfer, and outputting an index address designating a destination of the data; and an index address. With reference to the address conversion table for storing the correspondence between the address and the physical address, and referring to the address conversion table, the index address output by the transfer request means is converted into the physical address, and the register existing in the space of the physical address A data transfer unit for transferring data output from the storage device. 2. A transfer request means for outputting a source address of data stored in a storage device, requesting data transfer, and outputting an index address designating a destination of the data, and an index address. With reference to the address conversion table for storing the correspondence between the address and the intermediate address, and referring to the address conversion table, the index address output by the transfer request means is converted into the intermediate address, and the base address is added to the intermediate address. A data transfer unit for generating a physical address by using the data transfer unit and transferring data output from the storage device to a register existing in a space of the physical address. 3. The data transfer device according to claim 1, further comprising changing means for changing the correspondence stored in the address conversion table. 4. A data transfer request by outputting a source address of data stored in a storage device and outputting an index address designating a transfer destination of the data, wherein the index address and the physical address of the physical address are output. Referring to an address conversion table for storing the correspondence, an index address designating a transfer destination of the data is converted into a physical address, and data output from the storage device to a register existing in the space of the physical address. Transfer data transfer method. 5. A data transfer request by outputting a source address of data stored in a storage device and outputting an index address designating a transfer destination of the data, wherein the index address and the intermediate address are output. Referring to an address conversion table for storing the correspondence, the index address specifying the transfer destination of the data is converted into an intermediate address, and the base address is added to the intermediate address to generate a physical address. A data transfer method for transferring data output from the storage device to a register existing in an address space. 6. The data transfer device according to claim 4, wherein a change of the correspondence stored in the address conversion table is permitted.