JP3067458B2 - 3D graphics drawing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a three-dimensional graphics drawing apparatus mounted on a work station or the like to display a three-dimensional image. Mechanical CAD and architectural CAD
An expensive graphic workstation has been used for three-dimensional display. However, with the cost reduction of workstations, it is necessary to use the method so that the design result can be confirmed in three dimensions because it may be late, and a low-cost three-dimensional graphics rendering apparatus that matches low-cost workstations is required. Have been.

[0002]

2. Description of the Related Art FIG. 5 shows a three-dimensional graphics drawing mechanism mounted on a conventional workstation. In FIG. 5, a main storage unit (MSU) 18 is connected to a bus 12 of a central processing unit (hereinafter referred to as a “CPU”) via a main storage control unit (MCU) 16 and a three-dimensional drawing mechanism 62 is connected. Is done.

The three-dimensional drawing mechanism 62 includes frame memories 22, 24, which store pixel data (for example, RGB color values) corresponding to two-dimensional display coordinates (x, y) of three-dimensional image data on a screen basis. 26, and Z buffer memories 70, 72, and 74 for storing the z value, which is the depth component of the three-dimensional image data, on a screen basis. The CPU 10 expresses 3 as a set of polygons using minute triangles and quadrilaterals.
It handles dimensional objects, and each polygon has vertex coordinates (x,
y, z) and the color value of each vertex, for example, RGB data. At the three-dimensional object drawing, C PUs 10 are polygon vertex coordinates (x, y, z) developed from the pixel fill the face of the polygon, pixel coordinates (x, y, z) and the RGB pixel data for each pixel The data is supplied to the three-dimensional drawing mechanism as three-dimensional drawing data. Note that the three-dimensional coordinates of the polygon vertices are in the form of vector data that can be treated as relative coordinates in order to reduce the amount of data.

The three-dimensional drawing mechanism 62 writes RGB pixel data to the frame memory 22 by, for example, specifying an address based on two-dimensional coordinates (x, y) of a drawing screen, and at the same time,
The depth coordinates (z1) of the pixel are written in the Z buffer memory 70 by addressing with the dimensional coordinates (x, y). Similarly, for another drawing screen, the RGB pixel data is transferred to another frame 2 by specifying the address using the two-dimensional coordinates (x, y).
4 and the depth coordinate (z2) to the Z buffer memory 72 at the same time.

[0005] After the drawing on the frame memories 22 and 24 is completed, the depth coordinates (z1, z2) of the three-dimensional drawing mechanism 62 and the Z buffers 70 and 72 corresponding to the frame memories 22 and 24 are set for each pixel. The pixel data is read out and compared, and the RGB pixel data in the frame memory 22 or 24 is read out with the pixel located in the front as valid, and is written and drawn in the frame memory 26 storing the composite screen. When the drawing of the composite image in the frame memory 26 is completed, the display control unit 2
8, the composite image is displayed on the color display 30.

[0006]

However, in such a conventional three-dimensional graphics rendering apparatus mounted on a workstation, two-dimensional coordinates (x, y) are not used.
And a Z buffer memory for storing depth coordinates (z) with exactly the same address designation in addition to the frame memory addressed by
The additional provision of the buffer memory results in an increase in the memory capacity, which leads to an increase in cost.

In order to solve this problem, it is conceivable to place a Z buffer memory on the main storage device 18 of the CPU 10. However, if the Z-buffer memory is placed on the main storage device 18 of the CPU 10, access to the Z-buffer memory will be via the bus of the CPU 10, and access will inevitably be slowed down, lowering the drawing performance. When a Z buffer area is secured in a fixed area after the address 0 in the main storage device 18 , it must be secured as an area having a size corresponding to the maximum number of screens to be synthesized in the depth direction. The fixed area 18 is an area in which an initialization program and the like are stored, and there is a disadvantage that the fixed area is restricted. In addition, when the number of combined screens is small, there is a problem that the unused area increases and the utilization efficiency of the main storage device 18 is low.

The present invention has been made in view of such a conventional problem. Even if the Z-buffer is arranged in the main storage device to reduce the price, the three-dimensional image can be formed without deteriorating the drawing performance. It is an object to provide a drawing device.

[0009]

FIG. 1 is a diagram illustrating the principle of the present invention. The three-dimensional graphic rendering apparatus of the present invention includes a three-dimensional rendering mechanism 20 having a main bus 12 and a local bus 32, and three-dimensional rendering data (x, y, z pixels) transmitted to the three-dimensional rendering mechanism 20 via the main bus 12. A CPU (Central Processing Unit) 10 for supplying coordinates and pixel color values), and a main storage controller 16 for selectively receiving access from the CPU 10 via the main bus 12 and access from the three-dimensional drawing mechanism 20 via the local bus 32. A main storage device 1 that stores drawing information to be handled by the three-dimensional drawing mechanism 20 in a predetermined area 34 assigned in advance in addition to information to be handled by the CPU 10.
8 is provided.

That is, the three-dimensional drawing mechanism 20 specifies the drawing information storage area 34 allocated to the main storage device 18 and writes the depth information (Z value) of the three-dimensional image in units of screens.
When synthesizing the two-dimensional image information, there is provided a depth control means 36 for reading and comparing the depth information in the main storage device 18 and selecting and drawing the image information located closest to the front.

The depth control means 36 is provided in the main storage device 18.
The offset address that specifies the head position of the drawing information storage area 34 assigned to the address is stored as the upper address, and the X and Y addresses of the frame memory that indicates the drawing position specified by the two-dimensional display coordinates are stored as the lower address. The main memory 18 is connected to the local bus 32 using the storage address of the address register.
Access directly through.

The offset address of the address register provided in the depth control means 36 can be set by an initialization program of the CPU 10 or an application program executed by the CPU 10.

[0013]

According to the three-dimensional graphic drawing apparatus of the present invention having such a configuration, a special high-speed bus is provided as a local bus between the three-dimensional drawing mechanism and the main storage control device, and the main storage device is provided. By making the A buffer area directly accessible, high-speed drawing processing can be performed even if the Z buffer is placed on the main storage unit to reduce the price.

The depth control unit of the three-dimensional drawing mechanism is provided with an offset address register for designating the start position of the Z buffer area on the main memory so that the Z buffer area can be located at an arbitrary position in the main memory. , To improve the efficiency of memory use. Therefore, the Z-buffer memory is not required and the price of the drawing mechanism can be reduced without deteriorating the performance of the three-dimensional drawing mechanism.

[0015]

FIG. 2 is a block diagram showing an embodiment of the present invention using a workstation as an example. In FIG. 2, a main storage device 18 is connected via a main storage control device 16 to a main bus 12 serving as a bus of a CPU 10 provided in a workstation. Furthermore, the main bus 12
Is connected to the cache memory 14 as a secondary storage device. The CPU 10 accesses the main storage device 18 only when the cache memory 14 does not hit. By providing the cache memory 14, the access frequency of the main storage device 18 is reduced and high-speed processing is enabled.

A three-dimensional drawing mechanism 20 is connected to the main bus 12 of the CPU 10. The three-dimensional drawing mechanism 20 includes frame memories 22, 24 for reading and writing RGB pixel data by addressing by two-dimensional coordinates (x, y).
26 are provided. The pixel data of the frame memory is, for example, a color value composed of bit data of three components of R, G, and B.

For the composite drawing of a three-dimensional image, at least three
One frame memory is required. Two of these frame memories store RGB pixel data before synthesis, and the other frame memory stores RGB pixel data of a synthesized image obtained by synthesizing two three-dimensional images in the depth direction. Store. Of course, for convenience of explanation, they are shown separately in the frame memories 22, 24, and 26, but one memory unit may be used by being divided into three areas.

A display controller 28 is provided following the frame memories 22, 24 and 26. The display controller 28 reads out a composite image from a specific frame memory obtained by combining two screens and converts it into an analog signal. 30 is displayed. The display control unit 28 is provided with a look-up table for performing various color conversions. For example, when a pallet conversion mechanism is employed to reduce the number of bits of the pixel data in the three-dimensional drawing mechanism 20, the pixel data processed as the address data of the pallet table is stored in the look-up table of the display control unit 28. RGB
Perform processing to convert to data.

In the case of the color display 30, R
Although the data may be GB data, when the output device is a printer device using the CMYK space, the color conversion from the RGB space to the CMYK space is performed. In addition, the three components of pigment, saturation, and brightness, which are known as a color space that reflects human color perception, are expressed from RGB space to XYZ space, L ^* a ^* b ^* space, or L ^* u ^* v ^* space. HSB space and SSV
Conversion to space or the like is also possible. Furthermore, when the RGB space has a linear characteristic, the color space can be converted to a non-linear characteristic, and further, the color resolution can be increased by performing a bit-up operation to increase the number of bits of the pixel data.

The three-dimensional drawing mechanism 20 has a local bus 32 in addition to the main bus 12.
2 is directly connected to the main memory control device 16.
The main memory control device 16 receives both the access from the main bus 12 of the CPU 10 and the access from the local bus 32 of the three-dimensional drawing mechanism 20, and writes or reads the main memory device 18.

Naturally, when the access from the main bus 12 and the access from the local bus 32 conflict with each other, the higher priority bus access is selected according to the priority mode setting at that time, and the main access is selected. The read or write of the storage device 18 is performed. The Z buffer area 3 allocated in advance to the three-dimensional drawing mechanism 20 is stored in the main storage device 18.
4, the three-dimensional drawing apparatus 20 accesses the Z buffer area 34 using the local bus 32.

FIG. 3 is a block diagram showing an embodiment showing details of the three-dimensional drawing mechanism of FIG. 2 and a main memory control device connected by a local bus. 3, the three-dimensional drawing mechanism 20 includes an address register 38 that generates an address for accessing the Z buffer area 34 of the main storage device 18. The address register 38 stores the upper offset address 40
And a lower X address 42 and a lower Y address 44.

In the offset address 40, the main storage 1
The offset value up to the start position of the Z buffer area 34 provided with 8 is set by the CPU 10. In this embodiment, since three frame memories 22, 24, and 26 are provided, the Z buffer area 34 of the main storage device 18
It is divided into three buffer areas 34-1, 34-2, 34-3 corresponding to the respective frame memories 22, 24, 26.

Therefore, three offset values corresponding to the divided buffer areas 34-1 to 34-3 are prepared in the CPU 10, and an offset value suitable for access to the frame memories 22, 24, 26 is set as an offset address 40 as an offset register. Set to 38. Thus the CPU
10 can arbitrarily change the value of the offset address 40 as needed and place the Z buffer area 34 in an arbitrary area of the main storage device 18.

The CPU 10 stores the X address 42 and the Y address 44 of the address register 38 in the frame memory 2.
Two-dimensional coordinates (x, y) used for specifying an address when accessing 2, 24, or 26 are set for each pixel. The values of the X address 42 and the Y address 44 are used to specify the drawing address of the frame 22, 24, or 26, and at the same time, the divided buffer areas 34-1 to 34-3 specified by the offset address 40 of the main storage device 18.
Is used to specify the address of one of the z data storage positions.

Here, the CPU 10 handles a three-dimensional object represented by a set of polygons using minute triangles or quadrilaterals, and each polygon has vertex coordinates (x, y, z) and a color value of each vertex, for example, RGB. Consists of data. When drawing a three-dimensional object, the CPU 10 determines the vertex coordinates (x,
(y, z) is expanded to pixels that fill the polygon surface, and pixel coordinates (x, y, z) and pixel RGB data are
It is supplied to the three-dimensional drawing mechanism 20 as three-dimensional drawing data.

The three-dimensional drawing mechanism 20 converts the two-dimensional coordinates (x, y) in the three-dimensional drawing data (x, y, z, RGB pixel data) supplied from the CPU 10 into X addresses 42, Y
Set to address 44. RG from the CPU 10
The B pixel data is given to the frame control unit 34, and the frame memory 2 is designated by an address using two-dimensional coordinates (x, y).
2, 24, 26.

Further, z data indicating the depth coordinates of each pixel supplied from the CPU 10 is supplied from the depth control unit 36 to the main storage control device 16 via the local bus 32.
The data is written into one of the divided buffer areas 34-1 to 34-3 of the main storage device 18 specified by the offset value of the address register 38. That is, the z data supplied from the CPU 10 is supplied from the selector 50 to the main storage controller 16 via the local bus 32. The main storage controller 16 is provided with an address selector 46 and a data selector 48, and can select either the main bus 12 or the local bus 32. Depth control unit 36
In the state where z data is supplied from the CPU 10 to the divided buffer areas 34-1 to 34-3, the value of the offset address 40 set in the address register 38 is used.
Is specified, and the address specified by the X address 42 and the Y address 44 in the area specified at the same time is
Write z data from PU10.

The processing of synthesizing a plurality of screens after storing the three-dimensional drawing data in the frame memory and the Z buffer area 34, so-called merge control, is performed by the registers 54 and 56 provided in the three-dimensional drawing mechanism 20, a comparator 58, and a frame control unit. This is performed under the control of the depth control unit 36 using. Now, the first image is drawn in the frame memory 22, and its depth coordinate is z1 in the divided Z buffer area 34-1.
And stored in the frame memory 24 as second data.
It is assumed that an image is drawn and its depth coordinates are stored as z2 data in the divided Z-far area 34-2.

In this state, the CPU 10
Assuming that merge control for combining the two screens stored in 2 and 24 is instructed, the CPU 10 sets a read address in the address register 38 of the three-dimensional drawing mechanism 20. That is, the first two-dimensional coordinates (x, y) are set at the same time as the offset value of the divided buffer area 3-1 is set, and the depth control unit 36 requests the main storage control device 16 to perform read access via the local bus 32. I do. The selector 46 of the main storage controller 16 selects the address value of the address register 38 supplied via the local bus 32, and selects the z1 data of the divided buffer area 34-1 of the main storage controller 16 corresponding to the frame memory 22. Is read and set in the register 54.

Subsequently, the value of the offset address 40 is updated to the offset value of the divided buffer area 34-2 corresponding to the frame memory 24, and the address in the area is designated by the same X address 42 and Y address 44, and z2 The data is read out and set in the register 56. Registers 54 and 5
6 is set by the selector 52. When the data depth data z1 and z2 of the same frame address for two screens can be set in the registers 54 and 56 in this way, the comparator 58 compares the two depth data z1 and z2 and selects the comparison result as the select information. Is output to the frame control unit 34. The frame control unit 34 validates the smaller one of the two pieces of depth data z1 and z2, that is, the one located closer to the front, and stores one of the valid frame memories 22 or 24 as the X address 42 and Y at that time.
Reads RGB pixel data specified by address 44,
The data is written to the position specified by the X address 42 and the Y address 44 in the frame memory 26 for synthesis.

By performing the synthesizing process using such depth information for all pixels, it is possible to draw two-dimensional image data synthesized according to the depth information on the frame memory 26. The synthesized image data drawn in the frame memory 26 is transferred to the display control unit 28 at a frame cycle, converted into an analog signal after desired conversion by a look-up table, and displayed on the color display 30.

In the embodiments shown in FIGS. 2 and 3, three frame memories are provided for the sake of simplicity, but the number of the frame memories is limited to the depth image to be synthesized by the three-dimensional drawing mechanism 20. It can be determined appropriately according to the number. Further, the Z buffer area 34 secured in the main storage device 18 only needs to secure a capacity required for the number of screens used for synthesizing the depth images, that is, the number of frame memories.

Further, in the embodiment shown in FIG.
The switching designation of the divided buffer areas 34-1 to 34-3 corresponding to the frame memories 22, 22, and 24 is performed by changing the offset value, but the offset value is fixed to the head position of the Z buffer area 34, and X The reading and writing of z data may be performed by setting the address and the Y address as consecutive addresses in the three frame memories 22, 24, and 26.

In this case, the X address 42 and the Y address 44 set in the address register 38 cannot be used as they are for addressing the frame memories 24 and 26 other than the first frame memory 22. The value may be a value obtained by subtracting the address value. FIG. 4 is a block diagram showing an embodiment showing another embodiment of the present invention. In this embodiment, in order to reduce the processing load on the CPU side, the three-dimensional rendering mechanism side uses 3D polygons. It is characterized by having a drawing operation mechanism for developing three-dimensional drawing data from pixel data into pixel units. FIG.
1, the main bus 12 of the CPU 10 is connected to the main storage device 1 via the cache memory 14 and the main storage control device 16.
8 are provided. On the other hand, a three-dimensional graphics drawing unit 100 is provided for the main bus 12.

A three-dimensional graphics drawing unit 100
Is composed of a drawing operation mechanism 60, a three-dimensional drawing mechanism 62, frame memories 22 and 24 for drawing, a depth control mechanism 64, a two-dimensional drawing mechanism 66, a frame memory 26 for display, and a display control unit 28. The drawing operation mechanism 60 includes the CPU 10
A three-dimensional data composed of the vertex coordinates (x, y, z) and the vertex RGB data (color value) of the polygon in FIG. Into three-dimensional drawing data
The pixel coordinates (x, y, z) and RGB pixel data for each pixel are supplied to the three-dimensional drawing mechanism 62.

The three-dimensional drawing mechanism 62 has two-dimensional coordinates (x,
y), the RGB pixel data is written into the frame memories 22 and 24 by the address designation, and at the same time, the local divided buffer in the Z buffer area 34 of the main memory 18 via the main memory controller 16 via the local bus 32. The areas 34-1 and 34-2 are accessed and the frame memory 2 is accessed.
Writing of z data corresponding to 2,24 writing pixels is performed. That is, the three-dimensional drawing mechanism 62 has a function as a writing control unit for the Z buffer area 34 of the depth control unit 36 provided in the three-dimensional drawing mechanism 20 in FIG.

The depth control mechanism 64 includes the frame memory 22,
The XY address for reading the frame memories 22 and 24 and the CPU 10
The main storage device 18 is read-accessed via the local bus 32 and the main storage control device 16 using the offset address set. In this lead axe, Z
2 for each frame memory 22 and 24 from the buffer area 34
The two depth data z1 and z2 are read, and the frame memory corresponding to the smaller depth data is validated as RGB.
The data is read and supplied to the two-dimensional drawing mechanism 66.

The two-dimensional drawing mechanism 66 writes the RGB data supplied from the depth control mechanism 64 into the display frame memory 26 by specifying the XY address at that time. By performing this processing for one screen, a composite image in the depth direction of two screens can be obtained in the frame memory 26. The two-dimensional drawing mechanism 66 is used to transfer and write the depth synthesized image from the depth control mechanism 64 to the display frame memory 26,
Window control can be directly received from the main bus 12 of U10. The two-dimensional drawing mechanism 66 has a CPU
When the window control is further performed, in this embodiment, since the three-dimensional drawing side can operate independently, the three-dimensional drawing on the frame memories 22 and 24 can be performed in parallel during that time.

The processors used for the three-dimensional drawing mechanism 62 and the depth control mechanism 64 include a global bus and a local bus 32 used as the main bus 12 and a DSP or the like which can control each bus independently. Just use it. Further, in the embodiment of FIG. 4, the drawing operation mechanism 60 is provided in the three-dimensional graphics drawing unit 100 to reduce the load on the CPU 10 and improve the drawing performance. It may be realized by the CPU 10 and provided with the three-dimensional drawing mechanism 62 or later.

Further, in the above embodiment, the Z buffer area 34 of the main storage device 18 is shown as one area, but the Z buffer areas are arbitrarily distributed and arranged in the main storage device. It may be.

[0042]

As described above, according to the present invention, the Z used in the three-dimensional drawing mechanism in order to reduce the cost.
Even if the buffer is placed in the main storage device, the main storage device can be accessed directly from the three-dimensional drawing mechanism using the local bus, thereby realizing low-cost and high-speed drawing processing by reducing the drawing memory capacity. can do.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a configuration diagram of an embodiment showing details of FIG. 2;

FIG. 4 is a configuration diagram showing another embodiment of the present invention.

FIG. 5 is an explanatory view of a conventional device.

[Explanation of symbols]

 10: Central processing unit (CPU) 12: Main bus 14: Cache memory 16: Main storage control unit (MCU) 18: Main storage unit (MSU) 20: Three-dimensional drawing mechanism 22, 24, 26: Frame memory 28: Display Control mechanism 30: Color display 32: Local bus 34: Z buffer area (drawing information storage area) 36: Depth control unit 38: Address register 40: Offset address 42: X address 44: Y address 46, 48, 50, 52: Selectors 54, 56: Register 58: Comparator 60: Drawing operation mechanism 62: Three-dimensional drawing mechanism 64: Depth control mechanism 66: Two-dimensional drawing mechanism

Claims (2)

(57) [Claims] [Claim 1] 3 with a Meinba scan you and Rokaruba scan
And Dimension drawing Organization, a central processing equipment supplying the three-dimensional drawing data to the three-dimensional drawing Organization through the Meinba scan, and the central processing instrumentation placed these access by the Meinba scan, the Rokaruba scan in the three-dimensional drawing Organization said three dimensional representation Organization or these access selectively receiving a main storage equipment, in addition to the predetermined realm allocated in advance on the information handled by the central processing equipment by It is composed of a main storage equipment which stores drawing information handled drawing, the three-dimensional drawing mechanism, assigned to the main storage device
Depth information of 3D image for each screen by specifying information storage area
When writing information and synthesizing two-dimensional image information of multiple screens
Then, the depth information of the main storage device is read and compared,
Depth control hand that selects and draws image information located in front
And a depth control unit , wherein the depth control means includes a drawing information allocated to the main storage device.
The offset address that specifies the start position of the
Stored as upper address, specified by 2D display coordinates
X address and Y address indicating the drawing position
Address register for storing the
The main storage is accessed using the storage address of the register.
Three-dimensional graphics drawing apparatus which is characterized in that process. Wherein at the three-dimensional graphics drawing apparatus according to claim 1, the offset address of the address register are set by the central processing equipment initialization program or application program by the central processing equipment to perform the A three-dimensional graphics drawing device characterized by the above-mentioned.