JP2001016041A - Semiconductor device and frequency multiplexing circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device which can remove unwanted frequency components. SOLUTION: This semiconductor device is equipped with an FET 13, having electrodes G, D, and S and a bias circuit connected to the source electrode S of the FET 13. The bias circuit is composed of two capacitors C1 and C2 each having one end grounded, a transmission line 15 which is connected between the other end terminals of the capacitors C1 and C2, and a resistance 16 which is connected between the other end of the capacitor C2 at a side away from the source electrode S and the ground GND.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an MMIC (Microw
ave Monolithic Integrated Circuit).

[0002]

2. Description of the Related Art In recent years, available frequencies have been restricted with the expansion of the communication field. As a result, high-frequency bands such as microwaves and millimeter waves have been used for communication purposes. In a communication device using such a high frequency band, M
The MIC is one of the key components. MM
The IC has a structure in which an active element such as a HEMT, a MESFET, or an HBT, which has good characteristics even at a high frequency, and passive elements such as a transmission line, an MIM capacitor, and a resistor are incorporated in a semiconductor substrate.

[0003] Here, a conventional semiconductor device is referred to as MM.
An example of a multiplier formed by an IC will be described with reference to FIG. Reference numeral IN denotes an input terminal, and the input terminal IN is connected to a matching circuit 42 via an input coupling capacitor 41. The matching circuit 42 is connected to the gate electrode G of the FET 43. A stub 44 forming a gate bias circuit is connected to the gate electrode G of the FET 43. The stub 44 is connected to the ground GN.
The capacitor 45 connected to D and the bias input terminal Bg are connected.

A stub 46 constituting a drain bias circuit is connected to the drain electrode D of the FET 43. The stub 46 is connected to a capacitor 47 for connecting the stub 46 to the ground GND, and a bias input terminal Bd. Further, a stub 48 for suppressing the input wave is connected to the drain electrode D of the FET 43 so that the input wave (frequency f) input from the input terminal IN is not output. The stub 48 is usually formed with a line length of １ ／ of the wavelength (λ) of the input wave. Also, F
The drain electrode D of the ET 43 is connected to the matching circuit 49,
The matching circuit 49 is connected to the output terminal OUT via the output coupling capacitor 50. The matching circuit 49
Matching is performed for twice the frequency (2f) of the input wave.

Since the gate and drain bias circuits appear to have higher impedance than the signal line, the stub 44 and the stub 46 are respectively set to the wavelength of the input wave frequency f or the output wave frequency (2f). On the other hand, it is constituted by a line having a length of about 1/4. Further, the capacitors 45 and 47 are configured by MIM capacitors and the like.

In the above-described semiconductor device, the bias circuit is formed by a stub or a capacitor. Therefore, the area of the bias circuit increases, and the chip area of the entire MMIC increases. In addition, bias voltages having different polarities are applied to the drain electrode and the gate electrode. Therefore, two power supplies are used.

Here, the operating point of the multiplier shown in FIG. 4 will be described with reference to FIG. FIG. 5 shows the I-
The V characteristic is shown. The horizontal axis is the drain voltage Vd, the vertical axis is the drain current Id, and the gate voltage Vg is V1, V2, V
3, V4 (V1>V2>V3> V4). In the case of the multiplier, an area P surrounded by a dotted line is usually used as a bias point. This bias point is determined by FET4
3 is a pinch-off region where the drain voltage is sufficiently high but the flowing current value is small. When the multiplier is operated at such a bias point, there is a problem that the pinch-off voltage changes and the characteristics of the multiplier change greatly if there is a variation in the manufacturing of the FET or a change in temperature. As one of the methods for solving such a problem, there is a method of connecting a resistor to a bias circuit to have a self-bias function.

Here, a configuration in which the bias circuit has a self-bias function will be described with reference to FIG. Source electrode S of FET43
, A resistor R1 and a capacitor Ca are connected in parallel with the ground GND. The gate electrode G of the FET 43 includes:
The resistor R2 is connected to the ground GND. A bias circuit having such a configuration is called a self-bias type,
Often used when the ET threshold is negative.

In the bias circuit having the above-described configuration, even when the gate electrode G is set to the ground potential, the potential Vgs between the gate and the source is Vgs =-(Id * R) (where Id: FE
Drain current flowing through T43, R: resistance value of resistor R1)
Becomes Therefore, if the gate-source voltage during operation is negative, the MMIC can be operated with one power supply by selecting the values of Id and R. The resistance R1
When the power supply voltage fluctuates by connecting
Or, if the characteristics of the active device deviate from the design values,
There is an advantage that feedback is applied and fluctuations in the characteristics of the FET 43 are suppressed.

Note that the resistor R1 only needs to work in the DC region.
In the high frequency region, the signal component is rather attenuated, and the characteristics are degraded. Therefore, the capacitor Ca is connected so that the impedance is sufficiently reduced in the operation region.

In the case where the above-mentioned bias circuit is formed by an MMIC, the resistor is usually composed of a thin-film resistor.
The capacitor is composed of an MIM capacitor.

[0012]

A conventional semiconductor device is:
For example, when a multiplier is configured, a harmonic component generated in a preceding circuit may be amplified and output. For example,
As shown in FIG. 7, a case of a multiplier circuit in which two-stage multipliers 71 and 72 are connected in cascade and the frequency of an input signal input from an input terminal IN is multiplied by 4 will be described. Here, assuming that the frequency of the input signal input to the multiplier 71 at the preceding stage is f, the third harmonic (3 × f) of the unnecessary wave is output from the multiplier 71 in addition to the second harmonic (2f) of the input signal. ) Component is output,
It is input to the multiplier 72 at the subsequent stage. Therefore, in addition to the desired frequency (4 × f), an unnecessary frequency such as a triple frequency (3 × f) is output from the multiplier 72 at the subsequent stage, and output to the output terminal OUT. The unnecessary frequency adversely affects the operation of a circuit connected to the subsequent stage of the frequency multiplier.
However, with the above-described configuration, it is difficult to remove such unnecessary frequency components.

An object of the present invention is to provide a semiconductor device which can solve the above-mentioned drawbacks and can remove unnecessary frequency components.

[0014]

According to the present invention, there is provided a semiconductor device comprising: an active element having a plurality of electrodes; and a bias circuit for applying a bias voltage to one electrode of the active element. Two capacitors having one end grounded, a transmission line connected between the other ends of the two capacitors, and a resistor connected between the other end of the capacitor located farther from the one electrode and the ground; It is composed of

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. Symbol IN indicates an input terminal, and input terminal I
N is connected to a matching circuit 12 via an input coupling capacitor 11. The matching circuit 12 is connected to the gate electrode G of the FET 13. The resistor 14 is connected between the gate electrode G of the FET 13 and the ground GND. One end of the source electrode S of the FET 13 is ground GND.
And the transmission line 1 connected to the other ends of the capacitors C1 and C2.
5, and the capacitor C2 far from the source electrode S
And a self-bias circuit composed of a resistor 16 connected between the ground GND. Note that the resistor 16 is
Usually, it is composed of a semiconductor resistor or a thin film resistor.

Also, the drain electrode D of the FET 13
A stub 17 constituting a bias circuit for the drain and a capacitor C3 for grounding the stub 17 are connected. A bias terminal Bd is connected to a connection point between the stub 17 and the capacitor C3. Further, the drain electrode D is connected to a matching circuit 18, and the matching circuit 18 is connected to an output terminal OU via an output coupling capacitor 19.
Connected to T. Further, a stub 20 for suppressing the input wave is connected between the drain electrode D and the matching circuit 18 so that the input wave (frequency f) is not output. The stub 20 is formed, for example, with a line length of １ ／ of the wavelength (λ) of the input wave.

Here, the characteristics of the circuit connected to the source electrode S of the FET 13 will be described with reference to FIG. In FIG. 2, the portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted. When the capacitances of the capacitors C1 and C2 and the length of the transmission line 15 are selected to be certain values, the frequency characteristics of the impedance viewed from the source electrode S in the arrow Y direction in FIG. 2 are as shown in FIG. FIG. 3A shows the absolute value of the impedance. The horizontal axis represents the frequency (f), and the vertical axis represents the absolute value of the impedance (Z). FIG. 3B shows a locus in the Smith chart. As shown in FIG. 3, the absolute value of the impedance is twice the specific frequency (2 ×
f), and becomes almost zero at twice the frequency (4 × f). In addition, a filter that increases at the triple frequency (3 × f) and suppresses the triple frequency (3 × f) is configured.

Therefore, the source electrode of the FET 13
A multiplier connected to the bias circuit shown in FIG.
The multiplier having such a configuration is applied as, for example, a subsequent multiplier of a frequency multiplier in which multipliers are connected in cascade in two stages. In this case, in the subsequent multiplier, the bias circuit looks like a resistor at the triple frequency (3 × f). for that reason,
F at 3 times frequency compared to 2 times or 4 times frequency
The gain of the ET 13 decreases, and unnecessary wave components are suppressed.
Further, since the gate bias circuit is constituted by resistors, the chip area of the MMIC can be reduced.

In the above embodiment, the case of the multiplier has been described. However, according to the configuration described above, a characteristic of suppressing a specific frequency, for example, a difference frequency between an input signal and a local oscillation signal can be obtained. Therefore, if the FET is used in a mixer that mixes the input signal and the local oscillation signal,
If a feedback circuit is connected to the source electrode, the image frequency generated by the mixer can be suppressed.

In the above-described embodiment, the case where the active element used for the MMIC is the FET is described. However, the present invention can be applied not only to FETs but also to, for example, bipolar transistors.

[0021]

According to the present invention, a semiconductor device having a self-bias circuit and capable of suppressing harmonic components of an input signal can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram for explaining an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining a bias circuit used in the present invention.

FIG. 3 is a characteristic diagram for explaining characteristics of the present invention.

FIG. 4 is a circuit configuration diagram for explaining a conventional example.

FIG. 5 is a characteristic diagram for explaining characteristics of a conventional example.

FIG. 6 is a circuit diagram illustrating a conventional bias circuit.

FIG. 7 is a circuit configuration diagram for explaining a multiplication circuit configured by cascade-connecting conventional multipliers.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Input coupling capacitor 12 ... Matching circuit 13 ... FET 14 ... Resistor 15 ... Transmission line 16 ... Resistor 17 ... Stub 18 ... Matching circuit 19 ... Output coupling capacitor 20 ... Stub C1, C2, C3 ... Capacitor IN ... Input terminal OUT… Output terminal

Claims (3)

[Claims] 1. A semiconductor device comprising: an active element having a plurality of electrodes; and a bias circuit for applying a bias voltage to one electrode of the active element, wherein the bias circuit includes two capacitors each having one end grounded. And a transmission line connected between the other ends of the two capacitors;
A semiconductor device comprising: a resistor connected between the other end of a capacitor located far from one of the electrodes and ground; 2. A frequency multiplier comprising the semiconductor device according to claim 1. 3. A frequency multiplier in which a plurality of frequency multipliers are connected in cascade in a frequency multiplier, wherein the frequency multiplier configured by using the semiconductor device according to claim 1 is connected to a second or subsequent one of the plurality of stages. circuit.