JP2001010100A - Double power-type thermal head - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film type thermal head having a heating means that generates different energies even when an identical power source is used by an identical heating body. SOLUTION: This thermal head comprises a thin film resistor layer 102 wherein a heating resistor section 102-1 formed on a glaze layer 101 partially provided on an insulation substrate 100 and an additional resistor section 102-2 formed on the insulation substrate 100 are integrally formed. The thermal head further comprises a first electrode connection section 104-1 which is provided on the thin film resistor layer 102 to be connected to a first switching means and a second electrode connection section 104-2 which is provided on the thin film resistor layer 102 to be connected to a second switching means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal head for two-color printing which can output different heating temperatures during the same scanning and is suitable for, for example, a heat-sensitive element which develops different colors depending on the heating temperature. The present invention relates to a print head that can optimize print quality by making a difference between high and low energy generated in a heating head when used as a high-temperature thermal head and when used as a low-temperature thermal head.

[0002]

When printing with respect to the thermal paper by the Related Art Thermal head, conventionally, as shown in FIG. 9 (A), printing energy (temperature) and T ₀ from as high as the print temperature constant, such as for example, black color When the energy is lower than that, the print density becomes lighter, so that the portion not desired to be printed does not heat the thermal head. That is, only the operation control of printing or not printing is performed based on the presence or absence of data on one line.

In order to perform this control, there is a type in which a hysteresis control circuit is added to limit a rise in temperature due to heat storage of the thermal head substrate. However, when printing, the thermal head is set to a single temperature, that is, a single energy. Control was the goal.

In recent years, a multi-color thermal paper has been manufactured in which, for example, printing is performed in black when printing with a high-temperature thermal head, and printed in red, for example, when printing with a low-temperature thermal head. For example, it is provided as product name MB-23 of Oji Paper Co., Ltd.

Namely, the heat-sensitive paper of this kind, as shown in FIG. 9 (B), when the thermal head of the printing energy (temperature) is T _2, and color, for example red, printing energy is T ₁
When (T ₂ <T ₁ ), the color develops black. Note whitening phenomenon appears when still higher than T _1. In addition to this type of heat-sensitive paper, not only a combination of red and black, but also a combination of other colors based on low / high printing energy exists.

[0006] Using such a multi-color thermal paper, when performing multi-color printing, for example, as shown in FIG. 10 (A), when performing red and black print on the scanning line L _0, the thermal head in the conventional , for example first data is transferred via the current amount corresponding to the low temperature of the print data portions for red, then it is necessary to perform a data transfer by a current amount corresponding to the high temperature on the same scanning line L ₀ again Was.

Also, as shown in FIG.
Scan line L even when printing₁, L _Two...
Also, the print data in the red part is
Data transfer is performed according to the amount, and then the same scan line L₁,
L_Two... Data transfer based on the amount of current corresponding to high temperature
Had been sent.

In order to cope with two types of energy, data transfer is performed twice in one line, and each energy is set. Therefore, there is a problem that the printing speed is slow because two data transfers are required for one line.

In order to solve this, the present inventor has previously described in Japanese Patent Application Nos. 9-302728 and 10-12320.
We have proposed a thermal head that can do this in a single scan even when different energy settings are set in the line.

[0010]

In the above-mentioned conventional thermal head, the setting of the large and small printing energy is determined by keeping the amount of heat generated per unit time of the thermal head constant and by the magnitude of the heat generation time. That is, assuming that the heat value per unit time is W, the resistance of the thermal head is r ₀ , and the applied voltage is V, the heat value W of the thermal head per unit time is determined by W = V ² / r. When the thermal head is used in the high energy state, the thermal head generates heat only for the time t ₂ , that is, W × t _2. When the thermal head is used in the low energy state, the thermal head is heated for the time t ₁ (t ₂ > t ₁ ). That is, heat was generated by W × t ₁ .

That is, in a thermal head in which the above-mentioned different energy settings can be set in one scan based on the magnitude of a strobe signal, which will be described later, the magnitude of the printing energy is determined by setting the heat generation amount per unit time to be the same. The setting is made only by the magnitude of the heating time of the head heater.

Therefore, even if the heating time is shortened in order to reduce the printing energy, the amount of heat generated per unit time is the same as in the case of the high energy state. Exists. Also, by giving a lower energy heat than the thermal head,
When used on rewritable paper for erasing characters and the like printed in a high energy state, there are cases where characters cannot be sufficiently erased due to short time.

[0013] Therefore, an object of the present invention is to connect an additional resistor in series with the heating resistor so that only the heating resistor is energized when used in a high energy state, and is used when used in a low energy state. An object of the present invention is to provide a thin-film two-power type thermal head in which an additional resistor is energized in series with a heating resistor. That is, an object of the present invention is to provide a thin-film thermal head capable of giving different energy even when the same heating element and the same power supply are used.

[0014]

FIG. 1 shows a schematic configuration of the present invention.
This will be described below. In FIG. 1, 100 is an insulating substrate such as alumina, 101 is a glaze layer, 102 is a boron-doped polysilicon layer, 102-1 is a heating element layer, 102-2.
Is an additional resistance portion, 103 is a common electrode layer, 104 is a conductive line,
104-1 is a first electrode connection portion, 104-2 is a second electrode connection portion, 105 is a protective layer, and 106 is a heating portion.

In the high energy state, the first switching means connected to the first electrode connecting portion 104-1 is turned on, and the heating of the heating element layer 102-1 is controlled. In the low energy state, the second switching means connected to the second electrode connection 104-2 is turned on, and the heating element layer 1
Heat generation of the heating element layer 102-1 is controlled in a state where the heating element layer 102-1 is connected in series with the additional resistance section 102-2. At this time, heat generated in the additional resistance section 102-2 is radiated through the insulating substrate 100.

The above object of the present invention can be achieved by the following constitutions.

(1) Heating resistor 102 formed on glaze layer 101 partially provided on insulating substrate 100
-1 and the additional resistance portion 10 formed on the insulating substrate 100
2-2, a thin-film resistance layer 102 integrally formed, a first electrode connection portion 104-1 provided on the thin-film resistance layer 102 and connected to a first switching means, and provided on the thin-film resistance layer 102 And a second electrode connecting portion 104-2 connected to the second switching means.

(2) Heating resistor portion 102 formed on glaze layer 101 partially provided on insulating substrate 100
-1 and the additional resistance portion 10 formed on the insulating substrate 100
2-2, a first electrode connecting portion 104-1 provided on the thin-film resistance layer 102 and connected to a first switching means, and the thin-film resistance layer 1
02, a second electrode connecting portion 104-2 connected to a second switching means, and a first strobe signal input means for controlling the heating resistance of the first switching means with the first energy. And second strobe signal input means for controlling the heat generation of the heating resistor by the second energy with respect to the second switching means, and based on the input of the second strobe signal, And the additional resistance section are connected in series and energized, and the unit heat value of the heating resistance section is equal to the first heat generation amount.
It is characterized in that it is smaller than a unit heat generation amount generated by the heat generation resistor section based on the input of the strobe signal.

Thus, the following effects can be obtained.

(1) A thin-film resistor in which a heating resistor and an additional resistor are integrally formed is formed on an insulating substrate, and a glaze layer is formed below the heating resistor.
The heat generated by the heat generating resistor portion is stored by the glaze layer, so that the heat treatment of the thermal paper can be performed accurately, and the heat generated by the additional resistor can be radiated well through the insulating substrate on which the glaze layer is not formed. So you can
Even if the heating resistor and the additional resistor are integrally formed, it is possible to suppress the adverse effect caused by the heat generated by the additional resistor.

(2) Since the heating resistor and the additional resistor are energized in a state of being connected in series based on the input of the second strobe signal, the unit heating value of the heating resistor can be reduced by only the heating resistor. It can be made smaller than the unit heat value of the high energy state that is energized independently. For this reason, it is possible to provide a two-power type thermal head suitable for thermal paper whose characteristics in the low energy state require a small amount of heat generation.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view of a heat-generating portion of a two-power thermal head showing an embodiment of the present invention, and FIG. 2 is a heat-generating portion and a driving IC of a two-power thermal head of the present invention.
FIG. 3 is a comparison diagram of heat generation energy between the conventional example and the present invention, FIG. 4 is a control circuit per dot of the thermal head according to the present invention, FIG. 5 is a control signal explanatory diagram thereof, and FIG. FIG. 3 is a circuit configuration diagram of a two-power type thermal head using the thermal head of the present invention.

As shown in FIG. 1, the thermal head of the present invention comprises a glaze layer 10 on an insulating substrate 100 such as alumina.
Form one. The glaze layer 101 is formed on the insulating substrate 100
Is partially formed at a position of a heat generating portion 106 described later.

On the insulating substrate 100 and the glaze layer 101, a boron-doped polysilicon layer 102 is formed. At one end of the polysilicon layer 102,
For example, an aluminum common electrode layer 103 is provided. Then, the heating resistance section 102-1 is separated, and a conductive line 104 made of, for example, aluminum is provided. The conductive line 104 is provided for each print dot of the thermal head.

The left end of the conductive wire 104 becomes a first electrode connection 104-1 described later.
A second electrode connecting portion 104-2 described later, which is constituted by the conductive line 104 and separated from the polysilicon layer functioning as the additional resistance portion 102-2, is provided from 04-1.

As shown in FIG. 1, a protective layer 105 made of, for example, SiBP is formed on the polysilicon layer 102, the common electrode layer 103, and the conductive lines 104. The heating resistor section 102-1 and the protective layer on the heating resistor section 102-1 constitute a heating section 106 for heating the thermal paper.

The insulating substrate 100 on which the glaze layer 101, the polysilicon layer 102, the common electrode layer 103, the conductive lines 104, the protective layer 105 and the like are formed is placed on a supporting aluminum plate 107 as shown in FIG. Deploy. An interface board 108 is separately arranged on the supporting aluminum plate 107, and a driving IC 109 is mounted on the interface board 108. This driving IC 109
A control circuit including FET1 and FET2, which are switching means as shown in FIG.

The first electrode connecting portion 104-1 and the second electrode connecting portion 104-2 are connected to the first electrode connecting wire 110 and the second electrode connecting portion 104-2.
A driving IC 109 is connected to each of the electrode connecting wires 111.
The driving IC 109 is connected to the external connection wire 1.
The connection circuit 12 is connected to an external circuit such as a shift register shown in FIG.

In FIG. 1, a heating portion 102-of the polysilicon layer 102 between the common electrode layer 103 and the conductive line 104 is formed.
1 of the resistance value and r _0, when the first electrode connecting portions 104-1 the resistance value of the additional resistor unit 102-2 of the polysilicon layer 102 between the second electrode connecting portions 104-2 and the r _1, the The terminal voltage V is applied between the one electrode connecting portion 104-1 and the common electrode 103.
The heating power W ₀ in the heating resistor section 102-1 when the voltage is applied is given by the following equation (1) from the circuit of FIG.

W ₀ = V ² / r ₀ (1) Further, the heat generation power W in the heat generation resistor section 102-1 when the terminal voltage V is applied between the second electrode connection section 104-2 and the common electrode 103. heating power W ₂ in ₁ and the additional resistor unit 102-2, from the circuit of FIG. 3 (C), the following equation (2),
Equation (3) is obtained.

W ₁ = (V × r ₀ / (r ₀ + r ₁ )) ² / r ₀ (2) W ₂ = (V × r ₁ / (r ₀ + r ₁ )) ² / r _1.・ ・ (3) The proposal in Japanese Patent Application No. Hei 10-12320 is shown in FIG.
As shown in (A), the power W ₀ applied to the thermal paper per unit time from the heat generation resistance is the same in both the high energy state and the low energy state. In the case of the high energy state, the heat generation time t ₂ is represented by: By setting the heating time to be longer than the heat generation time t _{1 in} the low energy state, the applied energy to the thermal paper in the high energy state becomes W ₀ × t ₂ , and the applied energy W ₀ × t in the low energy state
_{It is} larger than ₁ by the difference in heat generation time t ₂ −t ₁ .

On the other hand, in the present invention, as shown in FIG.
Apply heat to the thermal paper in unit time
Power in the high energy state is W₀But low energy
W for ruggy state₁And W₀Lower than. did
Therefore, as shown in FIG.
t_TwoApplying to thermal paper in high energy state
Energy is W₀× t_TwoIn a low energy state
Applied energy W ₁× t_TwoLarger than. this
By adjusting the unit heating value in the heating resistor
Lower energy state. FIG. 3
In the case of (B), the heat generation time in the high energy state and
When the heat generation time in the low energy state is the same,
However, it is not necessary that they be the same.
Both can be appropriately set depending on the properties of the paper.

Further, according to the present invention, when operated in the low energy state, the heat generated by the above equation (3) is generated by the additional resistance unit 1.
However, the heat generated by the thermal head can be reduced as much as possible by providing the additional resistance portion 102-2 in a portion having no glaze layer.

Control of the thermal head of the present invention shown in FIG.
The circuit will be described with reference to FIGS. Fig. 4 (A) smell
1, 2 are FETs, 3, 4, 5 are multi-input AND circuits,
6 is an AND circuit, 7 to 10 are NAND circuits, 11 and 12 are
EOR (exclusive sheave) circuit, 13 is output protection
Circuits, 14 to 18 are inverters, 19 and 20 are NAND times
Road, 21 is an EOR circuit, 22 to 24 are inverters, 3
0 and 31 are diodes, r ₀Is the heating resistance, r₁Is an additional resistor
It is anti. These circuits correspond to the drive I shown in FIG.
C109.

FETs 1 and 2 are switching circuits,
FET1 is connected to the first electrode connection 104-1 shown in FIG. 1, and FET2 is connected to the second electrode connection 104-2.

When the IC constituting the thermal head is operating normally, the output protection circuit 13 operates when the multi-input AND circuits 3, 4
Is output as "1".

The signals indicating the presence / absence of the print dots Q1, Q2, Q3, LQ2, and RQ2 in the high energy portion shown in FIG. 4B are the signals Q1, Q2, Q3, and Q3 shown in FIG.
Signals that are input as LQ2 and RQ2 and that indicate the presence or absence of the print dots q1, q2, and q3 in the low-energy portion shown in FIG. 4C are input as signals q1, q2, and q3 that are shown in FIG. .

Then, the strobe signal STROBE1
Is for heating the thermal head as a high energy portion to print black on paper, and the strobe signal STROBE2 is for heating the thermal head as a low energy portion and printing red, for example, on paper. .

When printing the corresponding print Q1 shown in FIG. 4B, if there is no print data in Q2, Q3, LQ2, and RQ2, these are "0", and the NAND circuits 7-1
Since 0 outputs “1”, both the multi-input AND circuit 5 and the multi-input AND circuit 3 output “1”,
FET1 is thereby turned on for a time T ₁ as defined by the strobe signal STROBE1, for heating the heating resistor r ₀ of the thermal head. Here, the heating resistor r ₀ corresponds to the heating resistor section 102-1 in FIG.

However, if there is print data in at least one of Q2, Q3, LQ2, and RQ2, the gate signals A1,
B1, A2, only being controlled time based on B2 output time of multi-input AND "1" of the the circuit 5 is output is "0" strobe signal STROBE1 by multi-input AND circuit 3 is shorter than the T ₁ And the energy of the heat generating portion including the heat generating resistance r ₀ of the thermal head in the strobe signal STROBE1 is controlled to be equal.

When printing the corresponding print q1 shown in FIG. 4C, if there is no print data in q2 and q3, these are "0", and both the NAND circuits 19 and 20 output "1". Therefore, the AND circuit 6 and the multi-input AND circuit 4 both output "1", and the FET 2 thereby operates for the time T determined by the strobe signal STROBE2.
₂ only FET2 turn on, turn the heating resistor r ₀ and an additional resistor r ₁ is the heat generating resistor r ₀ in the heat generating portion of the thermal head in a state of being connected in series to generate heat. Where the additional resistance r
₁ corresponds to the additional resistance unit 102-2 in FIG.

However, if there is print data in at least one of q2 and q3, the AND circuit 6 is controlled for a time controlled based on the gate signals C1 and C2 corresponding to the print data in consideration of the heat storage effect, as described later. output time of the "1" in the multi-input aND circuit 4 according to the strobe signal STROBE2 "0" is output is controlled to be shorter than the T ₂ from the energy of the heat generating portion of the thermal head in the strobe signal STROBE2 Control to be equal.

The various control signals shown in FIG. 5 are output from a control signal output circuit (not shown) and are output at the same period S.

The control signals shown in FIG. 5A are various control signals for controlling the thermal head in a high energy state, and the control signals shown in FIG. 5B are for controlling the thermal head in a low energy state. Are various control signals.

[0045] STROBE1 signal, the printing control range shown in FIG. 4 (B), when printing only the appropriate print dot Q1 dot is present, a thermal head connected thereto to turn on period T ₁ only FET1 is intended to heating control only for the period T _1, as shown in FIG. 5 (a), only for the period T ₁ is at a low level.

[0046] GATE A1 signal, falls at the same time as the STROBE1 signal, in which rises after a period t _1.

The GATE A2 signal falls at the same time as the STROBE1 signal and rises after a period (t ₁ + t ₂ ).

The GATE B1 signal is a STROBE1 signal.
Period (t₁+ T _Two+ T_Three+ T_Four)rear
And then the period t_FiveLater, STROBE1
It rises simultaneously with the issue.

The GATE B2 signal is a STROBE1 signal.
Period (t₁+ T _Two+ T_Three) Fall after
And then the period (t_Four+ T_Five) Later, STROBE
It rises at the same time as one signal.

[0050] Further STROBE2 signal, the printing control range shown in FIG. 4 (C), if there is a printed dot only the appropriate print dot q1, thermal head connected thereto turns on the period T ₂ by FET1 For period T ₂
(T ₂ <T ₁ ).
As (B), the falls simultaneously with STROBE1 signal only during the period T ₂ is at a low level.

[0051] GATE C1 signal, falls at the same time as the STROBE2 signal, in which rises after a period t _6.

The GATE C2 signal falls at the same time as the STROBE2 signal, and rises after a period (t ₆ + t ₇ ).

These T ₁ , T ₂ , t _{1 to} t ₈ are:
It can be set appropriately according to the characteristics of the paper.

First, based on FIGS. 4 and 5, with regard to the heat history control, the print control range shown in FIGS. 4B and 4C will be described.
That is, the printing dots Q1 to Q
3, there is print data for LQ2 and RQ2 as follows, and for low energy parts, print dots q1 to
Regarding q3, a case where print data exists as described below will be described.

Here, when Q1 is the corresponding print dot,
Q2 indicates a print dot immediately before the one line, and Q3 indicates a print dot immediately before the two lines. LQ2 indicates the left print dot one line before, and RQ2 indicates the right print dot one line before.

When q1 is the corresponding print dot,
q2 indicates a print dot immediately before the one line, and q3 indicates 2
Indicates the print dot immediately before the line.

(1) When print data exists only in the print dot Q1, in the print control range shown in FIG. 4B, print data exists only in the print dot Q1.
When print data does not exist in 2, Q3, LQ2, and RQ2, in FIG. 4A, Q1 = "1", Q2 = "0", and Q3
= "0", LQ2 = "0", RQ2 = "0".

Since the NAND circuits 7 to 10 output "1" in response to these "0", the multi-input AND circuit 5 outputs "1". At this time, if the thermal head is normal, “1” is output from the output protection circuit 13 and Q1 = “1”, and the inverter 14 receives the signal shown in FIG.
Since the STROBE1 signal as shown in FIG.
“1” is output from the multi-input AND circuit 3 only during a period T ₁ shown in FIG. At this time, since q1 = “0”, the multi-input AND circuit 4 outputs “0”.

As described above, since "1" output from the multi-input AND circuit 3 is input to the FET 1 via the OR circuit 2, the OR circuit 2 eventually has print data in Q1, Q2, Q3, LQ2, if no RQ2 the print data, which is turned on by applying only the period T ₁ to "1" to the FET1, to heat generation control only for the period T ₁ the heating resistor r ₀ of the thermal head connected to FET1 .

(2) When print data exists in the print dots Q1 and Q2, and when print data exists in the print dot Q1 and the print dot Q2 one line before the print data, FIG.
In (A), “1” is applied to each of Q1 and Q2,
3 = “0”, LQ2 = “0”, and RQ2 = “0” are applied. As a result, the NAND circuits 8 to 10 each become “1”.
Is output.

At this time, the NAND circuit 7 includes the inverter 1
5, the inversion of the GATE A1 signal shown in FIG.
Since the signal and Q2 = "1" are applied, the period in FIG.
Interval t ₁The NAND circuit 7 outputs "0" only during
"1" is output. Therefore, the multi-input AND circuit 5 is configured as shown in FIG.
Period T shown in₁To period t₁After subtracting (t_Two
+ T_Three+ T_Four+ T_Five) Outputs “1” and FET1
Is turned on only during the period of
Heating resistance of head r₀To (T₁-T₁) Heating only for a period
I will.

(3) When print data exists in the print dots Q1 and LQ2, and when print data exists in the print dot L1 adjacent to the print dot Q1 and the left adjacent print dot LQ2 in FIG.
"1" is applied to each of Q1 and LQ2 of (A),
2 = “0”, Q3 = “0”, and RQ2 = “0” are applied. As a result, the NAND circuit 7 and the NAND circuits 9 and 10 each output "1".

At this time, LQ2 =
“1” and the output of the EOR circuit 11 are input. EO
The inverted signal of the GATE A1 signal shown in FIG.
At night, since the inverted signal of GATE A2 signal shown in FIG. 5 (A) is applied only during the period t ₂ shown in FIG. 5 EOR
The circuit 11 outputs “1”, and outputs “0” in other periods. Therefore the NAND circuit 8 outputs only period t ₂ "0", other periods outputs "1".

Therefore, the multi-input AND circuit 3 is shown in FIG.
Period T₁To period t_TwoAfter subtracting (t₁+ T_Three
+ T_Four+ T_Five) Outputs “1”, and FET1
Only the thermal head connected to FET1
Heating resistance r₀To (T₁-T _Two) Heat generation control only for a period
You.

(4) When print data exists in the print dots Q1 and RQ2, and when print data exists in the corresponding print dot Q1 and the immediately adjacent print dot RQ2 in FIG.
“A” is applied to each of Q1 and RQ2 in FIG.
2 = “0”, Q3 = “0”, LQ2 = “0” are applied. Thereby, the NAND circuits 7 to 9 each output "1".

At this time, RQ2 =
“1” and the output of the EOR circuit 12 are input. EO
The R circuit 12 outputs an inverted signal of the GATE B1 signal shown in FIG.
5A is applied, the EOR circuit 12 outputs “1” only during the period t ₄ shown in FIG. 2 and outputs “0” during the other periods. .
Therefore the NAND circuit 10 outputs only the period t ₄ "0", other periods outputs "1".

Therefore, the multi-input AND circuit 3 is shown in FIG.
Period T₁To period t_FourAfter subtracting (t₁+ T_Two
+ T_Three+ T_Five) Outputs “1”, and FET1
Only the thermal head connected to FET1
Heating resistance r₀To (T₁-T _Four) Heat generation control only for a period
You.

(5) When print data exists in the print dots Q1 and Q3, and when print data exists in the print dot Q1 and the print dot Q3 two dots before the print data, FIG.
“1” is applied to each of Q1 and Q3 in FIG.
= “0”, LQ2 = “0”, and RQ2 = “0”. Thus, the NAND circuits 7, 8 and 10 each output "1".

At this time, Q3 = “1” is applied to the NAND circuit 9.
And GATE shown in FIG.
 Since an inverted signal of the B1 signal is applied, it is shown in FIG.
Period t _FiveOnly the NAND circuit 9 outputs "0" and the other period
Outputs “1”.

Therefore, the multi-input AND circuit 3 is shown in FIG.
Period T₁To period t_FiveAfter subtracting (t₁+ T_Two
+ T_Three+ T_Four) Outputs “1”, and FET1
Only the thermal head connected to FET1
Heating resistance r₀To (T₁-T _Five) Heat generation control only for a period
You.

(6) When print data exists in the print dots Q1, Q2, and Q3, and when print data exists in the print dot Q1, the print dot Q2 one dot before the print dot Q2, and the print dot Q3 two dots before the print dot Q1 , Q in FIG.
“1” is applied to each of 1, Q2, and Q3, and LQ2 =
“0” and RQ2 = “0” are applied. As a result, the NAND circuits 8 and 10 each output "1".

At this time, Q2 = “1” is applied to the NAND circuit 7.
And GATE shown in FIG.
A1 Since the signal inverting signal and is applied, the NAND circuit 7 only during the period t ₁ in FIG. 5 outputs "0", other periods outputs "1". The NAND circuit 9 has Q3
= "1", according to the inverter 17, since the inverted signal of GATE B1 signals shown in FIG. 5 (A) is applied, the NAND circuit 9 only for the period t ₅ shown in FIG. 5 outputs "0",
In other periods, “1” is output.

Therefore, the multi-input AND circuit 3 outputs the remaining period (t) obtained by subtracting the periods t ₁ and t ₅ from the period T ₁ shown in FIG.
₂ + t ₃ + t ₄ ) outputs “1”, FET 1 is also turned on only during this period, and the heating resistance r ₀ of the thermal head connected to FET _{1 is} controlled to generate heat for (T ₁ −t ₁ −t ₅ ). .

(7) Print dots Q1, Q2, Q3, L
When print data exists in a plurality of print dots among Q2 and RQ3, the corresponding print dot Q1 and print dot Q
A plurality of print dots among 2, Q3, LQ2, RQ2,
For example, when print data exists in Q2 and LQ2,
Since 3 = “0” and RQ2 = “0”, the NAND circuits 9 and 10
Output "1".

At this time, as shown in the above (2), the NAND circuit 7 uses the inverter 15 to generate the G signal shown in FIG.
Since ATE A1 signal and Q2 = "1" is applied, the NAND circuit only during the period t ₁ in FIG. 5 7 outputs "0".

As shown in the above (3), LQ2 = "1" and the output of the EOR circuit 11 are input to the NAND circuit 8. Since the inverted signal of the GATE A1 signal shown in FIG. 5A by the inverter 15 and the inverted signal of the GATE A2 signal shown in FIG. 5A by the inverter 16 are applied to the EOR circuit 11, FIG. The EOR circuit 11 outputs “1” only for the period t ₂ shown in FIG.
Is output. For this reason, the NAND circuit 8 outputs only the period t ₂ "0".

Therefore, when print data exists in Q2 and LQ2, when data exists in the corresponding print dot Q1 and print dot Q2, the period t ₁ during which the multi-input AND circuit 5 outputs “0”, and the corresponding print dot Q1 outputs (t ₁ + t ₂₎ only multi-input aND circuit 5 is "0" in the sum of the time period t ₂ to the multi-input aND circuit 5 outputs "0" when the data in the print dots LQ2 is present and, FET1 the heating resistor r ₀ of the connected thermal head by (T ₁ -t ₁ -t ₂₎ for controlling heat generation to.

That is, when print data is present in the print dot Q1 and a plurality of print dots among the print dots Q2, Q3, LQ2, and RQ2, the print dot Q1 and other print dots Q2, Q3, LQ2, RQ2 When there is data in the print dot of the multi-input AND circuit 5, the multi-input AND circuit 5 is operated by the sum of the periods of “0” described in the above (2) to (5) according to the other print dots. outputs "0", the period F which is obtained by subtracting from only T ₁ period of the sum of these
The heating resistor r ₀ of the thermal head connected to ET1 generates heat.

For example, Q1, Q2, Q3, LQ2, RQ
When all of the 2 printing data is present, T ₁ - (t ₁
The multi-input AND circuit 5 outputs “1” only during the period of (t ₂ + t ₄ + t ₅ ) = t ₃ , and heats the heating resistor r ₀ of the thermal head connected to the FET 1 during this period t ₃ .

(8) When print data exists only in print dot q1, in the print control range shown in FIG. 4C, print data exists only in print dot q1 and q
If print data does not exist in q2 and q3, q1 = "1", q2 = "0", and q3 = "0" in FIG. 4A.

Accordingly, since "1" is output to the NAND circuits 19 and 20 by q2 = "0" and q3 = "0", the multi-input AND circuit 6 outputs "1". At this time, if the thermal head is normal, "1" is output from the output protection circuit 13. At this time q1 = a "1", since STROBE2 signal such shown in FIG. 5 (B) to the inverter 22 is transferred, "1" from the period T ₂ by multi-input AND circuit 4 shown in FIG. 5 (B) Is output. Then Q
Since 1 = “0”, the multi-input AND circuit 3 outputs “0”.

As described above, since “1” output from the multi-input AND circuit 4 is input to the FET 2, F 1
ET2, there is print data to q1, q2, q3 when no print data, period T ₂ by a "1" is applied to the FET2 is turned on this, the heating resistor r ₀ of the thermal head connected to the FET2 additional resistor r ₁ is the heat generating resistor r ₀ in a state of being connected in series are heat controlling only the period T ₂ and.

(9) When print data exists in the print dots q1 and q2, and when print data exists in the print dot q1 and the print dot q2 one line before the print data, FIG.
In (A), “1” is applied to q1 and q2, respectively, and q
3 = “0” is applied. Thereby, the NAND circuit 20 outputs “1”.

[0084] The NAND circuit 19 at this time, the inverter 23, since FIG. 5 inverted signal and q2 = "1" of the GATE C1 signal shown in (B) is applied, NAND only during the period t ₆ in FIG. 5 The circuit 19 outputs "0", and the other outputs "1". Thus the AND circuit 6, the remaining time obtained by subtracting the time t ₆ from the period T ₂ shown in FIG. 5 (t ₇ + t
₈₎ outputs "1", since the multi-input AND circuit 4 and an OR circuit 2 outputs only "1" during this period (t ₇ + t _8), FET2 becomes ON only during this period, connected to the FET2 Heating resistance r ₀ and additional resistance r _{1 of} thermal head
Are connected in series and the heating resistance r ₀ is (T ₂ −t ₆ )
Heat generation is controlled only during the period.

(10) When print data exists at the print dots q1 and q3, and when print data exists at the print dot q1 and the print dot q3 two dots before the print data, FIG.
In (A), “1” is applied to q1 and q3, respectively, and q2
= “0” is applied. Thus, the NAND circuit 19 outputs “1”.

At this time, in the NAND circuit 20, q3 =
“1” and the output of the EOR circuit 21 are input. EO
The inverted signal of the GATE C1 signal shown in FIG.
According to, since the inverted signal of GATE C2 signal shown in FIG. 5 (B) is applied, "1" of the two signals, the period t ₇ only EOR circuit 21 shown in FIG. 5 does not match the "0""1"
And outputs “0” in other periods. Therefore the NAND circuit 20 outputs "0" only for the period t _7, other periods outputs "1".

Therefore, the AND circuit 6 operates in the period T shown in FIG.
_The remaining period (t ₆ + t ₈ ) obtained by subtracting the period t ₇ from ₂ outputs “1”, and the multi-input AND circuit 4 and the OR circuit 2 output “1” only during this period (t ₆ + t ₈ ). So F
ET2 becomes ON only this period, the heating resistor r ₀ and an additional resistance r ₁ of the connected thermal head is only heat controlling heat generation resistor r ₀ in a state of being connected in series (T ₂ -t ₇₎ period FET2 .

(11) When print data exists in the print dots q1, q2, q3, the print data is stored in the print dot q1, the print dot q2 immediately before the print dot q2, and the print dot q3 immediately before the print dot q3. When present, FIG.
“1” is applied to q1, q2, and q3 of (A).

At this time, as shown in the above (9), the inverted signal of the GATE C1 signal shown in FIG. 5B and q2 = "1" are applied to the AND circuit 19 by the inverter 23. The NAND circuit 19 outputs “0” only during the period t ₆ in FIG.

As shown in the above (10), q3 = “1” and the output of the EOR circuit 21 are input to the NAND circuit 20. At this time, the inverted signal of the GATE C1 signal shown in FIG. 5B by the inverter 23 and the inverted signal of the GATE C2 signal shown in FIG. 5B by the inverter 24 are applied to the EOR circuit 21. 5, the period t ₇ shown in FIG. 5 where “1” and “0” of both signals do not match.
Only, the EOR circuit 21 outputs “1”, and outputs “0” in other periods. Therefore, the NAND circuit 20 operates in the period t ₇
Only "0" is output, and "1" is output during other periods.

Therefore, the AND circuit 6 operates in the period T shown in FIG.
_TwoTo period t₆And t₇Remaining time t minus₈Is "1"
And the multi-input AND circuit 4 and the OR circuit 2
Interval t ₈Only "1" is output, so FET2 is also
t₈= T_Two− (T₆+ T₇) Only turns on and FET2
Heating resistance r of the thermal head connected to₀And additional resistance
r₁Are connected in series and the heating resistance r₀Is this period T
_Two− (T₆+ T₇) Only heat generation is controlled.

Next, the control operation in the case where there is print data in q1 of the low energy part, there is no print data in q2 or q3 of the low energy part, and there is print data in Q2 or Q3 of the high energy part, etc. . Due to the nature of the print data, the print data is created so that the print data of the high energy portion and the print data of the low energy portion do not exist together in the same dot.

(2-1) When print data exists in the print dots q1 and Q2, in the print control range of the low energy portion shown in FIG. 4C, print data exists only in the print dot q1 and q2, q3 There is no print data in FIG.
In the case where print data is present in the print dot Q2 in the high energy part shown in FIG. 4B and no print data is present in Q3, q1 = "1", q2 = "0", q3 = "0", and Q3 in FIG.
2 = “1” and Q3 = “0”.

At this time, since q3 = "0", the NAND circuit 2
0 outputs “1”. However, in the NAND circuit 19, although q2 = "0", Q2 = "1" is input to the signal input circuit of q2 via the diode 30. Further, an inverter 23 is connected to the NAND circuit 19 as shown in FIG.
Since the inverted signal of the GATE C1 signal shown in (B) is applied, only the NAND circuit 19 during the period t ₆ in FIG. 5
Outputs “0”, and the other outputs “1”.

Therefore, the AND circuit 6 has the STR shown in FIG.
Period T due to OBE2 signal_TwoTo t ₆Remaining period minus
Between (t₇+ T₈) Outputs "1" and outputs a multi-input AND circuit.
4 also during this period (t₇+ T₈) Only outputs "1"
Thus, FET2 is also turned on only during this period, and is connected to FET2.
Heating resistance r of the continued thermal head₀And additional resistance r₁
Are connected in series and the heating resistance r₀Is (T_Two-T₆)
Heat generation is controlled only during the period.

By shortening the heating time by the period t ₆ in this way, it is possible to prevent the effect of heat accumulation in the print dot Q 2 in the high energy portion with respect to the corresponding print dot q 1.

(2-2) When print data exists in the print dots q1 and Q3, in the print control range of the low energy portion shown in FIG. There is no print data in q3, and FIG.
When print data is present in the print dot Q3 of the high energy portion shown in FIG. 4B and no print data is present in Q2, in FIG. 4A, q1 = "1", q2 = "0", q3 = "0", Q3
2 = “0” and Q3 = “1”.

At this time, since q2 = "0", the NAND circuit 19 outputs "1". However, in the NAND circuit 20, although q3 = "0", Q3 = "1" is input to the signal input circuit of q3 via the diode 31.
Further, the output of the EOR circuit 21 is input to the NAND circuit 20. At this time, the EOR circuit 21 includes the inverter 2
5 and the inverted signal of the GATE C1 signal shown in FIG.
Since the inverted signal of the TE C2 signal is applied, "1" of the two signals do not match the "0", only the EOR circuit 21 period t ₇ shown in FIG. 5 outputs "1", the other periods "0"
Is output. Therefore the NAND circuit 20 outputs "0" only for the period t _7, other periods outputs "1".

Therefore, the AND circuit 6 operates as shown in FIG.
The remaining period (t ₆ + t ₈ ) obtained by subtracting the period t ₇ from the period T ₂ by the ROBE2 signal outputs “1”, and the multi-input AND circuit 4 and the OR circuit 2 also output “1” during this period (t ₆ + t ₈ ). 1 ", the FET 2 is also turned on only during this period, and the heating resistor r ₀ of the thermal head connected to the FET ₂ and the additional resistor r ₁ are connected in series.
₀ is controlled to generate heat only for a period (T ₂ −t ₇ ).

In this way, by shortening the heating period by the period t _7, it is possible to prevent the effect of heat accumulation on the print dot Q 3 in the high energy portion with respect to the print dot q 1.

(2-3) When print data exists in the print dots q1, Q2, and Q3, in the print control range of the low energy portion shown in FIG. There is no print data in q2 and q3, and the print dot Q in the high energy portion shown in FIG.
2, when print data exists in Q3, q1 = “1”, q2 = “0”, q3 = “0”, Q3 in FIG.
2 = “0” and Q3 = “0”.

At this time, in the NAND circuit 19, q2 = "0"
However, the diode 30 is connected to the signal input circuit of q2.
= “1” is input via the. Further, the NAND circuit 19 is connected to the inverter circuit 23 so that the G signal shown in FIG.
Since the inverted signal of the ATE C1 signal is applied, the NAND circuit 19 outputs “0” only during the period t ₆ in FIG. 5, and outputs “1” for the other circuits.

In the NAND circuit 20, although q3 = "0", Q3 = "1" is input to the signal input circuit of q3 via the diode 31. In the NAND circuit 20,
The output of the EOR circuit 21 is input.
The OR circuit 21 outputs the inverted signal of the GATE C1 signal and the GAT signal.
E "1" and the inverted signal of the C2 signal, does not match the "0", only the EOR circuit 21 period t ₇ shown in FIG. 5 outputs "1", other periods outputs "0". For this reason, FIG.
During the NAND circuit 20 of the time t ₇ at outputs "0" and the other outputs "1".

Therefore, the AND circuit 6 operates as shown in FIG.
Period T due to ROBE2 signal_TwoTo period (t₆+ T₇)
Remaining time t minus₈Only "1" is output, so F
ET2 also period t₈= T_Two− (T₆+ T₇Only)
And the heating resistance r of the thermal head connected to FET2.
₀And additional resistance r₁Are connected in series and the heating resistance r ₀
Is this period t₈Only heat generation is controlled.

In this way, by shortening the heating period by the period (t ₆ + t ₇ ), it is possible to prevent the effect of heat accumulation on the printing dots Q2 and Q3 in the high energy portion with respect to the printing dot q1.

(2-4) When print data exists in the print dots q1, q2, and Q3, the print dot q1 in the print control range of the low energy portion shown in FIG.
FIG. 4B shows a case where print data exists in the print dot q2 and no print data exists in the print dot q3, and print data exists in the print dot Q3 in the high energy portion shown in FIG. 4 (A), q1 =
“1”, q2 = “1”, q3 = “0”, Q2 = “0”,
Q3 = “1”.

In this case, the same control as in the above (3) is performed, and the FET 2 is turned on only during the period t ₈ = T ₂ − (t ₆ + t ₇ ).

In this way, by reducing the heat generation time by the period (t ₆ + t ₇ ), the heat storage effect of not only the print dot q2 of the low energy part but also the print dot Q3 of the high energy part with respect to the corresponding print dot q1 is prevented. can do.

(2-5) When print data exists in the print dots q1, q3, and Q2, the corresponding print dot q1 in the print control range of the low energy portion shown in FIG.
FIG. 4B shows a case where print data exists in the print dot q3 and no print data exists in the print dot q2, and print data exists in the print dot Q2 in the high energy portion shown in FIG. 4B but no print data exists in the print dot Q3. 4 (A), q1 =
“1”, q2 = “0”, q3 = “1”, Q2 = “1”,
Q3 = “0”.

In this case, the same control as in the above (3) is performed, and the FET 2 is turned on only during the period t ₈ = T ₂ − (t ₆ + t ₇ ).

By reducing the heat generation time by the period (t ₆ + t ₇ ) in this manner, the heat storage effect of not only the print dot q3 of the low energy portion but also the print dot Q2 of the high energy portion with respect to the corresponding print dot q1 is prevented. can do.

The circuit configuration of a two-power type thermal head using the thermal head of the present invention controlled as described above will be described with reference to FIG. 6 and other figures. FIG. 6 shows an example in which a 64-bit print head is controlled, and the same parts as those in the other figures are denoted by the same reference numerals.
In FIG. 6, FETs 1 and 2 are for controlling printing of the corresponding print dot Q1 described in FIG.
L1 and L2 indicate FETs for controlling the printing of the printing dot on the left side of the corresponding printing dot Q1, FETs R1 and R2 indicate the FETs for controlling the printing of the printing dot on the right side of the corresponding printing dot Q1, and VSS indicates the ground signal. , VDD indicate the power supply voltage of the control system.

A shift register 40 is a 64-bit first register to which print data for the high energy portion Q is inputted.
(Not shown) and a 64-bit second shift register (not shown) to which print data for the low energy portion q is input. In this example, CL
According to the OCK signal, 64-bit input data of the high energy part Q is serially input to the first shift register from DATAin1 (Q), and 64-bit input data of the low energy part q is input to the second shift register from DATAin2 (q). Serial input, DATAout
From 1 (Q) and DATAout (q), for example, the data is serially output to the next stage. Reference numerals 41, 42, 43,... Denote data holding registers for holding print data of 3 bits for the high energy portion Q and 3 bits for the low energy portion q.

The data holding register 41 sequentially holds three lines of the 1-bit print data transmitted to the input terminal D ₁ by the LOAD signal, and also stores the 1-bit print data transmitted to the input terminal d _1. The data is sequentially held for only three lines. Data holding register 42,
43 are the same.

For example, the first print data line for the high energy portion is set in the first shift register of the shift register 40, and the first print data line for the low energy portion is set in the second shift register of the shift register 40. after, entering the LOAD signal to the LATCH terminal of the data holding register 41, 42, 43, ..., the data 1 bit of data in the first shift register is transmitted to the input terminal D ₁ transmitted data retention is output from the terminal Q1 is held in the use register 41, the held in the second shift register of the first bit input terminal d data which also data holding register 41 is transferred to the ₁ data is transmitted in Output from terminal q1.

Similarly, the second bit data of each of the first shift register and the second shift register is output from the output terminals Q1 and q1 of the data holding register 42, and the three bits of each of the first shift register and the second shift register are output. The eye data is output from the output terminals Q1 and q1 of the data holding register 43.

Next, the second print data line for the high energy portion is set in the first shift register of the shift register 40, and the second print data line for the low energy portion is set in the second shift register of the shift register 40. and then, if you enter a LOAD signal to the LATCH terminal of the data holding register 41, 42, 43, ..., which are transmitted one new bit of data in the first shift register to the input terminal D ₁ registers for data retention The data held at 41 and output from the output terminal Q1 and the data previously output from the output terminal Q1 are shifted to the next stage and output from the output terminal Q2. Similar control is performed for the second shift register, which new first bit of data of the second shift register is transmitted to the input terminal d ₁ is output from the terminal q1 is held in the data holding register 41, The data previously output from the output terminal q1 is shifted to the next stage and output data is output to the output terminal q2.
Output.

Similarly, the second bit data of the first shift register and the second shift register are output from the output terminals Q1 and q1 of the data holding register 42, and the data output from the output terminals Q1 and q1 until then. Is shifted to the next stage and output from the output terminals Q2 and q2.

The same control is performed in the data holding register 43, and the third bit data of the first shift register and the second shift register are output from the output terminals Q1 and q1 of the data holding register 43, respectively. The data that has been output from the output terminals Q1 and q1 is shifted to the next stage and output from the output terminals Q2 and q2.

The third print data line for the high energy portion is set in the first shift register of the shift register 40, and the third print data line for the low energy portion is set in the second shift register of the shift register 40. After that, when the LOAD signal is input to the LATCH terminals of the data holding registers 41, 42, 43,..., The same control as described above is performed.
The data of the bit is output from the output terminal Q1, and the data output from the output terminals Q1 and Q2 is shifted to the next stage and output from the output terminals Q2 and Q3, respectively. Also, new first bit data of the second shift register is output from the output terminal q1, and the output terminal q
The data output from 1, q2 is shifted to the next stage and output from output terminals q2, q3, respectively.

Similarly, in the data holding register 42, the new second bit data of the first shift register is output from the output terminal Q1, and the output terminal Q
The data output from Q1 and Q2 is shifted to the next stage and output from output terminals Q2 and Q3, respectively. Further, new second bit data of the second shift register is output from the output terminal q1, and the data output from the output terminals q1 and q2 is shifted to the next stage and output from the output terminals q2 and q3, respectively. .

The output terminal Q2 is connected to the output terminal q2 via the diode 30, and the output terminal Q3 is connected to the output terminal q3 via the diode 31.

Similarly, in the data holding register 43, similarly, new data of the third bit of the first shift register is output from the output terminal Q1, and the data previously output from the output terminals Q1 and Q2 is output. Are shifted to the next stage and output from the output terminals Q2 and Q3, respectively. Also, new third-bit data of the second shift register is output from the output terminal q1, and the data that has been output from the output terminals q1 and q2 is shifted to the next stage and output from the output terminals q2 and q3, respectively. .

Here, the first print data line corresponds to the previous two print lines shown in FIGS.
The third print data line corresponds to the preceding print line, and the third print data line corresponds to the corresponding print line.

The output of the output terminal Q2 of the register 41 is input to the NAND circuit 8 (corresponding to LQ2 in FIG. 4A), and the output of the output terminal Q2 of the register 43 is input to the NAND circuit 10 (FIG. A) RQ2). Thus, a control circuit similar to that described with reference to FIG. 4A is configured based on the outputs of the data holding registers 41, 42, and 43.

Therefore, for FET1, FIG.
(B) A print control range shown in (C) which includes thermal history control according to the state of each print dot.
Control is performed based on the E1 signal and the STROBE2 signal. This control is performed by the FETs L1, L2, FETs R1, R
2 are performed in the same manner.

Therefore, the print data of the high energy portion is input to the first shift register of the shift register 40,
The print data of the low energy portion is input to the shift register, and the STROBE1 signal, STROBE2 signal, G
ATE A1 signal, GATEA2 signal, GATE B1
Signal, GATE B2 signal, GATE C1 signal, GA
By inputting a control signal such as a TEC2 signal, it is possible to simultaneously perform the printing control based on the printing data of the high energy portion and the printing data of the low energy portion, including the heat storage effect prevention control of the printing control range, as described above. For example, FIG.
As shown by 0, multi-color printing is accurately performed by one scan.

Next, a second control circuit per dot of the thermal head according to the present invention will be described with reference to FIGS. FIG. 7 shows an example in which forward print data and adjacent data of a high energy portion are added to a control range, and FIG. 8 is an explanatory diagram of control signals applied to this control circuit.

In the control circuit shown in FIG. 7A, in the unique control in the high energy portion, as shown in FIG. 7B, when the line of the corresponding print dot Q1 is used as the relevant print line, Previous print dot Q at
2 and the left and right print dots LQ2 and RQ2, and the print control range of the previous print dot Q3 in the previous two print lines.

In the unique control in the low energy section, as shown in FIG. 7D, when the line of the corresponding print dot q1 is set as the corresponding print line, the previous print dot q2 in the preceding one print line, and It has a print control range of the previous print dot q3 in the previous two print lines.

In this example, as shown in FIG. 7C, the range of influence of the high energy portion on the corresponding print dot q1 in the low energy portion is determined by the print dots Q2 and Q3 and the LQ2 and LQ2 of the adjacent print dot of the previous print line. RQL2.

Therefore, as shown in FIG. 7A, diodes 30, 31, 32, and 33, an inverter 25, a NAND circuit 26, an EOR circuit 27, and the like are provided.

The GATE C3 signal is shown in FIG.
As described above, the signal falls simultaneously with the STROBE2 signal, and the period (t)
₆+ T₇+ T₈) It will rise later. Of course these
(T ₆+ T₇+ T₈) Can be set appropriately according to the characteristics of the paper.
It can be.

The diodes 30 and 31 are the same as those in the control circuit shown in FIG.

The diode 32 is for controlling the influence of print data on the print dot LQ2 in the high energy portion when the print data is present. The diode 32 has a signal input circuit for the print dot LQ2 in the high energy portion and an input for the NAND circuit 26. It connects to a circuit.

The diode 33 is for controlling the influence of print data in the print dot RQ2 of the high energy portion when the print data is present. The signal input circuit of the print dot RQ2 of the high energy portion and the input of the NAND circuit 26 are provided. It connects to a circuit.

The other input circuit of the NAND circuit 26 has EOR
The output of the circuit 27 is input.

The EOR circuit 27 receives an inverted signal of the GATE C2 signal and an inverted signal of the GATE C3 signal.

FIG. 7A shows the same operation as that of the control circuit shown in FIG. 4A for controlling the high energy portion alone. For the control of the low energy part alone, LQ
Since both RQ2 and RQ2 are "0", the NAND circuit 26 outputs "1" to the multi-input AND circuit 6-0. Otherwise, the operation is the same as that of the control circuit shown in FIG. Therefore, these single operations are omitted for simplification of description.

A typical control for the corresponding print dot q1 in the low energy portion when print data exists in LQ2 and RQ2 in FIG. 7C will be described below.

(3-1) When print data exists in the print dots q1 and LQ2, in the print control range of the low energy portion shown in FIG. 7D, print data exists only in the print dot q1 and q2, q3 There is no print data in FIG.
When print data is present in the print dot LQ2 in the high energy portion shown in FIG. 7C and no print data is present in Q2, Q3, and RQ2, q1 = “1”, q2 = “0” in FIG.
q3 = “0”, Q2 = “0”, Q3 = “0”, LQ2 =
"1", RQ2 = "0".

At this time, since q2 = "0" and Q2 = "0", the NAND circuit 19 outputs "1" and q3 = "0" and Q3
Since 3 = “0”, the NAND circuit 20 outputs “1”.

Since LQ2 = "1", the NAND circuit 26
"1" is applied to one input circuit, and the output of the EOR circuit 27 is input to the other input circuit. Then E
The OR circuit 27 outputs the inverted signal of the GATE C2 signal shown in FIG.
8B, the inverted signal of the GATE C3 signal shown in FIG. 8B is applied, so that the “1” and “0” of both signals do not match, and the EOR circuit 27 only for the period t ₈ shown in FIG. 8B.
Outputs “1”, and outputs “0” in other periods. Therefore the NAND circuit 26 outputs "0" only for the period t _8, other periods outputs "1".

Therefore, the multi-input AND circuit 6-0 has the structure shown in FIG.
Period T due to STROBE2 signal shown_TwoTo period t₈To
Remaining period (t₆+ T₇+ T₉) Outputs "1"
Then, the multi-input AND circuit 4 and the OR circuit 2 also operate during this period (t
₆+ T₇+ T₉) = T_Two-T ₈Only output "1"
Thus, FET2 is also turned on only during this period, and is connected to FET2.
Heating resistance r of the continued thermal head₀And additional resistance r₁
Are connected in series and the heating resistance r₀Is this (T_Two-T
₈) Heat generation is controlled only during the period.

[0145] By shortening the only heating time period t ₈ in this manner, it is possible to prevent heat accumulation effect in the print dot LQ2 in the high energy portion to the corresponding print dot q1.

(3-2) When print data exists in print dots q1 and RQ2, in the print control range of the low energy portion shown in FIG. In the case where there is no print data in q3, there is print data in the print dot RQ2 of the high energy portion shown in FIG. 7C, and there is no print data in Q2, Q3 and LQ2, q1 = "1" in FIG. 7A. , Q2 =
“0”, q3 = “0”, Q2 = “0”, Q3 = “0”,
LQ2 = "0" and RQ2 = "1".

At this time, since q2 = "0" and Q2 = "0", the NAND circuit 19 outputs "1" and q3 = "0" and Q3
Since 3 = “0”, the NAND circuit 20 outputs “1”.

Since RQ2 = “1”, the NAND circuit 26
"1" is applied to one input circuit, and the output of the EOR circuit 27 is input to the other input circuit. Thus as in the case where print data exists in the print dot q1 and LQ2 of the (1) only during the period t ₈ shown in FIG. 8 (B) E
The OR circuit 27 outputs “1” and outputs “0” in other periods, and the heating resistor r ₀ and the additional resistor r _{1 of} the thermal head connected to the FET 2 are connected in series.
₀ is controlled to generate heat only for a period (T ₁ −t ₈ ).

[0149] By shortening the way by the period t ₈ the heating time, it is possible to prevent the heat accumulation effect in the print dot RQ2 high energy portion to the corresponding print dot q1.

(3-3) Print dot q1, LQ2, R
When the print data exists in Q2, in the print control range of the low energy portion shown in FIG.
If there is no print data in q2 and q3 and there is print data in the print dots LQ2 and RQ2 in the high energy portion shown in FIG. 1 ”, q2 =“ 0 ”, q3 =“ 0 ”, Q
2 = “0”, Q3 = “0”, LQ2 = “1”, LQ2 =
It becomes "1".

At this time, as in the case where the print data exists in the print dots q1 and LQ2 in the above (1), FIG.
Only EOR circuit 27 period t ₈ shown in (B) outputs a "1", the other period, the outputs "0", the heating resistor r ₀ and an additional resistance r ₁ of the connected thermal head series FET2 In the connected state, the heat generation of the heating resistor r ₀ is controlled only for a period of (T ₂ −t ₈ ).

[0152] By shortening the way by the period t ₈ the heating time, it is possible to prevent the heat accumulation effect in the print dot LQ2, RQ2 high energy portion to the corresponding print dot q1.

(3-4) Print dots q1, Q2, LQ
When the print data exists in the print control range of the low energy portion shown in FIG.
No. 1 has print data, q2 and q3 have no print data, and the print dots Q in the high energy portion shown in FIG.
2, when there is print data in LQ2 and no print data in Q3 and RQ2, q1 = “1” in FIG.
= "0", q3 = "0", Q2 = "1", LQ2 =
“1”, Q3 = “0”, and RQ2 = “0”.

At this time, since q3 = "0" and Q3 = "0", the NAND circuit 20 outputs "1". However, in the NAND circuit 19, although q2 = "0", Q2 = "1" is input to the signal input circuit of q2 via the diode 30. Further by the inverter 23 to the NAND circuit 19, the inverted signal of the GATE C1 signal shown in FIG. 8 (B) is applied, the NAND circuit 19 only during the period t ₆ in FIG. 8 (B) is a "0" The other outputs "1".

Since LQ2 = "1", the diode 3
2 to one input circuit of the NAND circuit 26 via "1"
And the output of the EOR circuit 27 is input to the other input circuit. At this time, the inverted signal of GATE C2 shown in FIG. 8B by the inverter 24 and the GAT signal shown in FIG.
Since the inverted signal of the EC3 signal is applied, "1" and "0" of both signals do not coincide with each other, and the period t shown in FIG.
_{For eight, the} EOR circuit 27 outputs “1”, and outputs “0” in other periods. Therefore, the NAND circuit 26 operates in the period t ₈
Only "0" is output, and "1" is output during other periods.

Therefore, the multi-input AND circuit 6-0 has the structure shown in FIG.
The remaining period (t ₇ + t ₉ ) obtained by subtracting the periods t ₆ and t ₈ from the period T ₂ by the STROBE2 signal shown in FIG. 3B outputs “1”, and the multi-input AND circuit 4 and the OR circuit 2 also output this signal. period _{(t 7 + t 9) =} T 2 - since (t ₆ + t ₈₎ only outputs "1", FET2 becomes oN only during this period, additional resistance r and the heat generating resistor r ₀ of the thermal head connected to the FET2 Heating resistance r with ₁ connected in series
₀ is controlled to generate heat only during this [T _2- (t ₆ + t ₈ )] period.

By shortening the heating time by the period (t ₆ + t ₈ ), it is possible to prevent the effect of heat accumulation on the printing dots Q2 and LQ2 in the high energy portion with respect to the printing dot q1.

(3-5) Print dots q1, Q3, LQ
When the print data exists in the print control range of the low energy portion shown in FIG.
No. 1 has print data, q2 and q3 have no print data, and the print dots Q in the high energy portion shown in FIG.
3, when there is print data in LQ2 and no print data in Q2 and RQ2, q1 = "1" in FIG.
= “0”, q3 = “0”, Q2 = “0”, Q3 =
“1”, LQ2 = “1”, and RQ2 = “0”.

At this time, since q2 = "0" and Q2 = "0", the NAND circuit 19 outputs "1". However, in the NAND circuit 20, although q3 = "0", Q3 = "1" is input to the signal input circuit of q3 via the diode 31. Further, the output of the EOR circuit 21 is input to the other input circuit of the NAND circuit 20. At this time, EOR
Since the inverted signal of the GATE C1 signal shown in FIG. 8B by the inverter 23 and the inverted signal of the GATE C2 signal shown in FIG. Does not match, FIG. 8 (B)
The EOR circuit 21 outputs “1” only for the period t ₇ shown in FIG.
In other periods, “0” is output. Therefore, the NAND circuit 20
Outputs only the period t ₇ "0", the other period, the output "1".

[0160] Further LQ2 = only for the period t ₈ the NAND circuit 26, as shown when the print data to the print dots q1 and LQ2 of the (1) for the "1" is present and outputs "0", the other During the period, “1” is output.

Accordingly, the multi-input AND circuit 6-0 has a structure shown in FIG.
The remaining period (t ₆ + t ₉ ) obtained by subtracting the periods t ₇ and t ₈ from the period T ₂ by the STROBE2 signal shown in FIG. 3B outputs “1”, and the multi-input AND circuit 4 and the OR circuit 2 also output this signal. period _{(t 6 + t 9) =} T 2 - since (t ₇ + t ₈₎ only outputs "1", FET2 becomes oN only during this period, additional resistance r and the heat generating resistor r ₀ of the thermal head connected to the FET2 Heating resistance r with ₁ connected in series
₀ is controlled to generate heat only during this [T _2- (t ₇ + t ₈ )] period.

By shortening the heating time by the period (t ₇ + t ₈ ) in this way, it is possible to prevent the effect of heat storage on the printing dots Q3 and LQ2 in the high energy portion with respect to the printing dot q1.

In the other cases, the control circuit shown in FIG. 7A can prevent the adverse effect of the printing dots in the high energy portion.

As described above, according to the present invention, high energy printing control and low energy printing control can be performed very accurately.
Even when data of two colors are mixed, accurate printing can be performed.

In the above description, the embodiments for two energies, high and low, have been described. However, the present invention is of course not limited to this.

The colors are not limited to red and black, but may be green and black, another combination, or a combination of three or more colors.

[0167] Another embodiment of the present invention will be described.

Some print media, such as Aladdin Card (registered trademark) manufactured by Tokyo Magnetic Printing Co., Ltd., allow printing when high energy is applied by a thermal head, but change to another color when low energy is applied. There are rewritable media that can erase characters and the like printed with high energy and write character figures and the like again with high energy printing.

A head as shown in FIG. 1 and a control circuit as shown in FIGS. 4 and 7 can also be used for such a medium. In this case, the STROBE1 signal is set so as to add high energy for printing, and the STROBE2 signal is set so as to give low energy for erasing printed characters and the like. In this case, q1, q2, and q3 are print erasure data for performing print erasure control. This medium has a very strict setting of the low energy range for erasing,
In addition to the magnitude of the TROBE2 signal, the q2, q3
History control based on presence / absence of print, ie, print erase data q
2, it is preferable to perform heat control by q3, suppress the unit heat value by an additional resistor, and adjust the energy of the STROBE2 signal to adjust the energy.

In this manner, a thermal head for a rewritable medium can be provided.

The case where STROBE2 has the same length as STROBE1 has been described, but the present invention is not limited to this, and may be larger or smaller.

[0172]

According to the present invention, the following effects can be obtained.

(1) A thin-film resistor in which a heating resistor and an additional resistor are integrally formed is formed on an insulating substrate, and a glaze layer is formed below the heating resistor.
The heat generated by the heat generating resistor portion is stored by the glaze layer, so that the heat treatment of the thermal paper can be performed accurately, and the heat generated by the additional resistor can be radiated well through the insulating substrate on which the glaze layer is not formed. So you can
Even if the heating resistor and the additional resistor are integrally formed, it is possible to suppress the adverse effect caused by the heat generated by the additional resistor.

(2) Since the heating resistor and the additional resistor are connected in series based on the input of the second strobe signal and these are energized, the unit heating value of the heating resistor is reduced by only the heating resistor. It can be made smaller than the unit heat value of the high energy state that is energized independently. For this reason, it is possible to provide a two-power type thermal head suitable for thermal paper whose characteristics in the low energy state require a small amount of heat generation.

[Brief description of the drawings]

FIG. 1 is a sectional view of a heat generating portion of a two-power thermal head showing one embodiment of a thermal head according to the present invention.

FIG. 2 is an explanatory diagram illustrating a connection state between a heat generating portion of a two-power thermal head and a driving IC according to the present invention.

FIG. 3 is a comparison diagram of heat generation energy between a conventional example and the present invention.

FIG. 4 is a drive control circuit per dot of the thermal head of the present invention.

5 is an explanatory diagram of control signals applied to the drive control circuit of FIG.

FIG. 6 is an explanatory diagram of a printed circuit using the thermal head of the present invention.

FIG. 7 is a second drive control circuit per dot of the thermal head of the present invention.

FIG. 8 is an explanatory diagram of control signals applied to the drive control circuit of FIG. 7;

FIG. 9 is an explanatory diagram of printing energy for thermal paper.

FIG. 10 is an explanatory diagram of multicolor printing.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Insulating substrate 101 Glaze layer 102 Polysilicon layer 102-1 Heating resistor section 102-2 Additional resistor section 103 Common electrode layer 104 Conductive line 104-1 First electrode connection section 104-2 Second electrode connection section 105 Protective layer

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhito Uchida 1-13-1 Nihonbashi, Chuo-ku, Tokyo TDC Corporation F term (reference) 2C065 AB01 AC01 CZ03 KJ15 KJ17

Claims (2)

[Claims] A heating resistor formed on a glaze layer partially provided on an insulating substrate; a thin film resistor layer integrally formed with an additional resistor formed on the insulating substrate; A first electrode connection portion provided on the layer and connected to the first switching means; and a second electrode connection portion provided on the thin film resistance layer and connected to the second switching means. 2-power type thermal head. 2. A thin-film resistance layer integrally formed with a heating resistor portion formed on a glaze layer partially provided on an insulating substrate, an additional resistor portion formed on the insulating substrate, A first electrode connection provided on the layer and connected to the first switching means; a second electrode connection provided on the thin-film resistance layer and connected to the second switching means; A first strobe signal input means for controlling the heat generation of the heating resistor by a first energy; and a second strobe signal input for controlling the heat generation of the heating resistor by a second energy to the second switching means. Means, based on the input of the second strobe signal,
The heating resistor and the additional resistor are connected in series and energized, and the unit heating value of the heating resistor is a unit heating value generated by the heating resistor based on the input of the first strobe signal. A two-power type thermal head characterized by being smaller than the above.