JP2001010099A - Double power-type thermal head - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thermal head capable of accurately outputting different heating temperatures in the identical scanning to a thermal medium representing different colors corresponding to the heating temperatures. SOLUTION: This thermal head comprises a heating body r0 for executing the heating in different energies, an additional resistor r1 connected to the heating body r0, a first switching means 1 for controlling the heating body r0 in an active condition or an inactive condition and a second switching means 2 for controlling the heating body r0 and additional resistor r1 in an active condition or an inactive condition. When controlling the heating body r0 in the first energy condition, the heating body r0 is controlled to generate the heat by the first switching means 1. When controlling the heating body r0 in the second energy condition, the heating body r0 and additional resistor r1 are controlled in the series connecting condition by the second switching means 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal head for two-color printing which can output different heating temperatures during the same scanning and is suitable for, for example, a heat-sensitive element which develops different colors depending on the heating temperature. The present invention relates to an apparatus for optimizing print quality by making a difference between high and low powers applied to a high-temperature thermal head and a low-temperature thermal head.

[0002]

When printing with respect to the thermal paper by the Related Art Thermal head, conventionally, as shown in FIG. 8 (A), printing energy (temperature) and T ₀ from as high as the print temperature constant, such as for example, black color When the energy is lower than that, the print density becomes lighter, so that the portion not desired to be printed does not heat the thermal head. That is, only the operation control of printing or not printing is performed based on the presence or absence of data on one line.

In order to perform this control, there is a type in which a hysteresis control circuit is added to limit a rise in temperature due to heat storage of the thermal head substrate. However, when printing, the thermal head is set to a single temperature, that is, a single energy. Control was the goal.

In recent years, a multi-color thermal paper has been manufactured in which, for example, printing is performed in black when printing with a high-temperature thermal head, and printed in red, for example, when printing with a low-temperature thermal head. For example, it is provided as product name MB-23 of Oji Paper Co., Ltd.

Namely, the heat-sensitive paper of this kind, as shown in FIG. 8 (B), when the thermal head of the printing energy (temperature) is T _2, and color, for example red, printing energy is T ₁
When (T ₂ <T ₁ ), the color develops black. Note whitening phenomenon appears when still higher than T _1. In addition to this type of heat-sensitive paper, not only a combination of red and black, but also a combination of other colors based on low / high printing energy exists.

[0006] Using such a multi-color thermal paper, when performing multi-color printing, for example, as shown in FIG. 9 (A), when performing red and black print on the scanning line L _0, the thermal head in the conventional , for example first data is transferred via the current amount corresponding to the low temperature of the print data portions for red, then it is necessary to perform a data transfer by a current amount corresponding to the high temperature on the same scanning line L ₀ again Was.

Further, as shown in FIG. 9B, even in the case of performing two-color printing of red and black, the printing data of the red portion is also changed by the current amount corresponding to the low temperature in the scanning lines L ₁ , L _2. Data transfer is performed, and then the same scan lines L ₁ , L
₂ ... Data transfer was performed by the amount of current corresponding to the high temperature above.

In order to cope with two types of energy, data transfer is performed twice in one line, and each energy is set. Therefore, there is a problem that the printing speed is slow because two data transfers are required for one line.

In order to solve this problem, the present inventor has previously proposed in Japanese Patent Application No. 9-302728 a thermal head which can perform this in one scan even when different energy settings are made for one line.

In the control circuit of the thermal head, the control of the data of the high energy part and the control of the data of the low energy part are performed independently. for that reason,
When such two types of input energy data coexist, it is not possible to print with low-energy data on low-energy print dots due to the influence of the high-energy side. Become.
For example, what should be printed in red is printed in a color close to black.

In order to improve such a problem, the present inventor has disclosed in Japanese Patent Application No. 10-12320 that the presence or absence of high energy print data in the vicinity of a print point does not affect the print output of low energy data. A thermal head was proposed.

First, a control state of the thermal head will be described with reference to FIG.

In FIG. 10A, reference numeral 1 denotes an FET, which is connected to a terminal DOn of a one-dot heater of a thermal head (not shown) and controls on / off of the terminal DOn. 2 is an OR circuit, 3 to 5 are multi-input AND circuits, 6 is an AND circuit, 7 to 10 are NAND circuits, 11, 1
2 is an EOR (exclusive sheave) circuit, 13 is an output protection circuit, 14 to 18 are inverters, 19 and 20 are NAND circuits, 21 is an EOR circuit, and 22 to 24 are inverters.

When the IC constituting the thermal head is operating normally, the output protection circuit 13 operates when the multi-input AND circuits 3 and 4 are operated.
Is output as "1".

A signal indicating the presence or absence of the print dots Q1, Q2, Q3, LQ2, and RQ2 in the high energy portion shown in FIG. 10B is a signal Q1, Q2, Q shown in FIG.
3, LQ2 and RQ2, and the signals indicating the presence / absence of the print dots q1, q2 and q3 in the low energy portion shown in FIG. 10C are the signals q1 and q2 shown in FIG.
q3.

Then, as described later, the strobe signal S
TROBE1 is for heating the thermal head as a high-energy part for a long time to print black on paper, and strobe signal STROBE2 is heating the thermal head for a short time as a low-energy part to print red, for example, on paper. STROBE1> STR
OBE2.

When printing the corresponding print Q1 shown in FIG. 10B, if there is no print data in Q2, Q3, LQ2, and RQ2, these are "0", and the NAND circuits 7 to
10 outputs "1", the multi-input AND circuit 5 and the multi-input AND circuit 3 output "1", and the OR circuit 2 outputs the strobe signal STROB.
Turn on time T ₁ only FET1 defined by E1, heating the heater of the thermal head.

However, if there is print data in at least one of Q2, Q3, LQ2, and RQ2, the gate signals A1,
B1, A2, only being controlled time based on B2 output time of multi-input AND "1" of the the circuit 5 is output is "0" strobe signal STROBE1 by multi-input AND circuit 3 is shorter than the T ₁ And the energy of the heater of the thermal head in the strobe signal STROBE1 is controlled to be equal.

When the corresponding print q1 shown in FIG. 10C is printed, if there is no print data in q2 and q3, these are "0", and both NAND circuits 19 and 20 output "1". Therefore, both the AND circuit 6 and the multi-input AND circuit 4 output "1", whereby the OR circuit 2 turns on the FET ₁ for a time T ₂ (T ₁ > T ₂ ) determined by the strobe signal STROBE2, Heat the heater of the thermal head.

However, if there is print data in at least one of q2 and q3, the AND circuit 6 is controlled for a time controlled based on the gate signals C1 and C2 corresponding to the print data in consideration of the heat storage effect, as described later. controlled to be shorter than the T ₂ output time of "1" of the multi-input aND circuit 4 according to the strobe signal STROBE2 "0" is outputted from the equal heater energy of the thermal head in the strobe signal STROBE2 Control so that

In this manner, the print head can be energized by a plurality of long and short strobe signals in one scanning line, so that a sheet which emits different colors with respect to a plurality of heat energies can be formed. On the other hand, the print head can be controlled by a plurality of thermal energies by one print scan, and a plurality of colors can be printed by one print scan.

Accordingly, it is not necessary to scan the same scanning line a plurality of times in accordance with the number of colors as in the conventional case, and printing of a plurality of colors can be performed at high speed.

The operation of the control circuit shown in FIG.
This will be described in more detail with reference to the control signal of FIG.

The various control signals shown in FIG. 11 are output from a control signal output circuit (not shown).
Both are output in the same cycle S.

The control signals shown in FIG. 11A are various control signals for controlling the thermal head in a high energy state, and the control signals shown in FIG. 11B are for controlling the thermal head in a low energy state. Are various control signals.

[0026] STROBE1 signal, the printing control range shown in FIG. 10 (B), when printing only the appropriate print dot Q1 dot is present, a thermal head connected thereto to turn on period T ₁ only FET1 is intended to heating control only for the period T _1, as shown in FIG. 11 (a),
Only the period T ₁ is at a low level.

[0027] GATE A1 signal, falls at the same time as the STROBE1 signal, in which rises after a period t _1.

The GATE A2 signal falls at the same time as the STROBE1 signal, and rises after a period (t ₁ + t ₂ ).

The GATE B1 signal is a STROBE1 signal.
Period (t₁+ T _Two+ T_Three+ T_Four)rear
And then the period t_FiveLater, STROBE1
It rises simultaneously with the issue.

The GATE B2 signal is a STROBE1 signal.
Period (t₁+ T _Two+ T_Three) Fall after
And then the period (t_Four+ T_Five) Later, STROBE
It rises at the same time as one signal.

The STROBE2 signal is shown in FIG.
In the printing control range shown in, when there is a printed dot only the appropriate print dot q1, by the period T ₂ FET1
Is turned on and the thermal head connected to the
₂ (T ₂ <T ₁ ) to control the heating.
As (B), the falls simultaneously with STROBE1 signal only during the period T ₂ is at a low level.

[0032] GATE C1 signal, falls at the same time as the STROBE2 signal, in which rises after a period t _6.

The GATE C2 signal falls at the same time as the STROBE2 signal, and rises after a period (t ₆ + t ₇ ).

And these T ₁ , T ₂ , t _{1 to} t ₈ are:
It can be set appropriately according to the characteristics of the paper.

First, based on FIG. 10 and FIG. 11, the thermal history control is performed in the printing control range shown in FIG. 10B and FIG.
-Q3, LQ2, and RQ2 have print data as shown below, and print dots q
Regarding 1 to q3, a case where print data exists as described below will be described.

Here, when Q1 is the corresponding print dot,
Q2 indicates a print dot immediately before the one line, and Q3 indicates a print dot immediately before the two lines. LQ2 indicates the left print dot one line before, and RQ2 indicates the right print dot one line before.

When q1 is the corresponding print dot,
q2 indicates a print dot immediately before the one line, and q3 indicates 2
Indicates the print dot immediately before the line.

(1) When print data exists only in the print dot Q1, in the print control range shown in FIG. 10B, print data exists only in the print dot Q1.
If there is no print data in 2, Q3, LQ2, and RQ2, Q1 = "1", Q2 = "0", and Q2 in FIG.
3 = “0”, LQ2 = “0”, and RQ2 = “0”.

Since each of the NAND circuits 7 to 10 outputs "1" according to each "0", the multi-input AND circuit 5 outputs "1". At this time, if the thermal head is normal, “1” is output from the output protection circuit 13 and Q1 = “1”.
Since STROBE1 signal as shown in (A) is transmitted, "1" is output from the period T ₁ only multi-input AND circuit 3 shown in Figure 11 (A). At this time, since q1 = “0”, the multi-input AND circuit 4 outputs “0”.

As described above, since "1" output from the multi-input AND circuit 3 is input to the FET 1 via the OR circuit 2, the OR circuit 2 eventually has print data in Q1, Q2, Q3, LQ2, if there is no print data to RQ2, which was turned on by applying only the period T ₁ to "1" to the FET1, to heating control of the heater of the thermal head connected to FET1 only for the period T _1.

(2) When print data exists in the print dots Q1 and Q2, and when print data exists in the print dot Q1 and the print dot Q2 one line before the print data, FIG.
In (A), “1” is applied to each of Q1 and Q2,
3 = “0”, LQ2 = “0”, and RQ2 = “0” are applied. As a result, the NAND circuits 8 to 10 each become “1”.
Is output.

At this time, the NAND circuit 7 includes the inverter 1
The 5, since FIG. 11 the inverted signal and Q2 = "1" GATE A1 signal shown in (A) is applied, the NAND circuit only during the period t ₁ in FIG. 11 7 outputs "0", the other is "1" is output. Thus the multi-input AND circuit 5, the remaining time obtained by subtracting the time t ₁ from the period T ₁ shown in FIG. _{11 (t 2 + t 3 +} t 4 + t 5) outputs "1", FET
1 is also turned on only during this period, and controls the heating of the heater of the thermal head connected to the FET _{1 for the} period (T ₁ −t ₁ ).

(3) When print data exists in the print dots Q1 and LQ2, and when print data exists in the print dot L1 adjacent to the print dot Q1 and the left adjacent print dot LQ2 in FIG.
"1" is applied to each of Q1 and LQ2 of 0 (A),
Q2 = "0", Q3 = "0", and RQ2 = "0" are applied. Thereby, the NAND circuit 7 and the NAND circuits 9, 10
Output "1".

At this time, LQ2 =
“1” and the output of the EOR circuit 11 are input. EO
FIG. 11 (A) shows an R circuit 11 using an inverter 15.
And the inverted signal of the GATE A1 signal shown in FIG.
According to 6, since the inverted signal of GATE A2 signal shown in FIG. 11 (A) is applied, only the EOR circuit 11 a period t ₂ shown in FIG. 11 outputs "1", the other period to "0" Output. For this reason the NAND circuit 8 is only for the period t ₂ "0"
And outputs “1” in other periods.

Therefore, the multi-input AND circuit 3 operates by subtracting the period t ₂ from the period T ₁ shown in FIG. 11 (t ₁ + t
₃ + t ₄ + t ₅₎ outputs "1", FET1 also only this time turned on to heating control of the heater of the thermal head connected to FET1 only (T ₁ -t ₂₎ period.

(4) When print data exists in the print dots Q1 and RQ2, and when print data exists in the print dot RQ2 adjacent to and immediately before the corresponding print dot Q1, the print data shown in FIG.
"1" is applied to Q1 and RQ2 of 0 (A), respectively.
Q2 = "0", Q3 = "0", and LQ2 = "0" are applied. Thereby, each of the NAND circuits 7 to 9 is “1”.
Is output.

At this time, RQ2 =
“1” and the output of the EOR circuit 12 are input. EO
The R circuit 12 includes an inverter 17 shown in FIG.
The inverted signal of the GATE B1 signal shown in FIG.
According to 8, since the inverted signal of GATE B2 shown in FIG. 11 (A) is applied only during the period t ₄ when FIG. 11 EO
The R circuit 12 outputs “1”, and outputs “0” in other periods. Therefore the NAND circuit 10 outputs only the period t ₄ "0", other periods outputs "1".

[0048] Thus the multi-input AND circuit 3, the remaining time obtained by subtracting the time t ₄ from the period T ₁ shown in FIG. 11 (t ₁ + t
₂ + t ₃ + t ₅₎ outputs "1", FET1 also only this time turned on to heating control of the heater of the thermal head connected to FET1 only (T ₁ -t ₄₎ period.

(5) When print data exists in the print dots Q1 and Q3, and when print data exists in the print dot Q1 and the print dot Q3 two dots before the print data, FIG.
“1” is applied to each of Q1 and Q3 in FIG.
= “0”, LQ2 = “0”, and RQ2 = “0”. Thus, the NAND circuits 7, 8 and 10 each output "1".

At this time, Q3 = “1” in the NAND circuit 9
And the GAT shown in FIG.
Since the inverted signal of the E B1 signal is applied, the period t ₅ only the NAND circuit 9 shown in FIG. 11 outputs "0", other periods outputs "1".

Therefore, the multi-input AND circuit 3 calculates the remaining period (t ₁ + t) obtained by subtracting the period t ₅ from the period T ₁ shown in FIG.
₂ + t ₃ + t ₄₎ outputs "1", FET1 also only this time turned on to heating control of the heater of the thermal head connected to FET1 only (T ₁ -t ₅₎ period.

(6) When print data exists in the print dots Q1, Q2, and Q3, when print data exists in the print dot Q1, the print dot Q2 one dot before the print dot Q2, and the print dot Q3 two dots before the print dot Q1 , Q in FIG.
“1” is applied to each of 1, Q2, and Q3, and LQ2 =
“0” and RQ2 = “0” are applied. As a result, the NAND circuits 8 and 10 each output "1".

At this time, Q2 = "1" is applied to the NAND circuit 7.
And the GAT shown in FIG.
Since the inverted signal of the E A1 signal and is applied, the NAND circuit 7 only during the period t ₁ in Figure 11 outputs "0", other periods outputs "1". In addition, in the NAND circuit 9, Q3 = "1",
Since the inverted signal of the GATE B1 signal shown in (A) and is applied, the NAND circuit 9 only for the period t ₅ shown in FIG. 11 outputs "0", other periods outputs "1".

Therefore, the multi-input AND circuit 3 outputs “1” for the remaining period (t ₂ + t ₃ + t ₄ ) obtained by subtracting the periods t ₁ and t ₅ from the period T ₁ shown in FIG. It turns on only during this period, and controls the heating of the heater of the thermal head connected to the FET ₁ only for the period (T ₁ −t ₁ −t ₅ ).

(7) Print dots Q1, Q2, Q3, L
When print data exists in a plurality of print dots among Q2 and RQ3, the corresponding print dot Q1 and print dot Q
A plurality of print dots among 2, Q3, LQ2, RQ2,
For example, when print data exists in Q2 and LQ2,
Since 3 = “0” and RQ2 = “0”, the NAND circuits 9 and 10
Output "1".

At this time, the GATE A1 signal shown in FIG. 11A and Q2 = "1" are applied to the NAND circuit 7 by the inverter 15 as shown in (2) above.
Only the NAND circuit 7 during the period t ₁ in FIG. 11 is "0"
Is output.

As shown in the above (3), LQ2 = "1" and the output of the EOR circuit 11 are input to the NAND circuit 8. The EOR circuit 11 includes an inverted signal of the GATE A1 signal shown in FIG. 11A by the inverter 15 and a GATE A signal shown in FIG.
Since the inverted signal of the two signals is applied, the period t ₂ only EOR circuit 11 shown in FIG. 11 outputs "1", other periods outputs "0". Therefore, the NAND circuit 8 operates in the period t ₂
Only "0" is output.

Accordingly, when print data exists in Q2 and LQ2, when data exists in the corresponding print dot Q1 and print dot Q2, the period t ₁ during which the multi-input AND circuit 5 outputs “0”, and the corresponding print dot Q1 outputs (t ₁ + t ₂₎ only multi-input aND circuit 5 is "0" in the sum of the time period t ₂ to the multi-input aND circuit 5 outputs "0" when the data in the print dots LQ2 is present and, FET1 Is controlled by (T ₁ −t ₁ −t ₂ ).

That is, when print data exists in the corresponding print dot Q1 and a plurality of print dots among the print dots Q2, Q3, LQ2, and RQ2, the relevant print dot Q1 and other print dots Q2, Q3, LQ2, RQ2 When there is data in the print dot of the multi-input AND circuit 5, the multi-input AND circuit 5 is operated by the sum of the periods of “0” described in the above (2) to (5) according to the other print dots. outputs "0", the period F which is obtained by subtracting from only T ₁ period of the sum of these
The heater of the thermal head connected to ET1 is heated.

For example, Q1, Q2, Q3, LQ2, RQ
When all of the 2 printing data is present, T ₁ - (t <sub>1
+ T 2 + t 4 + t</sub> 5) = period only multi-input AND circuit 5 of t ₃ outputs "1" to heat the heater of the connected thermal head only FET1 this period t _3.

(8) When print data exists only in print dot q1, in the print control range shown in FIG. 10C, print data exists only in print dot q1 and q
FIG. 10A shows a case where print data does not exist in q2 and q3.
Then, q1 = "1", q2 = "0", and q3 = "0".

Accordingly, since q2 = "0" and q3 = "0", "1" is output to the NAND circuits 19 and 20, respectively, so that the multi-input CAND circuit 6 outputs "1". At this time, if the thermal head is normal, "1" is output from the output protection circuit 13. At this time, q1 = “1”, and the inverter 22 has STROBE2 as shown in FIG.
Since the signal is transmitted, "1" is output from the period T ₂ by multi-input AND circuit 4 shown in FIG. 11 (B). At this time, since Q1 = “0”, the multi-input AND circuit 3 outputs “0”.

As described above, since "1" output from the multi-input AND circuit 4 is input to the FET 1 via the OR circuit 2, the OR circuit 2 eventually has print data in q1, q2, If there is no print data in q3, the period T
₂ (T ₂ <T ₁ ), “1” is applied to the FET 1 to turn it on, and the heater of the thermal head connected to the FET 1 is heated and controlled for the period T ₂ .

(9) When print data exists in the print dots q1 and q2, and when print data exists in the print dot q1 and the print dot q2 one line before the print data, FIG.
In (A), “1” is applied to q1 and q2, respectively, and q
3 = “0” is applied. Thereby, the NAND circuit 20 outputs “1”.

At this time, the inverted signal of the GATE C1 signal shown in FIG. 11 (B) and q2 = “1” are applied to the NAND circuit 19 by the inverter 23, so that the NAND circuit 19 is operated only during the period t ₆ in FIG. The circuit 19 outputs "0", and the other outputs "1". Therefore, the AND circuit 6 outputs “1” for the remaining period (t ₇ + t ₈ ) obtained by subtracting the period t ₆ from the period T ₂ shown in FIG.
And because even the OR circuit 2 outputs "1" during this period only (t ₇ + t _8), becomes even only this time on FET1, F
Set the heater of the thermal head connected to ET1 to (T ₂ −
t ₆₎ to only heating control period.

(10) When print data exists in the print dots q1 and q3, and when print data exists in the print dot q1 and the print dot q3 two dots before the print data, FIG.
At 0 (A), “1” is applied to q1 and q3, respectively, and q
2 = “0” is applied. Thus, the NAND circuit 19 outputs “1”.

At this time, in the NAND circuit 20, q3 =
“1” and the output of the EOR circuit 21 are input. EO
The R circuit 21 includes an inverter 23, as shown in FIG.
The inverted signal of the GATE C1 signal shown in FIG.
According to 4, since the inversion signal of the GATE C2 signal shown in FIG. 11 (B) is applied, "1" of the two signals, the period t ₇ only EOR circuit 21 shown in FIG. 11 does not match the "0""1 ”And outputs“ 0 ”during other periods. Therefore the NAND circuit 20 outputs "0" only for the period t _7, other periods outputs "1".

Therefore, the AND circuit 6 outputs “1” for the remaining period (t ₆ + t ₈ ) obtained by subtracting the period t ₇ from the period T ₂ shown in FIG. 11, and the multi-input AND circuit 4 and the OR circuit 2 Since “1” is output only during this period (t ₆ + t ₈ ), F
ET1 becomes ON only this period, the heating control of the heater of the thermal head connected to FET1 by (T ₂ -t ₇₎ period.

(11) When print data exists in the print dots q1, q2, q3, the print data is stored in the print dot q1, the print dot q2 immediately before the print dot q2, and the print dot q3 two dots before the print dot q2. Figure 1 when present
“1” is applied to q1, q2, and q3 of 0 (A).

At this time, as shown in the above (9), the inverted signal of the GATE C1 signal shown in FIG. 11B and q2 = "1" are applied to the AND circuit 19 by the inverter 23. The NAND circuit 19 outputs “0” only during the period t ₆ in FIG.

As shown in (10), q3 = “1” and the output of the EOR circuit 21 are input to the NAND circuit 20. At this time, the inverted signal of the GATE C1 signal shown in FIG. 11B by the inverter 23 and the inverted signal of the GATE C2 signal shown in FIG. 11B by the inverter 24 are applied to the EOR circuit 21. , "1" of the two signals, EOR circuit 21 only for the period t ₇ shown in FIG. 11 does not match the "0" outputs "1", other periods outputs "0". Therefore the NAND circuit 20 outputs "0" only for the period t _7, other periods outputs "1".

Therefore, the AND circuit 6 operates during the period shown in FIG.
T_TwoTo period t₆And t₇Remaining time t minus₈Is
Outputs “1”, and the multi-input AND circuit 4 and the OR circuit 2
This period t₈Output "1" only, so FET1
Period t₈= T_Two− (T₆+ T₇) Only turns on and F
The heater of the thermal head connected to ET1 is turned on during this period.
T _Two− (T₆+ T₇) Only heating control.

As described above, the heater of the thermal head can arbitrarily output data of a high energy portion or data of a low energy portion. For example, it is possible to control the printing of black on the multi-color thermal paper by the data of the high energy part, and to control the red printing by the data of the low energy part.

By the way, in such a control circuit, the control for the data of the high energy part and the control for the data of the low energy part are performed independently. Therefore, when such two types of input energy data coexist, for example, high-energy data, that is, print dots Q2 and Q3 exist at the positions of the print dots q2 and q3 shown in FIG. In this case, the printing dot q1
However, printing using low energy data cannot be performed, and a printing result close to data on the high energy side is obtained. For example, what should be printed in red will be printed in black.

Therefore, it is necessary to provide a thermal head which does not affect the print output of low energy data in accordance with the presence or absence of such high energy print data near the print point. Therefore, the diode 30,
31 are connected as shown in FIG.

Thus, when print data exists in the print dots Q2 and Q3 in the high energy portion, the heating time of the thermal head by the low energy portion is controlled in accordance with the print data as described later.

The diode 30 connects the signal input circuit for the print dot Q2 in the high energy portion and the signal input circuit for the print dot q2 in the low energy portion. As a result, the same control as when print data exists in the print dot q2 in the low energy portion when print data exists in the print dot Q2 in the high energy portion is performed.

The diode 31 connects the signal input circuit for the print dot Q3 in the high energy portion and the signal input circuit for the print dot q3 in the low energy portion. As a result, the same control as when print data exists in the print dot q3 in the low energy portion when print data exists in the print dot Q3 in the high energy portion is performed.

The control operation will be described below, for example, when there is print data in q1 of the low energy part, there is no print data in q2 or q3 of the low energy part, and there is print data in Q2 or Q3 of the high energy part. Due to the nature of the print data, the print data is created so that the print data of the high energy portion and the print data of the low energy portion do not exist together in the same dot.

(12) When print data exists in the print dots q1 and Q2, in the print control range of the low energy portion shown in FIG. 10C, print data exists only in the corresponding print dot q1, and print is performed in q2 and q3. No data, FIG.
FIG. 10A shows a case where print data is present in the print dot Q2 in the high energy portion shown in FIG.
Where q1 = “1”, q2 = “0”, q3 = “0”,
Q2 = “1” and Q3 = “0”.

At this time, since q3 = "0", the NAND circuit 2
0 outputs “1”. However, in the NAND circuit 19, although q2 = "0", Q2 = "1" is input to the signal input circuit of q2 via the diode 30. Further, an inverter 23 is connected to the NAND circuit 19 as shown in FIG.
Since the inverted signal of the GATE C1 signal shown in FIG. 1 (B) is applied, the NAND circuit 19 outputs “0” only during the period t ₆ in FIG. 11, and outputs “1” in the other circuits.

Therefore, the AND circuit 6 is connected to the ST circuit shown in FIG.
Period T due to ROBE2 signal_TwoTo t₆Minus the remaining
Period (t₇+ T₈) Outputs “1” and outputs multiple inputs and times.
The path 4 and the OR circuit are also in this period (t₇+ T₈) Only "1"
Is output, FET1 is also turned on only during this period,
The heater of the thermal head connected to FET1 is set to (T _Two
-T₆) Heating control only for a period.

By shortening the heating time by the period t ₆ in this manner, it is possible to prevent the effect of heat accumulation in the print dot Q2 in the high energy portion with respect to the print dot q1.

(13) When print data exists in print dots q1 and Q3, in the print control range of the low energy portion shown in FIG. 10C, print data exists only in print dot q1, and print data exists in q2 and q3. No print data, Figure 1
FIG. 10 shows a case where print data is present in the print dot Q3 of the high energy portion shown in FIG.
In (A), q1 = “1”, q2 = “0”, q3 =
“0”, Q2 = “0”, and Q3 = “1”.

At this time, since q2 = “0”, the NAND circuit 19 outputs “1”. However, in the NAND circuit 20, although q3 = "0", Q3 = "1" is input to the signal input circuit of q3 via the diode 31.
Further, the output of the EOR circuit 21 is input to the NAND circuit 20. At this time, the EOR circuit 21 includes the inverter 2
3 is applied, and the inverted signal of the GATE C2 signal shown in FIG. 11B by the inverter 24 is applied, so that "1" and "1" of both signals are applied. 0 does not match the "period t ₇ only EOR circuit 21 shown in FIG. 11 outputs" 1 ", other periods outputs" 0 ". Therefore, the NAND circuit 20 operates in the period t ₇
Only "0" is output, and "1" is output during other periods.

Therefore, the AND circuit 6 operates as shown in FIG.
The remaining period (t ₆ + t ₈ ) obtained by subtracting the period t ₇ from the period T ₂ by the TROBE2 signal outputs “1”, and the multi-input AND circuit 4 and the OR circuit 2 also output “1” during this period (t ₆ + t ₈ ). since outputs 1 ', FET1 becomes oN only this period, the heating control of the heater of the thermal head connected to FET1 by (T ₂ -t ₇₎ period.

By shortening the heating period by the period t ₇ in this way, it is possible to prevent the effect of heat accumulation on the print dot Q 3 of the high energy portion with respect to the corresponding print dot q 1.

(14) When print data exists in the print dots q1, Q2, and Q3, in the print control range of the low energy portion shown in FIG. There is no print data in q3, and the print dot Q in the high energy portion shown in FIG.
2, when print data exists in Q3, q1 = "1", q2 = "0", q3 = "0", Q3 in FIG.
2 = “0” and Q3 = “0”.

At this time, in the NAND circuit 19, q2 = "0"
However, the diode 30 is connected to the signal input circuit of q2.
= “1” is input via the. Further, an inverted signal of the GATE C1 signal shown in FIG. 11B is applied to the NAND circuit 19 by the inverter 23.
The NAND circuit 19 outputs “0” only during the period t ₆ in 1 and outputs “1” in other cases.

In the NAND circuit 20, although q3 = "0", Q3 = "1" is input to the signal input circuit of q3 via the diode 31. In the NAND circuit 20,
The output of the EOR circuit 21 is input.
The OR circuit 21 outputs the inverted signal of the GATE C1 signal and the GAT signal.
"1" and the inverted signal of the E C2 signal, does not match the "0", EOR circuit 21 only for the period t ₇ shown in FIG. 11 is "1"
And outputs “0” in other periods. Therefore, the NAND circuit 20 outputs “0” during the period t ₇ in FIG. 11, and outputs “1” in the other cases.

Therefore, the AND circuit 6 operates as shown in FIG.
The period from the period T ₂ by TROBE2 signal (t ₆ +
Since “1” is output for the remaining period t ₈ after subtracting t ₇ ), the FET 1 is also turned on for the period t ₈ = T ₂ − (t ₆ + t ₇ ), and the heater of the thermal head connected to the FET 1 is turned on. heating control only for the period t _8.

In this way, by shortening the heating period by the period (t ₆ + t ₇ ), it is possible to prevent the effect of heat accumulation on the printing dots Q2 and Q3 in the high energy portion with respect to the printing dot q1.

(15) When print data exists in the print dots q1, q2, and Q3, the print dot q1 in the print control range of the low energy portion shown in FIG.
FIG. 10B shows a case where print data exists in print dot q2 and print data does not exist in q3, and print data exists in print dot Q3 in the high energy portion shown in FIG. 10B but no print data exists in Q2. In 10 (A), q1 =
“1”, q2 = “1”, q3 = “0”, Q2 = “0”,
Q3 = “1”.

In this case, the same control as in the above (14) is performed, and the FET 1 is turned on for the period t ₈ = T ₂ − (t ₆ + t ₇ ).

In this way, by shortening the heating time by the period (t ₆ + t ₇ ), the heat storage effect of not only the print dot q2 of the low energy portion but also the print dot Q3 of the high energy portion with respect to the corresponding print dot q1 is prevented. can do.

(16) When print data exists in the print dots q1, q3, and Q2, the corresponding print dot q1 in the print control range of the low energy portion shown in FIG.
FIG. 10B shows a case where print data exists in the print dot q3 and no print data exists in the print dot q2, and print data exists in the print dot Q2 in the high energy portion shown in FIG. 10B but no print data exists in the print dot Q3. In 10 (A), q1 =
“1”, q2 = “0”, q3 = “1”, Q2 = “1”,
Q3 = “0”.

In this case, the same control as in the above (14) is performed, and the FET 1 is turned on only during the period t ₈ = T ₂ − (t ₆ + t ₇ ).

In this way, by shortening the heating time by the period (t ₆ + t ₇ ), the heat storage effect of not only the print dot q3 of the low energy portion but also the print dot Q2 of the high energy portion with respect to the corresponding print dot q1 is prevented. can do.

Next, a second control circuit per dot of the thermal head in the above-mentioned Japanese Patent Application No. 10-12320 will be described with reference to FIGS. FIG. 12 shows an example in which forward print data and adjacent data of a high energy portion are added to a control range, and FIG. 13 is an explanatory diagram of control signals applied to this control circuit.

In the control circuit shown in FIG. 12A, in the unique control in the high-energy section, as shown in FIG. Previous print dot Q at
2 and the left and right print dots LQ2 and RQ2, and the print control range of the previous print dot Q3 in the previous two print lines.

In the unique control in the low energy section, as shown in FIG.
When the above-mentioned line is set as the corresponding print line, the print control range of the previous print dot q2 in the preceding one print line and the previous print dot q3 in the preceding two print lines are further included.

In this example, as shown in FIG. 12C, the influence range of the high energy portion on the corresponding print dot q1 in the low energy portion is determined by the print dots Q2 and Q3 and the LQ2 of the adjacent print dot of the previous print line. RQL2
It is determined.

Therefore, as shown in FIG. 12A, diodes 30, 31, 32, and 33, an inverter 25, a NAND circuit 26, an EOR circuit 27, and the like are provided.

As shown in FIG. 13B, the GATE C3 signal falls at the same time as the STROBE2 signal and rises after a period (t ₆ + t ₇ + t ₈ ). Of course, (t ₆ + t ₇ + t ₈ ) can be appropriately set according to the characteristics of the paper.

The diodes 30 and 31 are the same as those shown in FIG.
Is similar to the control circuit shown in FIG.

The diode 32 is for controlling the influence of print data in the print dot LQ2 in the high energy portion when the print data is present. The diode 32 has a signal input circuit for the print dot LQ2 in the high energy portion and an input to the NAND circuit 26. It connects to a circuit.

The diode 33 is for controlling the influence of print data on the print dot RQ2 in the high energy portion when the print data is present. The diode 33 has a signal input circuit for the print dot RQ2 in the high energy portion and an input for the NAND circuit 26. It connects to a circuit.

The other input circuit of the NAND circuit 26 has EOR
The output of the circuit 27 is input.

The EOR circuit 27 receives an inverted signal of the GATE C2 signal and an inverted signal of the GATE C3 signal.

FIG. 12A shows the same operation as that of the control circuit shown in FIG. 10A for controlling the high energy portion alone. For the control of the low energy part alone, LQ
Since both RQ2 and RQ2 are "0", the NAND circuit 26 outputs "1" to the multi-input AND circuit 6-0. Otherwise, the operation is the same as that of the control circuit shown in FIG. Therefore, these single operations are omitted for simplification of description.

A typical control for the corresponding print dot q1 in the low energy portion when print data exists in LQ2 and RQ2 in FIG. 12C will be described below.

(1) When print data exists in the print dots q1 and LQ2, in the print control range of the low energy portion shown in FIG. 12D, print data exists only in the corresponding print dot q1, and print is performed in q2 and q3. No data, FIG.
In the case where print data is present in the print dot LQ2 of the high energy portion shown in (C) and no print data is present in Q2, Q3, and RQ2, q1 = “1” and q2 =
“0”, q3 = “0”, Q2 = “0”, Q3 = “0”,
LQ2 = “1” and RQ2 = “0”.

At this time, since q2 = "0" and Q2 = "0", the NAND circuit 19 outputs "1", and q3 = "0" and Q3
Since 3 = “0”, the NAND circuit 20 outputs “1”.

Since LQ2 = "1", the NAND circuit 26
"1" is applied to one input circuit, and the output of the EOR circuit 27 is input to the other input circuit. Then E
The OR circuit 27 includes an inverter 24, as shown in FIG.
And the inverted signal of the GATE C2 signal shown in FIG.
According to 5, since the inverted signal of GATE C3 signal shown in FIG. 13 (B) is applied, "1" of the two signals do not match the "0", only the EOR circuit period t ₈ shown in FIG. 13 (B) 27 outputs "1", and outputs "0" in other periods. Therefore the NAND circuit 26 outputs "0" only for the period t _8, other periods outputs "1".

Therefore, the multi-input AND circuit 6-0 has the structure shown in FIG.
Period t ₈ from the period T ₂ by STROBE2 signal shown in
During the remaining period (t ₆ + t ₇ + t ₉ ), “1” is output, and the multi-input AND circuit 4 and the OR circuit 2 also output “1” during this period (t ₆ + t ₇ + t ₉ ) = T ₂ −t _8. 1 "is output, so that FET1 is also turned on only during this period, and FET1 is turned on.
(T ₂ −t)
₈ ) Control heating only for a period.

[0116] By shortening the only heating time period t ₈ in this manner, it is possible to prevent heat accumulation effect in the print dot LQ2 in the high energy portion to the corresponding print dot q1.

(2) When print data exists in the print dots q1 and RQ2, in the print control range of the low energy portion shown in FIG. 12D, print data exists only in the corresponding print dot q1, and print data exists in q2 and q3. No print data, Figure 1
In the case where print data is present in the print dot RQ2 of the high energy portion shown in FIG. 2C and no print data is present in Q2, Q3, and LQ2, in FIG. 12A, q1 = “1” and q2 =
“0”, q3 = “0”, Q2 = “0”, Q3 = “0”,
LQ2 = "0" and RQ2 = "1".

At this time, since q2 = "0" and Q2 = "0", the NAND circuit 19 outputs "1" and q3 = "0" and Q3
Since 3 = “0”, the NAND circuit 20 outputs “1”.

Since RQ2 = “1”, the NAND circuit 26
"1" is applied to one input circuit, and the output of the EOR circuit 27 is input to the other input circuit. Therefore as if print data to the print dots q1 and LQ2 of the (1) is present, the period t ₈ only EOR circuit 27 shown in FIG. 13 (B) outputs a "1", the other period "0 Is output to control the heating of the heater of the thermal head connected to the FET _{1 for a} period (T ₁ −t ₈ ).

Thus, by shortening the heating time by the period t _8, it is possible to prevent the effect of heat accumulation on the print dot RQ 2 in the high energy portion with respect to the print dot q 1.

(3) Print dot q1, LQ2, RQ2
When print data exists in the print control range of the low energy portion shown in FIG.
12 has no print data, q2 and q3 have no print data, and high-energy portion print dots LQ2 and RQ2 have print data and Q2 and Q3 have no print data as shown in FIG. In (A), q1 =
“1”, q2 = “0”, q3 = “0”, Q2 = “0”,
Q3 = “0”, LQ2 = “1”, and LQ2 = “1”.

At this time, as in the case where the print data exists in the print dots q1 and LQ2 in the above (1), FIG.
Only EOR circuit 27 period t ₈ shown in (B) outputs a "1", the other period, the outputs "0", only heaters (T ₂ -t ₈₎ duration of the thermal head connected to FET1 Control heating.

[0123] By shortening the way by the period t ₈ the heating time, it is possible to prevent the heat accumulation effect in the print dot LQ2, RQ2 high energy portion to the corresponding print dot q1.

When print dots exist in LQ2 and RQ2, the same control as when print dots exist in either LQ2 or RQ2 is performed for the following reason.

That is, in such multi-color printing, it is necessary to clearly output the boundary of each color, and there are few cases where such bits are present intermittently. This is because there is little requirement for a complicated control circuit necessary for the operation.

(4) When print data exists in the print dots q1, Q2, and LQ2, the corresponding print dot q1 is set in the print control range of the low energy portion shown in FIG.
Has print data only, and has no print data in q2 and q3. The print dot Q in the high energy portion shown in FIG.
2, when there is print data in LQ2 and no print data in Q3 and RQ2, q1 = “1” in FIG.
2 = “0”, q3 = “0”, Q2 = “1”, LQ2 =
“1”, Q3 = “0”, and RQ2 = “0”.

At this time, since q3 = "0" and Q3 = "0", the NAND circuit 20 outputs "1". However, in the NAND circuit 19, although q2 = "0", Q2 = "1" is input to the signal input circuit of q2 via the diode 30. Further, since the inverted signal of the GATE C1 signal shown in FIG. 13B is applied to the NAND circuit 19 by the inverter 23, the period t in FIG.
_The NAND circuit 19 outputs "0" only during the period ₆ , and outputs "1" for the others.

Since LQ2 = “1”, the diode 3
2 to one input circuit of the NAND circuit 26 via "1"
And the output of the EOR circuit 27 is input to the other input circuit. At this time, the inverted signal of GATE C2 shown in FIG. 13B by the inverter 24 and the G signal shown in FIG.
Since the inverted signal of the ATE C3 signal is applied, the EOR circuit 27 outputs “1” only during a period t ₈ shown in FIG. During this period, “0” is output. Therefore the NAND circuit 26 outputs "0" only for the period t _8, other periods outputs "1".

Therefore, the multi-input AND circuit 6-0 has a structure shown in FIG.
Period T due to STROBE2 signal shown in (B)_TwoBefore
Writing period t₆And t₈After subtracting (t₇+ T₉) Is
Outputs “1”, and the multi-input AND circuit 4 and the OR circuit 2
This period (t₇+ T₉) = T _Two− (T₆+ T₈Only)
Since "1" is output, FET1 is also ON only during this period.
The heater of the thermal head connected to FET1
This [T_Two− (T₆+ T ₈)] The heating is controlled only during the period.

In this way, by shortening the heating time by the period (t ₆ + t ₈ ), it is possible to prevent the effect of heat accumulation on the printing dots Q2 and LQ2 in the high energy portion with respect to the printing dot q1.

(5) When print data exists in the print dots q1, Q3, and LQ2, the corresponding print dot q1 is set in the print control range of the low energy portion shown in FIG.
Has print data only, and has no print data in q2 and q3. The print dot Q in the high energy portion shown in FIG.
3, when there is print data in LQ2 and no print data in Q2 and RQ2, q1 = “1” in FIG.
2 = “0”, q3 = “0”, Q2 = “0”, Q3 =
“1”, LQ2 = “1”, and RQ2 = “0”.

At this time, since q2 = "0" and Q2 = "0", the NAND circuit 19 outputs "1". However, in the NAND circuit 20, although q3 = "0", Q3 = "1" is input to the signal input circuit of q3 via the diode 31. Further, the output of the EOR circuit 21 is input to the other input circuit of the NAND circuit 20. At this time, EOR
Since the inverted signal of the GATE C1 signal shown in FIG. 13B by the inverter 23 and the inverted signal of the GATE C2 signal shown in FIG. Does not match, FIG.
The EOR circuit 21 outputs “1” only during the period t ₇ shown in FIG. 7B, and outputs “0” during other periods. Therefore the NAND circuit 20 outputs "0" only for the period t _7, other periods outputs "1".

[0133] Further LQ2 = only for the period t ₈ the NAND circuit 26, as shown when the print data to the print dots q1 and LQ2 of the (1) for the "1" is present and outputs "0", the other During the period, “1” is output.

Therefore, the multi-input AND circuit 6-0 has the structure shown in FIG.
Period T due to STROBE2 signal shown in (B)_TwoBefore
Writing period t₇And t₈After subtracting (t₆+ T₉) Is
Outputs “1”, and the multi-input AND circuit 4 and the OR circuit 2
This period (t₆+ T₉) = T _Two− (T₇+ T₈Only)
Since "1" is output, FET1 is also ON only during this period.
The heater of the thermal head connected to FET1
This [T_Two− (T₇+ T ₈)] The heating is controlled only during the period.

In this way, by shortening the heating time by the period (t ₇ + t ₈ ), it is possible to prevent the effect of heat storage on the printing dots Q3 and LQ2 in the high energy portion with respect to the printing dot q1.

In other cases, the control circuit shown in FIG. 12A can prevent the adverse effect of the print dots in the high energy portion.

As described above, high-energy printing control and low-energy printing control can be performed very accurately, so that accurate printing can be performed even when data of two colors are mixed.

For example, as shown in FIG. 9A, when a black character area B and a red character area R are formed into blocks on a sheet, the black area and the red area are also controlled by the control circuits shown in FIGS. It can be printed clearly. However, in the case where black characters are printed on a red background, that is, when the red region R and the black region B are mixed, a low-energy portion adjacent to the high-energy portion print and a low-energy portion before and after the low-energy portion print exist. The printing of the high-energy part in the high-energy part prints a color close to that of the high-energy part, thereby improving the disadvantage of inaccurate characters and patterns. Since the adverse effect of the energy data on the low energy data can be effectively controlled, clear and accurate printing can be performed.

Some print media, such as Aladdin Card (registered trademark) manufactured by Tokyo Magnetic Printing Co., Ltd., can print when high energy is applied by a thermal head, but change to another color when low energy is applied. There are rewritable media that can erase characters and the like printed with high energy and write character figures and the like again with high energy printing.

For such a medium, FIGS.
2 can be used. In this case, the STROBE1 signal is set so as to add high energy for printing, and the STROBE2 signal is set so as to give low energy for erasing printed characters and the like.
In this case, q1, q2, and q3 are print erasure data for performing print erasure control. In this medium, since the range of the low energy for erasing is very severe, not only the magnitude of the STROBE2 signal but also the thermal history control based on the presence or absence of the q2 and q3, that is, the heating control based on the print erasure data q2 and q3. In addition, it is preferable to perform energy adjustment.

Thus, the present invention can be used for a thermal head for a rewritable medium.

FIGS. 14 and 15 illustrate a logic table of the control circuit of FIG. In FIG. 12, since the diode 20 and the q2 input to the NAND circuit 19 have an OR relationship,
In FIG. 14A, these are equivalently shown by an OR circuit 115. The output protection circuit 13 in FIG.
(A) is omitted. Thus, FIG.
(A) enables equivalent display.

In FIG. 14A, 100 is F
ET and 101 are OR circuits, 102 and 103 are multi-input AND circuits, 104 is an AND circuit, 105 is a multi-input AND circuit, 106 and 107 are AND circuits, 108, 109, and 1
10, 111, 112, 113 and 114 are NAND circuits,
115, 116, 117 are OR circuits, 118, 119,
120, 121 are EOR circuits, 122, 123, 12
4, 125, 126, 127, 128, 129, 130
Is an inverter.

FIG. 14B is a view similar to FIG.
2B, a unique control portion of the print control range (high energy portion), a portion of the print control range (low energy portion) affected by high energy shown in FIG. 12C, and a print control shown in FIG. 12D. It is a collection of unique control parts of the range (low energy part). Then, Q1 in FIG.
Q2, Q3, LQ2, RQ2 are latch data, and q1, q2, q3 are also latch data.

In the circuit shown in FIG. 14A, when the thermal head has, for example, a 64-dot structure, 64 such thermal heads are prepared. The terminal DOn, the GQn, GAn, GBn of the AND circuit 104, and multiple inputs are provided. G of AND circuit 105
n in qn indicates that there are a plurality of such circuits.

As shown in FIG. 15A, the output of the terminal DOn is as follows: STROBE q is "0", latch data Q1 is "0", q1 is "1", and the multi-input AND circuit 105 is an output in the circuit. If the output of (Gqn) is “1”, the STROBE Q is either “1” or “0”, and the output of the AND circuit 104 (GQn) is either “1” or “0”. Indicates that it is on. Note that * is either “0” or “1”. The output of the terminal DOn is such that STROBE Q is “0”, STR
OBE q is “1”, latch data Q1 is “0”, q1
Is “0”, which indicates that the output of the AND circuit 104 (GQn) and the multi-input AND circuit 105 (Gqn) is OFF regardless of whether it is “1” or “0”. The output of the other terminal DOn is STROB shown in FIG.
EQ, STROBE q, Q1, q1, GQn, Gq
ON or OFF according to the state of "1" or "0" of n
Becomes

The AND circuit 104 (GQn)
As shown in FIG. 15B, "1" or "0" is output according to the state of "1" or "0" of the AND circuit 106 (GAn) and the AND circuit 107 (GBn), which are outputs in the circuit. As shown in FIG. 15C, the AND circuit 106 (GAn) has inputs GATE A1 and GATE A1.
A2, "1" or "0" is output according to the state of "1" or "0" of latch data Q2 or LQ2.

The AND circuit 107 (GBn) corresponds to FIG.
5 (D), inputs GATEB1, GATE B
2. It outputs "1" or "0" according to the state of "1" or "0" of the latch data Q3 or RQ2.

The multi-input AND circuit 105 (Gq
n) is the input GATE C as shown in FIG.
1, GATE C2, GATE C3, latch data Q
2 or q2, Q3 or q3, and outputs “1” or “0” according to the state of “1” or “0” of LQ2 or RQ2.

[0150]

By the way, in the conventional thermal heads shown in FIGS. 10 and 12, the magnitude of the printing energy is set by the magnitude of the application time of the current flowing to the heating terminal. That is, it is determined by the magnitude of STROBE1 and STROBE2 in FIGS.
The current value, that is, the unit power was the same.

Therefore, in order to reduce the printing energy, even if the unit power is fixed to the case where the printing energy is large and the application time is reduced, there are some papers whose coloring is insufficient depending on the properties of the paper. In addition, when used for rewritable paper for erasing characters and the like printed with high energy by applying a low-energy amount of heat by making the application time shorter than that of the thermal head, erasing may not be performed sufficiently.

Accordingly, it is an object of the present invention to provide a thermal head which can reduce the printing energy even when the application time is longer than in the prior art.

[0153]

FIG. 1 shows the principle of the present invention.
This will be described with reference to FIG. In FIG. 1A, r ₀ is a heating resistor, and r ₁ is an additional resistor connected in series to adjust the amount of heat generated by the heating resistor r _0.
The current flowing through the heat generating resistor r ₀ is controlled by controlling the on / off of the resistor 2.

In FIG. 1A, 3 to 5 are multi-input AND circuits, 6 is an AND circuit, 7 to 10 are NAND circuits,
1 and 12 are EOR (exclusive sieve or) circuits, 13
Is an output protection circuit, 14 to 18 are inverters, 19 and 20
Is a NAND circuit, 21 is an EOR circuit, and 22 to 24 are inverters. And 30 and 31 are diodes,
A connection circuit for connecting the signals Q2 and q2 and the signals Q3 and q3 shown in FIG.

The above object of the present invention can be achieved by the following constitutions.

(1) A plurality of heating elements r ₀ that generate heat with different energies, an additional resistor r ₁ connected to the heating elements r ₀ , and the heating elements r ₀ are controlled to an operating state or a non-operating state. A first switching means 1; a second switching means 2 for controlling the heating element r ₀ and the additional resistance r ₁ to an operating state or a non-operating state; and the first switching means 1
The first strobe signal input means 3 for controlling the heating element r ₀ to generate heat corresponding to the first energy, and the heating element r ₀ generates heat corresponding to the second energy to the second switching means 2. The second strobe signal input means 4 for controlling the printing and the printing control using the first energy, and the heating element r ₀ based on the first strobe signal is determined according to the presence or absence of print data in a print control range of the corresponding print data. First heat generation time control means 5 for controlling the heat generation time;
A second heat generation time control means for performing printing control using the second energy and controlling the heating time of the heating element r ₀ based on the second strobe signal in accordance with the presence or absence of print data in a print control range of the corresponding print data. 4 is provided.

(2) In the above (1), the heating element r
₀ and characterized by being constituted by a thin film resistor formed said additional resistor r ₁ on the same insulating substrate.

As a result, the following effects can be obtained.

(1) An additional resistor is connected to the heating element, and only the heating element is operated with high energy by the first switching means 1 and the second switching means 2, or the heating element and the additional resistance are connected in series to reduce the resistance. It is possible to selectively control whether the thermal head is put into the operating state by using energy, so that not only can the thermal head be controlled in the high energy state and the low energy state, but also the two-power type thermal head can be operated in the low energy state for a long time. can do.

(2) Since the heating element and the additional resistor are formed of the same thin film resistor, it is possible to provide a small, high-resolution two-power type thermal head.

[0161]

FIG. 1 shows a first embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 is a block diagram of a control circuit per dot of the thermal head according to the first embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of FIG. 1A, and FIG. FIG. 4 is a configuration diagram of a head portion, FIG. 4 is a comparative explanatory diagram of a conventional example and the present invention, and FIG. 5 is an embodiment of the present invention.

In the present invention, as shown in FIG. 1A, an additional resistor r ₁ is connected in series with the heat generating resistor r ₀ of the thermal head, and as shown by T ₁ in FIG. in the case of use, turn on the FET1, FET2 by applying a terminal voltage V to only heating resistor r ₀ is controlled to turn off the heat generation control this. Further, as shown by T ₂ in FIG.
Turn on FET1 when used with a low printing energy side, FET2 a heating resistor r ₀ is controlled to turn off the additional resistor r ₁ connected in series, the heating resistor r by applying a terminal voltage V1 to the series circuit ₀ is controlled for heat generation.

Thus, FET1 is turned on and FET2 is turned on.
It is turned off, and as shown in FIG.₀of
If the terminal voltage V is applied only to the heating resistor r₀Electricity generated
Force W ₀Is as shown in the following equation (1).

W ₀ = V ² / r ₀ (1) Further, the FET 1 is turned off and the FET 2 is turned on, and FIG.
As shown in (C), when the terminal voltage V is applied to the series connection circuit of the heating resistors r ₀ and r ₁ , the power W ₁ generated in the heating resistor r ₀ is expressed by the following equation (2).

W ₁ = (V × r ₀ / (r ₀ + r ₁ )) ² / r ₀ (2) As described above, according to the equation (2), W ₁ becomes W ₀ due to the presence of r _1.
It can be seen that the power is lower than the power.

As proposed in Japanese Patent Application No. 10-12320, as shown in FIG. 4A, the power W ₀ applied to the thermal paper per unit time from the heat generation resistance, that is, the unit power is in a high energy state. But even in the low energy state,
By setting the heat generation time t ₂ in the high energy state longer than the heat generation time t ₁ in the low energy state, the energy applied to the thermal paper in the high energy state becomes W ₀ × t ₂ , The difference in heat generation time t ₂ than the applied energy W ₀ × t ₁ in the energy state.
−t ₁ .

On the other hand, in the present invention, as shown in FIG.
Apply heat to the thermal paper in unit time
Power is in the high energy state, W₀But low energy
W for ruggy state₁And W₀Lower than. did
Therefore, as shown in FIG.
t_TwoApplying to thermal paper in high energy state
Energy is W₀× t_TwoIn a low energy state
Applied energy W ₁× t_TwoLarger than. this
By adjusting the unit heating value in the heating resistor
Lower energy state. FIG. 4
In the case of (B), the heat generation time in the high energy state and
When the heat generation time in the low energy state is the same,
However, it is not necessary that they be the same.
Both can be appropriately set depending on the properties of the paper.

FIG. 1A shows a first embodiment of the present invention.
Explain the state. In FIG. 1A, reference numerals 1 and 2 denote FETs,
3, 4, and 5 are multi-input AND circuits, 6 is an AND circuit, 7 to
10 is a NAND circuit, 11 and 12 are EOR (excursion
Circuit, 13 is an output protection circuit, and 14 to 18 are
Inverters, 19 and 20 are NAND circuits, 21 is EOR times
Roads, 22-24 are inverters, 30 and 31 are diodes
Do, r₀Is the heating resistance, r ₁Is an additional resistance.

When the IC constituting the thermal head operates normally, the output protection circuit 13 operates as a multi-input AND circuit 3 or 4.
Is output as "1".

The signals indicating the presence or absence of the print dots Q1, Q2, Q3, LQ2, and RQ2 in the high energy portion shown in FIG. 1B are the signals Q1, Q2, Q3, and Q3 shown in FIG.
Signals that are input as LQ2 and RQ2 and that indicate the presence or absence of the print dots q1, q2, and q3 in the low-energy portion illustrated in FIG. 1C are input as signals q1, q2, and q3 illustrated in FIG. .

Then, strobe signal STROBE1
Is for heating the thermal head as a high energy portion to print black on paper, and the strobe signal STROBE2 is for heating the thermal head as a low energy portion and printing red, for example, on paper. .

When the corresponding print Q1 shown in FIG. 1B is printed, if there is no print data in Q2, Q3, LQ2, and RQ2, these are "0", and the NAND circuits 7-1
Since 0 outputs “1”, both the multi-input AND circuit 5 and the multi-input AND circuit 3 output “1”,
FET1 is thereby turned on for a time T ₁ as defined by the strobe signal STROBE1, for heating the heating resistor r ₀ of the thermal head.

However, if print data exists in at least one of Q2, Q3, LQ2, and RQ2, the gate signals A1,
B1, A2, only being controlled time based on B2 output time of multi-input AND "1" of the the circuit 5 is output is "0" strobe signal STROBE1 by multi-input AND circuit 3 is shorter than the T ₁ In such a manner that the heating energy of the thermal head to the thermal paper in the strobe signal STROBE1 is controlled to be equal.

When printing the corresponding print q1 shown in FIG. 1C, if there is no print data in q2 and q3, these are "0", and both NAND circuits 19 and 20 output "1". Therefore, the AND circuit 6 and the multi-input AND circuit 4 both output "1", and the FET 2 thereby operates for the time T determined by the strobe signal STROBE2.
₂ only FET2 turn on, turn additional resistor r ₁ and the heating resistor r ₀ is the heating resistor r ₀ in a state of being connected in series and heated.

However, if there is print data in at least one of q2 and q3, taking into account the heat storage effect, and as will be described later, the AND circuit 6 is controlled by the gate signals C1 and C2 corresponding to the print data. controlled to be shorter than the output time of the "1" in the multi-input aND circuit 4 according to the strobe signal STROBE2 "0" is outputted by the T ₂ from the heating of the heat sensitive paper of the thermal head in the strobe signal STROBE2 Is controlled so that the energies are equal.

The various control signals shown in FIG. 2 are output from a control signal output circuit (not shown), and are all output at the same cycle S.

The control signals shown in FIG. 2A are various control signals for controlling the thermal head in a high energy state, and the control signals shown in FIG. 2B are for controlling the thermal head in a low energy state. Are various control signals.

[0178] STROBE1 signal, the printing control range shown in FIG. 1 (B), when printing only the appropriate print dot Q1 dot is present, a thermal head connected thereto to turn on period T ₁ only FET1 is intended to heating control only for the period T _1, as shown in FIG. 2 (a), only for the period T ₁ is at a low level.

[0179] GATE A1 signal, falls at the same time as the STROBE1 signal, in which rises after a period t _1.

The GATE A2 signal falls at the same time as the STROBE1 signal, and rises after a period (t ₁ + t ₂ ).

The GATE B1 signal is a STROBE1 signal.
Period (t₁+ T _Two+ T_Three+ T_Four)rear
And then the period t_FiveLater, STROBE1
It rises simultaneously with the issue.

The GATE B2 signal is a STROBE1 signal.
Period (t₁+ T _Two+ T_Three) Fall after
And then the period (t_Four+ T_Five) Later, STROBE
It rises at the same time as one signal.

[0183] Further STROBE2 signal, the printing control range shown in FIG. 1 (C), if there is a printed dot only the appropriate print dot q1, thermal head connected thereto turns on the period T ₂ by FET1 For period T ₂
Only the heating is controlled, and as shown in FIG.
STROBE1 signal falls simultaneously, by the period T ₂ is at a low level.

[0184] GATE C1 signal, falls at the same time as the STROBE2 signal, in which rises after a period t _6.

The GATE C2 signal falls at the same time as the STROBE2 signal, and rises after a period (t ₆ + t ₇ ).

These T ₁ , T ₂ , t _{1 to} t ₈ are:
It can be set appropriately according to the characteristics of the paper.

First, based on FIG. 1 and FIG. 2, with regard to the thermal history control, the print control range shown in FIG. 1 (B) and FIG.
In other words, the printing dots Q1 to Q
3, print data exists for LQ2 and RQ2 as described below, and print dots q1 to q
Regarding No. 3, a case where print data exists as described below will be described.

Here, when Q1 is the corresponding print dot,
Q2 indicates a print dot immediately before the one line, and Q3 indicates a print dot immediately before the two lines. LQ2 indicates the left print dot one line before, and RQ2 indicates the right print dot one line before.

When q1 is the corresponding print dot,
q2 indicates a print dot immediately before the one line, and q3 indicates 2
Indicates the print dot immediately before the line.

(1) When print data exists only in print dot Q1, in the print control range shown in FIG. 1B, print data exists only in print dot Q1 and Q
When print data does not exist in 2, Q3, LQ2, and RQ2, Q1 = "1", Q2 = "0", and Q3 in FIG.
= "0", LQ2 = "0", RQ2 = "0".

Since each of the NAND circuits 7 to 10 outputs "1" according to each "0", the multi-input AND circuit 5 outputs "1". At this time, if the thermal head is normal, "1" is output from the output protection circuit 13, and Q1 = "1".
Since the STROBE1 signal as shown in FIG.
“1” is output from the multi-input AND circuit 3 only during a period T ₁ shown in FIG. At this time, since q1 = “0”, the multi-input AND circuit 4 outputs “0”.

As described above, since "1" output from the multi-input AND circuit 3 is input to the FET 1, the OR circuit 2 eventually has print data in Q1, Q2, Q3, L
Q2, if there is no print data to RQ2, which was turned on by applying only the period T ₁ to "1" to the FET1, FET1
Period heating resistor r ₀ of the connected thermal head T ₁
Only heat generation control.

(2) When print data exists in the print dots Q1 and Q2, and when print data exists in the print dot Q1 and the print dot Q2 one line before the print data, FIG.
In (A), “1” is applied to each of Q1 and Q2,
3 = “0”, LQ2 = “0”, and RQ2 = “0” are applied. As a result, the NAND circuits 8 to 10 each become “1”.
Is output.

At this time, the NAND circuit 7 includes the inverter 1
5 inverts the GATE A1 signal shown in FIG.
Since the signal and Q2 = "1" are applied, the period in FIG.
Interval t ₁The NAND circuit 7 outputs "0" only during
"1" is output. Therefore, the multi-input AND circuit 5 is configured as shown in FIG.
Period T shown in₁To period t₁After subtracting (t_Two
+ T_Three+ T_Four+ T_Five) Outputs “1” and FET1
Is turned on only during the period of
Heating resistance of head r₀To (T₁-T₁) Heating only for a period
I will.

(3) When print data exists in the print dots Q1 and LQ2, and when print data exists in the print dot L1 adjacent to the print dot Q1 and the adjacent left front, the print data shown in FIG.
"1" is applied to each of Q1 and LQ2 of (A),
2 = “0”, Q3 = “0”, and RQ2 = “0” are applied. As a result, the NAND circuit 7 and the NAND circuits 9 and 10 each output "1".

At this time, LQ2 =
“1” and the output of the EOR circuit 11 are input. EO
The R circuit 11 outputs an inverted signal of the GATE A1 signal shown in FIG.
At night, since the inverted signal of GATE A2 signal shown in FIG. 2 (A) is applied only during the period t ₂ shown in FIG. 2 EOR
The circuit 11 outputs “1”, and outputs “0” in other periods. Therefore the NAND circuit 8 outputs only period t ₂ "0", other periods outputs "1".

Accordingly, the multi-input AND circuit 3 is shown in FIG.
Period T₁To period t_TwoAfter subtracting (t₁+ T_Three
+ T_Four+ T_Five) Outputs “1”, and FET1
Only the thermal head connected to FET1
Heating resistance r₀To (T₁-T _Two) Heat generation control only for a period
You.

(4) When print data exists in the print dots Q1 and RQ2, and when print data exists in the print dot RQ2 adjacent to the print dot Q1 and the right immediately before the print dot Q1, the print data shown in FIG.
“A” is applied to each of Q1 and RQ2 in FIG.
2 = “0”, Q3 = “0”, LQ2 = “0” are applied. Thereby, the NAND circuits 7 to 9 each output "1".

At this time, RQ2 =
“1” and the output of the EOR circuit 12 are input. EO
The R circuit 12 outputs an inverted signal of the GATE B1 signal shown in FIG.
2 is applied, the EOR circuit 12 outputs “1” for the period t ₄ shown in FIG. 2 and outputs “0” for the other periods. .
Therefore the NAND circuit 10 outputs only the period t ₄ "0", other periods outputs "1".

Therefore, the multi-input AND circuit 3 is shown in FIG.
Period T₁To period t_FourAfter subtracting (t₁+ T_Two
+ T_Three+ T_Five) Outputs “1”, and FET1
Only the thermal head connected to FET1
Heating resistance r₀To (T₁-T _Four) Heat generation control only for a period
You.

(5) When print data exists in the print dots Q1 and Q3, and when print data exists in the print dot Q1 and the print dot Q3 two dots before the print data, FIG.
“1” is applied to each of Q1 and Q3 in FIG.
= “0”, LQ2 = “0”, and RQ2 = “0”. Thus, the NAND circuits 7, 8 and 10 each output "1".

At this time, Q3 = “1” in the NAND circuit 9
And GATE shown in FIG.
Since the inverted signal of the B1 signal is applied, FIG.
Only for the period t ₅ shown in the NAND circuit 9 outputs "0", other periods outputs "1".

Therefore, the multi-input AND circuit 3 shown in FIG.
Period T₁To period t_FiveAfter subtracting (t₁+ T_Two
+ T_Three+ T_Four) Outputs “1”, and FET1
Only the thermal head connected to FET1
Heating resistance r₀To (T₁-T _Five) Heat generation control only for a period
You.

(6) When print data exists in the print dots Q1, Q2, and Q3, and when print data exists in the print dot Q1, the print dot Q2 one dot before the print dot Q2, and the print dot Q3 two dots before the print dot Q1 , Q in FIG. 1 (A)
“1” is applied to each of 1, Q2, and Q3, and LQ2 =
“0” and RQ2 = “0” are applied. As a result, the NAND circuits 8 and 10 each output "1".

At this time, Q2 = “1” is applied to the NAND circuit 7.
And GATE shown in FIG.
Since A1 signal inversion signal and is applied, the NAND circuit 7 only during the period t ₁ in Figure 2 outputs "0", other periods outputs "1". The NAND circuit 9 has Q3
= "1", according to the inverter 17, since the inverted signal of GATE B1 signals shown in FIG. 2 (A) is applied, the NAND circuit 9 only for the period t ₅ shown in FIG. 2 outputs "0",
In other periods, “1” is output.

Accordingly, the multi-input AND circuit 3 operates by subtracting the periods t ₁ and t ₅ from the period T ₁ shown in FIG.
₂ + t ₃ + t ₄ ) outputs “1”, FET 1 is also turned on only during this period, and the heating resistance r ₀ of the thermal head connected to FET _{1 is} controlled to generate heat for (T ₁ −t ₁ −t ₅ ). .

(7) Print dots Q1, Q2, Q3, L
When print data exists in a plurality of print dots among Q2 and RQ3, the corresponding print dot Q1 and print dot Q
A plurality of print dots among 2, Q3, LQ2, RQ2,
For example, when print data exists in Q2 and LQ2,
Since 3 = “0” and RQ2 = “0”, the NAND circuits 9 and 10
Output "1".

At this time, as shown in the above (2), the NAND circuit 7 uses the inverter 15 to generate the G signal shown in FIG.
Since ATE A1 signal and Q2 = "1" is applied, the NAND circuit only during the period t ₁ in FIG. 2 7 outputs "0".

The output of the EOR circuit 11 and LQ2 = "1" are input to the NAND circuit 8, as shown in the above (3). Since the inverted signal of the GATE A1 signal shown in FIG. 2A by the inverter 15 and the inverted signal of the GATE A2 signal shown in FIG. 2A by the inverter 16 are applied to the EOR circuit 11, FIG. The EOR circuit 11 outputs “1” only for the period t ₂ shown in FIG.
Is output. For this reason, the NAND circuit 8 outputs only the period t ₂ "0".

Therefore, when print data exists in Q2 and LQ2, when data exists in the corresponding print dot Q1 and print dot Q2, the period t ₁ during which the multi-input AND circuit 5 outputs “0” and the corresponding print dot Q1 outputs (t ₁ + t ₂₎ only multi-input aND circuit 5 is "0" in the sum of the time period t ₂ to the multi-input aND circuit 5 outputs "0" when the data in the print dots LQ2 is present and, FET1 the heating resistor r ₀ of the connected thermal head by (T ₁ -t ₁ -t ₂₎ for controlling heat generation to.

That is, when print data exists in the print dot Q1 and a plurality of print dots among the print dots Q2, Q3, LQ2, and RQ2, the print dot Q1 and the other print dots Q2, Q3, LQ2, RQ2 When there is data in the print dot of the multi-input AND circuit 5, the multi-input AND circuit 5 is operated by the sum of the periods of “0” described in the above (2) to (5) according to the other print dots. outputs "0", the period F which is obtained by subtracting from only T ₁ period of the sum of these
The heating resistor r ₀ of the thermal head connected to ET1 generates heat.

For example, Q1, Q2, Q3, LQ2, RQ
When all of the 2 printing data is present, T ₁ - (t ₁
The multi-input AND circuit 5 outputs “1” only during the period of (t ₂ + t ₄ + t ₅ ) = t ₃ , and heats the heating resistor r ₀ of the thermal head connected to the FET 1 during this period t ₃ .

(8) When print data exists only in print dot q1, in the print control range shown in FIG. 1C, print data exists only in print dot q1 and q
If print data does not exist in q2 and q3, in FIG. 1A, q1 = "1", q2 = "0", and q3 = "0".

Accordingly, since “1” is output to the NAND circuits 19 and 20 by q2 = “0” and q3 = “0”, the multi-input NAND circuit 6 outputs “1”. At this time, if the thermal head is normal, "1" is output from the output protection circuit 13. At this time q1 = a "1", since STROBE2 signal such shown in FIG. 2 (B) to the inverter 22 is transferred, "1" from the period T ₂ by multi-input AND circuit 4 shown in FIG. 2 (B) Is output. Then Q
Since 1 = “0”, the multi-input AND circuit 3 outputs “0”.

As described above, since "1" output from the multi-input AND circuit 4 is input to the FET 2, F1 is eventually output.
ET2, there is print data to q1, q2, q3 when no print data, period T ₂ by a "1" is applied to the FET2 is turned on this, the heating resistor r ₀ of the thermal head connected to the FET2 additional resistor r ₁ is the heat generating resistor r ₀ in a state of being connected in series are heat controlling only the period T ₂ and.

(9) When print data exists in the print dots q1 and q2, and when print data exists in the print dot q1 and the print dot q2 one line before the print data, FIG.
In (A), “1” is applied to q1 and q2, respectively, and q
3 = “0” is applied. Thereby, the NAND circuit 20 outputs “1”.

[0217] The NAND circuit 19 at this time, the inverter 23, since 2 inverted signal and q2 = "1" of the GATE C1 signal shown in (B) is applied, only during the period t ₆ in FIG. 2 NAND The circuit 19 outputs "0", and the other outputs "1". Thus the AND circuit 6, the remaining time obtained by subtracting the time t ₆ from the period T ₂ shown in FIG. 2 (t ₇ + t
₈₎ outputs "1", since the multi-input AND circuit 4 and an OR circuit 2 outputs only "1" during this period (t ₇ + t _8), FET2 becomes ON only during this period, connected to the FET2 Heating resistance r ₀ and additional resistance r _{1 of} thermal head
Are connected in series and the heating resistance r ₀ is (T ₂ −t ₆ )
Heat generation is controlled only during the period.

(10) When print data exists in the print dots q1 and q3, and when print data exists in the print dot q1 and the print dot q3 two dots before the print data, FIG.
In (A), “1” is applied to q1 and q3, respectively, and q2
= “0” is applied. Thus, the NAND circuit 19 outputs “1”.

At this time, in the NAND circuit 20, q3 =
“1” and the output of the EOR circuit 21 are input. EO
The inverted signal of the GATE C1 signal shown in FIG.
According to, since the inverted signal of GATE C2 signal shown in FIG. 2 (B) is applied, "1" of the two signals, the period t ₇ only EOR circuit 21 shown in FIG. 2 does not match the "0""1"
And outputs “0” in other periods. Therefore the NAND circuit 20 outputs "0" only for the period t _7, other periods outputs "1".

Therefore, the AND circuit 6 operates during the period T shown in FIG.
_The remaining period (t ₆ + t ₈ ) obtained by subtracting the period t ₇ from ₂ outputs “1”, and the multi-input AND circuit 4 and the OR circuit 2 output “1” only during this period (t ₆ + t ₈ ). So F
ET2 becomes ON only this period, the heating resistor r ₀ and an additional resistance r ₁ of the connected thermal head is only heat controlling heat generation resistor r ₀ in a state of being connected in series (T ₂ -t ₇₎ period FET2 .

(11) When print data exists in the print dots q1, q2, and q3, the print data is written in the print dot q1, the print dot q2 immediately before the print dot q2, and the print dot q3 immediately before the print dot q2. Figure 1 when present
“1” is applied to q1, q2, and q3 of (A).

At this time, as shown in the above (9), the inverted signal of the GATE C1 signal shown in FIG. 2B and q2 = "1" are applied to the AND circuit 19 by the inverter 23. The NAND circuit 19 outputs “0” only during the period t ₆ in FIG.

As shown in the above (10), q3 = “1” and the output of the EOR circuit 21 are input to the NAND circuit 20. At this time, the inverted signal of the GATE C1 signal shown in FIG. 2B by the inverter 23 and the inverted signal of the GATE C2 signal shown in FIG. 2B by the inverter 24 are applied to the EOR circuit 21. , The period t ₇ shown in FIG. 2 where “1” and “0” of both signals do not match.
Only, the EOR circuit 21 outputs “1”, and outputs “0” in other periods. Therefore, the NAND circuit 20 operates in the period t ₇
Only "0" is output, and "1" is output during other periods.

Therefore, the AND circuit 6 operates during the period T shown in FIG.
_TwoTo period t₆And t₇Remaining time t minus₈Is "1"
And the multi-input AND circuit 4 and the OR circuit 2
Interval t ₈Only "1" is output, so FET2 is also
t₈= T_Two− (T₆+ T₇) Only turns on and FET2
Heating resistance r of the thermal head connected to₀And additional resistance
r₁Are connected in series and the heating resistance r₀Is this period T
_Two− (T₆+ T₇) Only heat generation is controlled.

Next, the control operation in the case where there is print data in q1 of the low energy part, there is no print data in q2 or q3 of the low energy part, and there is print data in Q2 or Q3 of the high energy part, etc. . Due to the nature of the print data, the print data is created so that the print data of the high energy portion and the print data of the low energy portion do not exist together in the same dot.

(2-1) When print data exists in print dots q1 and Q2, in the print control range of the low energy portion shown in FIG. 1C, print data exists only in print dot q1 and q2, q3 There is no print data in
When print data is present in the print dot Q2 of the high energy portion shown in FIG. 1B and no print data is present in Q3, in FIG. 1A, q1 = "1", q2 = "0", q3 = "0", Q3
2 = “1” and Q3 = “0”.

At this time, since q3 = "0", the NAND circuit 2
0 outputs “1”. However, in the NAND circuit 19, although q2 = "0", Q2 = "1" is input to the signal input circuit of q2 via the diode 30. Further, the NAND circuit 19 is connected to the
Since the inverted signal of the GATE C1 signal shown in (B) is applied, only the NAND circuit 19 during the period t ₆ in FIG. 2
Outputs “0”, and the other outputs “1”.

Therefore, the AND circuit 6 has the STR shown in FIG.
Period T due to OBE2 signal_TwoTo t ₆Remaining period minus
Between (t₇+ T₈) Outputs "1" and outputs a multi-input AND circuit.
4 also during this period (t₇+ T₈) Only outputs "1"
Thus, FET2 is also turned on only during this period, and is connected to FET2.
Heating resistance r of the continued thermal head₀And additional resistance r₁
Are connected in series and the heating resistance r₀Is (T_Two-T₆)
Heat generation is controlled only during the period.

By shortening the heat generation time by the period t ₆ in this way, it is possible to prevent the effect of heat accumulation on the print dot Q 2 in the high energy portion with respect to the corresponding print dot q 1.

(2-2) When print data exists in print dots q1 and Q3, in the print control range of the low energy portion shown in FIG. There is no print data in q3,
When print data is present in the print dot Q3 in the high energy portion shown in FIG. 1B and no print data is present in Q2, in FIG. 1A, q1 = "1", q2 = "0", q3 = "0", Q3
2 = “0” and Q3 = “1”.

At this time, since q2 = "0", the NAND circuit 19 outputs "1". However, in the NAND circuit 20, although q3 = "0", Q3 = "1" is input to the signal input circuit of q3 via the diode 31.
Further, the output of the EOR circuit 21 is input to the NAND circuit 20. At this time, the EOR circuit 21 includes the inverter 2
2 and the inverted signal of the GATE C1 signal shown in FIG.
Since the inverted signal of the TE C2 signal is applied, "1" of the two signals do not match the "0", only the EOR circuit 21 period t ₇ shown in FIG. 2 outputs "1", the other periods "0"
Is output. Therefore the NAND circuit 20 outputs "0" only for the period t _7, other periods outputs "1".

Therefore, the AND circuit 6 operates as shown in FIG.
The remaining period (t ₆ + t ₈ ) obtained by subtracting the period t ₇ from the period T ₂ by the ROBE2 signal outputs “1”, and the multi-input AND circuit 4 also outputs “1” during this period (t ₆ + t ₈ ). Therefore, FET2 is also turned on only during this period, and FET2
When the heating resistor r ₀ of the thermal head connected to the resistor R ₀ and the additional resistor r ₁ are connected in series, the heating resistor r ₀ becomes (T ₂ −t).
₇ ) Heat generation is controlled only during the period.

By shortening the heat generation period by the period t ₇ in this manner, it is possible to prevent the effect of heat accumulation on the print dot Q 3 in the high energy portion with respect to the corresponding print dot q 1.

(2-3) When print data exists in the print dots q1, Q2, and Q3, in the print control range of the low energy portion shown in FIG. 1C, print data exists only in the print dot q1. There is no print data in q2 and q3, and the print dot Q in the high energy portion shown in FIG.
2, when print data exists in Q3, in FIG. 1A, q1 = “1”, q2 = “0”, q3 = “0”, Q2
= “1” and Q3 = “1”.

At this time, in the NAND circuit 19, q2 = "0"
However, the diode 30 is connected to the signal input circuit of q2.
= “1” is input via the. Further, the NAND circuit 19 is connected to the inverter circuit 23 so that the G signal shown in FIG.
Since the inverted signal of the ATE C1 signal is applied, the NAND circuit 19 only during the period t ₆ in FIG. 2 outputs "0" and the other outputs "1".

In the NAND circuit 20, although q3 = "0", Q3 = "1" is input to the signal input circuit of q3 via the diode 31. In the NAND circuit 20,
The output of the EOR circuit 21 is input.
The OR circuit 21 outputs the inverted signal of the GATE C1 signal and the GAT signal.
"1" and the inverted signal of the E C2 signal, does not match the "0", only the EOR circuit 21 period t ₇ shown in FIG. 2 outputs "1", other periods outputs "0". Therefore, FIG.
During the NAND circuit 20 of the time t ₇ at outputs "0" and the other outputs "1".

Therefore, the AND circuit 6 operates as shown in FIG.
Period T due to ROBE2 signal_TwoTo period (t₆+ T₇)
Remaining time t minus₈Only "1" is output, so F
ET2 also period t₈= T_Two− (T₆+ T₇Only)
And the heating resistance r of the thermal head connected to FET2.
₀And additional resistance r₁Are connected in series and the heating resistance r ₀
Is this period t₈Only heat generation is controlled.

By shortening the heat generation period by the period (t ₆ + t ₇ ) in this way, it is possible to prevent the effect of heat accumulation on the print dots Q2 and Q3 in the high energy portion with respect to the print dot q1.

(2-4) When print data exists in the print dots q1, q2, and Q3, the print dot q1 in the print control range of the low energy portion shown in FIG.
FIG. 5 shows a case where print data exists in print dot q2 and print data does not exist in q3, and print data exists in print dot Q3 in the high energy portion shown in FIG. 1B but no print data exists in Q2. In 1 (A), q1 =
“1”, q2 = “1”, q3 = “0”, Q2 = “0”,
Q3 = “1”.

In this case, the same control as in the above (3) is performed, and the FET 2 is turned on for the period t ₈ = T _2- (t ₆ + t ₇ ).

By shortening the heat generation time by the period (t ₆ + t ₇ ) in this manner, the heat storage effect of not only the print dot q2 of the low energy part but also the print dot Q3 of the high energy part with respect to the corresponding print dot q1 is prevented. can do.

(2-5) When print data exists in the print dots q1, q3, and Q2, the corresponding print dot q1 in the print control range of the low energy portion shown in FIG.
FIG. 1B shows a case where print data exists in print dot q3 and print data does not exist in q2, and print data exists in print dot Q2 in the high energy portion shown in FIG. 1B but no print data exists in Q3. In 1 (A), q1 =
“1”, q2 = “0”, q3 = “1”, Q2 = “1”,
Q3 = “0”.

In this case, the same control as in the above (3) is performed, and the FET 2 is turned on for the period t ₈ = T ₂ − (t ₆ + t ₇ ).

By shortening the heat generation time by the period (t ₆ + t ₇ ) in this way, the heat storage effect of not only the print dot q3 of the low energy part but also the print dot Q2 of the high energy part with respect to the corresponding print dot q1 is prevented. can do.

An embodiment of the thermal head of the present invention having such a control circuit will be described with reference to FIG. 5 and other drawings. FIG. 5 shows an example in which a 64-bit print head is controlled, and the same parts as those in the other figures are denoted by the same reference numerals. In FIG. 5, FETs 1 and 2
Is for controlling the printing of the corresponding printing dot Q1 described with reference to FIG. 1 (A), FETs L1 and L2 are FETs for controlling the printing of the printing dot on the left side of the corresponding printing dot Q1, and R1 and R2 are the corresponding FETs. An FET for controlling printing of a print dot on the right side of the print dot Q1 is shown, VSS indicates a ground signal, and VDD indicates a power supply voltage of a control system.

A shift register 40 is a 64-bit first register to which print data for the high energy portion Q is inputted.
(Not shown) and a 64-bit second shift register (not shown) to which print data for the low energy portion q is input. In this example, CL
According to the OCK signal, 64-bit input data of the high energy part Q is serially input to the first shift register from DATAin1 (Q), and 64-bit input data of the low energy part q is input to the second shift register from DATAin2 (q). Serial input, DATAout
From 1 (Q) and DATAout (q), for example, the data is serially output to the next stage. Reference numerals 41, 42, 43,... Denote data holding registers for holding print data of 3 bits for the high energy portion Q and 3 bits for the low energy portion q.

The data holding register 41 sequentially holds three lines of the 1-bit print data transmitted to the input terminal D ₁ by the LOAD signal, and also prints the 1-bit print data transmitted to the input terminal d _1. The data is sequentially held for only three lines. Data holding register 42,
43 are the same.

For example, the first print data line for the high energy portion is set in the first shift register of the shift register 40, and the first print data line for the low energy portion is set in the second shift register of the shift register 40. after, entering the LOAD signal to the LATCH terminal of the data holding register 41, 42, 43, ..., the data 1 bit of data in the first shift register is transmitted to the input terminal D ₁ transmitted data retention is output from the terminal Q1 is held in the use register 41, the held in the second shift register of the first bit input terminal d data which also data holding register 41 is transferred to the ₁ data is transmitted in Output from terminal q1.

Similarly, the second bit data of each of the first shift register and the second shift register is output from the output terminals Q1, q1 of the data holding register 42, and the third bit of each of the first shift register and the second shift register. Are output from the output terminals Q1 and q1 of the data holding register 43.

Next, the second print data line for the high energy portion is set in the first shift register of the shift register 40, and the second print data line for the low energy portion is set in the second shift register of the shift register 40. and then, if you enter a LOAD signal to the LATCH terminal of the data holding register 41, 42, 43, ..., which are transmitted one new bit of data in the first shift register to the input terminal D ₁ registers for data retention The data held at 41 and output from the output terminal Q1 and the data previously output from the output terminal Q1 are shifted to the next stage and output from the output terminal Q2. Similar control is performed for the second shift register, which new first bit of data of the second shift register is transmitted to the input terminal d ₁ is output from the terminal q1 is held in the data holding register 41, The data previously output from the output terminal q1 is shifted to the next stage and output data is output to the output terminal q2.
Output.

Similarly, the data of the second bit of each of the first shift register and the second shift register is output from the output terminals Q1 and q1 of the data holding register 42, and the data previously output from the output terminals Q1 and q1. Is shifted to the next stage and output from the output terminals Q2 and q2.

The same control is performed in the data holding register 43, and the third bit data of each of the first shift register and the second shift register is output from the output terminals Q1 and q1 of the data holding register 43. The data that has been output from the output terminals Q1 and q1 is shifted to the next stage and output from the output terminals Q2 and q2.

Then, the third print data line for the high energy portion is set in the first shift register of the shift register 40, and the third print data line for the low energy portion is set in the second shift register of the shift register 40. After that, when the LOAD signal is input to the LATCH terminals of the data holding registers 41, 42, 43,..., The same control as described above is performed.
The data of the bit is output from the output terminal Q1, and the data output from the output terminals Q1 and Q2 is shifted to the next stage and output from the output terminals Q2 and Q3, respectively. Also, new first bit data of the second shift register is output from the output terminal q1, and the output terminal q
The data output from 1, q2 is shifted to the next stage and output from output terminals q2, q3, respectively.

Similarly, in the data holding register 42, new second bit data of the first shift register is output from the output terminal Q1, and the output terminal Q
The data output from Q1 and Q2 is shifted to the next stage and output from output terminals Q2 and Q3, respectively. Further, new second bit data of the second shift register is output from the output terminal q1, and the data output from the output terminals q1 and q2 is shifted to the next stage and output from the output terminals q2 and q3, respectively. .

The output terminal Q2 is connected to the output terminal q2 via the diode 30, and the output terminal Q3 is connected to the output terminal q3 via the diode 31.

In the data holding register 43, similarly, the new third bit data of the first shift register is output from the output terminal Q1, and the data previously output from the output terminals Q1 and Q2 is output. Are shifted to the next stage and output from the output terminals Q2 and Q3, respectively. Also, new third-bit data of the second shift register is output from the output terminal q1, and the data that has been output from the output terminals q1 and q2 is shifted to the next stage and output from the output terminals q2 and q3, respectively. .

Here, the first print data line corresponds to the previous two print lines shown in FIGS.
The third print data line corresponds to the preceding print line, and the third print data line corresponds to the corresponding print line.

The output of the output terminal Q2 of the register 41 is input to the NAND circuit 8 (corresponding to LQ2 in FIG. 1A), and the output of the output terminal Q2 of the register 43 is input to the NAND circuit 10 (FIG. A) RQ2). Thus, a control circuit similar to that described with reference to FIG. 1A is configured based on the outputs of the data holding registers 41, 42, and 43.

Therefore, the FET 1 shown in FIG.
(B) A print control range shown in (C) which includes thermal history control according to the state of each print dot.
Control is performed based on the E1 signal and the STROBE2 signal. This control is performed by the FETs L1, L2, FETs R1, R
2 are performed in the same manner.

Therefore, the print data of the high energy portion is input to the first shift register of the shift register 40,
The print data of the low energy portion is input to the shift register, and the STROBE1 signal, STROBE2 signal, G
ATE A1 signal, GATEA2 signal, GATE B1
Signal, GATE B2 signal, GATE C1 signal, GA
By inputting a control signal such as a TEC2 signal, it is possible to simultaneously perform the printing control based on the printing data of the high energy portion and the printing data of the low energy portion including the printing control range and the heat storage effect prevention control as described above. For example, as shown in FIG. 9, multi-color printing is accurately performed by one scan.

The specific structure of the thermal head according to the present invention will be described with reference to FIG. 3, 100 is a common electrode portion, 101-0, 101-1,... Are heat generating resistors (r ₀ ), 102-0, 102-1,... Are high energy side connection pads, 103-0, 103-. 1 ... are additional resistor (r _1), 104-0,104-1 ··· low energy side connection pad, 105-0,105-1 ... high energy side connection pad of the IC-side, 106 −
.. Are low-energy-side connection pads on the IC side, 107-0, 107-1... Are wires for high-energy-side wire bonding, 108-0, 1
08-1... Are wires for wire bonding on the low energy side.

The common electrode section 100, the heating resistor 101-0,
101-1 ..., high energy side connection pad 102-
0, 102-1 ..., additional resistors 103-0, 103-
1,..., Low energy side connection pads 104-0, 10
.. Are formed on the same insulating substrate (not shown) by a thin film technique.

The high energy side connection pad 105-
0, 105-1 ..., low energy side connection pad 10
6-0, 106-1 ... are ICs not shown.
Formed on the side. And the high energy side connection pad 10
.. And the high energy side connection pads 105-0, 105-1.
07-1 ... and the low energy side connection pads 104-0, 104-1 ...
And low energy side connection pads 106-0, 106-1
Are also wire-bonded by wires 108-0, 108-1.

The connection pad 105-0 on the high energy side is F
ET1 and the low energy side connection pad 106−
0 is connected to FET2, so that FET1,
2 is selectively turned on to generate heat in a high energy state by the heating resistor r ₀ alone or the heating resistor r 0.
₀ and additional resistor r ₁ is the heat generation control of a low energy state in a state of being connected in series is performed.

Next, a second control circuit for one dot of the thermal head according to the present invention will be described with reference to FIGS. FIG. 6 shows an example in which forward print data and adjacent data of a high energy portion are added to a control range, and FIG. 7 is an explanatory diagram of control signals applied to the control circuit.

In the control circuit shown in FIG. 6A, in the unique control in the high energy portion, as shown in FIG. 6B, when the line of the corresponding print dot Q1 is set as the corresponding print line, Previous print dot Q at
2 and the left and right print dots LQ2 and RQ2, and the print control range of the previous print dot Q3 in the previous two print lines.

In the unique control in the low energy portion, as shown in FIG. 6D, when the line of the relevant print dot q1 is set as the relevant print line, the previous print dot q2 in the preceding one print line, and further, It has a print control range of the previous print dot q3 in the previous two print lines.

In this example, as shown in FIG. 6C, the influence range of the high-energy portion on the corresponding print dot q1 in the low-energy portion is represented by the print dots Q2 and Q3 and the LQ2 and LQ2 of the adjacent print dot of the preceding one print line. RQL2.

For this purpose, as shown in FIG. 6A, diodes 30, 31, 32, and 33, an inverter 25, a NAND circuit 26, an EOR circuit 27, and the like are provided.

The GATE C3 signal is shown in FIG.
As described above, the signal falls simultaneously with the STROBE2 signal, and the period (t)
₆+ T₇+ T₈) It will rise later. Of course these
(T ₆+ T₇+ T₈) Can be set appropriately according to the characteristics of the paper.
It can be.

The diodes 30 and 31 are the same as those in the control circuit shown in FIG.

The diode 32 is for controlling the influence of print data in the print dot LQ2 of the high energy portion when the print data is present. The diode 32 has a signal input circuit for the print dot LQ2 of the high energy portion and an input to the NAND circuit 26. It connects to a circuit.

The diode 33 is for controlling the influence of print data in the print dot RQ2 of the high energy portion when the print data is present. The diode 33 has a signal input circuit for the print dot RQ2 of the high energy portion and an input for the NAND circuit 26. It connects to a circuit.

The other input circuit of the NAND circuit 26 has EOR
The output of the circuit 27 is input.

An inverted signal of the GATE C2 signal and an inverted signal of the GATE C3 signal are input to the EOR circuit 27.

FIG. 6A performs the same operation as the control circuit shown in FIG. 1A for controlling the high energy portion alone. For the control of the low energy part alone, LQ
Since both RQ2 and RQ2 are "0", the NAND circuit 26 outputs "1" to the multi-input AND circuit 6-0. Otherwise, the operation is the same as that of the control circuit shown in FIG. Therefore, these single operations are omitted for simplification of description.

A typical control for the corresponding print dot q1 in the low energy portion when print data exists in LQ2 and RQ2 in FIG. 6C will be described below.

(3-1) When print data exists in the print dots q1 and LQ2, in the print control range of the low energy portion shown in FIG. 6D, print data exists only in the print dot q1 and q2, q3 There is no print data in FIG.
When print data is present in the print dot LQ2 of the high energy portion shown in FIG. 6B and no print data is present in Q2, Q3, and RQ2, q1 = “1”, q2 = “0” in FIG.
q3 = “0”, Q2 = “0”, Q3 = “0”, LQ2 =
"1", RQ2 = "0".

At this time, since q2 = "0" and Q2 = "0", the NAND circuit 19 outputs "1", and q3 = "0" and Q3
Since 3 = “0”, the NAND circuit 20 outputs “1”.

Since LQ2 = "1", the NAND circuit 26
"1" is applied to one input circuit, and the output of the EOR circuit 27 is input to the other input circuit. Then E
The OR circuit 27 outputs the inverted signal of the GATE C2 signal shown in FIG.
7B, the inverted signal of the GATE C3 signal shown in FIG. 7B is applied, so that the “1” and “0” of the two signals do not match, and the EOR circuit 27 only for the period t ₈ shown in FIG.
Outputs “1”, and outputs “0” in other periods. Therefore the NAND circuit 26 outputs "0" only for the period t _8, other periods outputs "1".

Accordingly, the multi-input AND circuit 6-0 has the structure shown in FIG.
Period T due to STROBE2 signal shown_TwoTo period t₈To
Remaining period (t₆+ T₇+ T₉) Outputs "1"
Then, the multi-input AND circuit 4 and the OR circuit 2 also operate during this period (t
₆+ T₇+ T₉) = T_Two-T ₈Only output "1"
Thus, FET2 is also turned on only during this period, and is connected to FET2.
Heating resistance r of the continued thermal head₀And additional resistance r₁
Are connected in series and the heating resistance r₀Is this (T_Two-T
₈) Heat generation is controlled only during the period.

[0282] By shortening the only heating time period t ₈ in this manner, it is possible to prevent heat accumulation effect in the print dot LQ2 in the high energy portion to the corresponding print dot q1.

(3-2) When print data exists in print dots q1 and RQ2, in the print control range of the low energy portion shown in FIG. In the case where there is no print data in q3, there is print data in the print dot RQ2 of the high energy portion shown in FIG. 6C, and there is no print data in Q2, Q3 and LQ2, q1 = "1" in FIG. , Q2 =
“0”, q3 = “0”, Q2 = “0”, Q3 = “0”,
LQ2 = "0" and RQ2 = "1".

At this time, since q2 = "0" and Q2 = "0", the NAND circuit 19 outputs "1", and q3 = "0" and Q3
Since 3 = “0”, the NAND circuit 20 outputs “1”.

Since RQ2 = "1", the NAND circuit 26
"1" is applied to one input circuit, and the output of the EOR circuit 27 is input to the other input circuit. Thus as in the case where print data exists in the print dot q1 and LQ2 of the (1) only during the period t ₈ shown in FIG. 7 (B) E
The OR circuit 27 outputs “1” and outputs “0” in other periods, and the heating resistor r ₀ and the additional resistor r _{1 of} the thermal head connected to the FET 2 are connected in series.
₀ is controlled to generate heat only for a period (T ₁ −t ₈ ).

[0286] By shortening the way by the period t ₈ heating time, it is possible to prevent the heat accumulation effect in the print dot RQ2 high energy portion to the corresponding print dot q1.

(3-3) Print dot q1, LQ2, R
When print data exists in Q2, in the print control range of the low energy portion shown in FIG. 6D, there is print data only in the corresponding print dot q1, there is no print data in q2 and q3, and FIG. In FIG. 6A, when print data is present in print dots LQ2 and RQ2 in the high-energy portion and no print data is present in Q2 and Q3, q1 = "1" in FIG.
q2 = “0”, q3 = “0”, Q2 = “0”, Q3 =
“0”, LQ2 = “1”, and LQ2 = “1”.

At this time, as in the case where the print data exists in the print dots q1 and LQ2 in the above (1), FIG.
Only EOR circuit 27 period t ₈ shown in (B) outputs a "1", the other period, the outputs "0", the heating resistor r ₀ and an additional resistance r ₁ of the connected thermal head series FET2 In the connected state, the heat generation of the heating resistor r ₀ is controlled only for a period of (T ₂ −t ₈ ).

[0289] By shortening the way by the period t ₈ heating time, it is possible to prevent the heat accumulation effect in the print dot LQ2, RQ2 high energy portion to the corresponding print dot q1.

(3-4) Print dots q1, Q2 and LQ
When print data exists in the print control range of the low energy portion shown in FIG.
1 has print data, q2 and q3 have no print data, and the print dots Q in the high energy portion shown in FIG.
2, when there is print data in LQ2 and no print data in Q3 and RQ2, q1 = "1" in FIG.
= "0", q3 = "0", Q2 = "1", LQ2 =
“1”, Q3 = “0”, and RQ2 = “0”.

At this time, since q3 = "0" and Q3 = "0", the NAND circuit 20 outputs "1". However, in the NAND circuit 19, although q2 = "0", Q2 = "1" is input to the signal input circuit of q2 via the diode 30. Further by the inverter 23 to the NAND circuit 19, the inverted signal of the GATE C1 signal shown in FIG. 7 (B) is applied, the NAND circuit 19 only during the period t ₆ in FIG. 7 (B) is a "0" The other outputs "1".

Since LQ2 = "1", the diode 3
2 to one input circuit of the NAND circuit 26 via "1"
And the output of the EOR circuit 27 is input to the other input circuit. At this time, the inverted signal of GATE C2 shown in FIG. 7B by the inverter 24 and the GAT signal shown in FIG.
Since the inverted signal of the EC3 signal is applied, “1” and “0” of both signals do not coincide with each other, and the period t shown in FIG.
_{For eight, the} EOR circuit 27 outputs “1”, and outputs “0” in other periods. Therefore, the NAND circuit 26 operates in the period t ₈
Only "0" is output, and "1" is output during other periods.

Therefore, the multiple input AND circuit 6-0 is
The remaining period (t ₇ + t ₉ ) obtained by subtracting the periods t ₆ and t ₈ from the period T ₂ by the STROBE2 signal shown in FIG. 3B outputs “1”, and the multi-input AND circuit 4 and the OR circuit 2 also output this signal. period _{(t 7 + t 9) =} T 2 - since (t ₆ + t ₈₎ only outputs "1", FET2 becomes oN only during this period, additional resistance r and the heat generating resistor r ₀ of the thermal head connected to the FET2 Heating resistance r with ₁ connected in series
₀ is controlled to generate heat only during this [T _2- (t ₆ + t ₈ )] period.

In this way, by shortening the heat generation time by the period (t ₆ + t ₈ ), it is possible to prevent the effect of heat accumulation on the printing dots Q2 and LQ2 in the high energy portion with respect to the printing dot q1.

(3-5) Print dots q1, Q3 and LQ
When print data exists in the print control range of the low energy portion shown in FIG.
1 has print data, q2 and q3 have no print data, and the print dots Q in the high energy portion shown in FIG.
3, when there is print data in LQ2 and no print data in Q2 and RQ2, q1 = "1" in FIG.
= “0”, q3 = “0”, Q2 = “0”, Q3 =
“1”, LQ2 = “1”, and RQ2 = “0”.

At this time, since q2 = "0" and Q2 = "0", the NAND circuit 19 outputs "1". However, in the NAND circuit 20, although q3 = "0", Q3 = "1" is input to the signal input circuit of q3 via the diode 31. Further, the output of the EOR circuit 21 is input to the other input circuit of the NAND circuit 20. At this time, EOR
Since the inverted signal of the GATE C1 signal shown in FIG. 7B by the inverter 23 and the inverted signal of the GATE C2 signal shown in FIG. Does not match, FIG. 7 (B)
The EOR circuit 21 outputs “1” only for the period t ₇ shown in FIG.
In other periods, “0” is output. Therefore, the NAND circuit 20
Outputs only the period t ₇ "0", the other period, the output "1".

[0297] Further LQ2 = only for the period t ₈ the NAND circuit 26, as shown when the print data to the print dots q1 and LQ2 of the (1) for the "1" is present and outputs "0", the other During the period, “1” is output.

Therefore, the multi-input AND circuit 6-0 is not
The remaining period (t ₆ + t ₉ ) obtained by subtracting the periods t ₇ and t ₈ from the period T ₂ by the STROBE2 signal shown in FIG. 3B outputs “1”, and the multi-input AND circuit 4 and the OR circuit 2 also output this signal. period _{(t 6 + t 9) =} T 2 - since (t ₇ + t ₈₎ only outputs "1", FET2 becomes oN only during this period, additional resistance r and the heat generating resistor r ₀ of the thermal head connected to the FET2 Heating resistance r with ₁ connected in series
₀ is controlled to generate heat only during this [T _2- (t ₇ + t ₈ )] period.

In this way, by shortening the heat generation time by the period (t ₇ + t ₈ ), it is possible to prevent the effect of heat accumulation on the print dots Q3 and LQ2 in the high energy portion with respect to the corresponding print dot q1.

In the other cases, the control circuit shown in FIG. 6A can prevent the adverse effect of the print dots in the high energy portion.

As described above, according to the present invention, high energy printing control and low energy printing control can be performed very accurately.
Even when data of two colors are mixed, accurate printing can be performed.

In the above description, the embodiments for two energies, high and low, have been described, but the present invention is of course not limited to these.

The color is not limited to red and black, but may be green and black, another combination, or a combination of three or more colors.

[0304] Another embodiment of the present invention will be described.

Depending on the printing medium, printing can be performed when high energy is applied by a thermal head, such as Aladdin Card (registered trademark) manufactured by Tokyo Magnetic Printing Co., Ltd., but changes to another color when low energy is applied. There are rewritable media that can erase characters and the like printed with high energy and write character figures and the like again with high energy printing.

The control circuit shown in FIGS. 1 and 6 can be used for such a medium. In this case, S
The TROBE1 signal is set to add high energy for printing, and the STROBE2 signal is set to give low energy for erasing printed characters and the like. In this case, q1, q2, and q3 are print erasure data for performing print erasure control. In this medium, since the range of the low energy for erasing is very severe, not only the magnitude of the STROBE2 signal but also the thermal history control based on the presence / absence of q2 and q3, that is, the heat generation control based on the print erasure data q2 and q3, It is preferable that the unit power value is suppressed by adding or adding resistance, and the energy is adjusted by adjusting the magnitude of the STROBE2 signal.

Thus, a thermal head for a rewritable medium can be provided.

[0308]

According to the present invention, the following effects can be obtained.

(1) An additional resistor is connected to the heat generating means,
Since the switching means 1 and the second switching means 2 can selectively control whether only the heat generating means is operated with high energy, or whether the heat generating means and the additional resistor are connected in series with low energy, the thermal head can be controlled. Not only can be controlled in a high energy state and a low energy state, but also can be operated for a long time in a low energy state.

(2) Since the heat generating means and the additional resistor are constituted by the same thin-film resistor, a small, high-resolution two-power type thermal head can be provided.

[Brief description of the drawings]

FIG. 1 is a control circuit per dot of a thermal head according to the present invention.

FIG. 2 is an explanatory diagram of a control signal applied to the control circuit of FIG. 1;

FIG. 3 is a configuration diagram of a head portion of a two-power type thermal head of the present invention.

FIG. 4 is a comparison diagram of heat generation energy between a conventional example and the present invention.

FIG. 5 is an embodiment of the present invention.

FIG. 6 shows a second control circuit per dot of the thermal head according to the present invention.

FIG. 7 is an explanatory diagram of a control signal applied to the control circuit of FIG. 6;

FIG. 8 is an explanatory diagram of printing energy for thermal paper.

FIG. 9 is an explanatory diagram of multicolor printing.

FIG. 10 is a prior art control circuit.

11 is an explanatory diagram of a control signal applied to the control circuit of FIG.

FIG. 12 is a second control circuit of the prior art.

13 is an explanatory diagram of a control signal applied to the control circuit of FIG.

FIG. 14 is an equivalent circuit diagram of the control circuit of FIG.

FIG. 15 is a logic table of the control circuit of FIG. 14;

[Explanation of symbols]

 1, 2 FET 3, 4, 5 Multi-input AND circuit 6 AND circuit 7, 8, 9, 10 NAND circuit 11, 12 EOR circuit 13 Output protection circuit 14, 15, 16, 17, 18 Inverter 19, 20 NAND circuit 21 EOR circuit 22, 23, 24 Inverter 30, 31 Diode 40 Shift register 41, 42, 43 Data holding register

Continued on the front page (72) Inventor Kazuhito Uchida 1-1-13 Nihonbashi, Chuo-ku, Tokyo TDC Corporation F-term (reference) 2C065 AB01 AC01 CZ03 KJ15 KJ17 2C066 AD01 BF04 CC01 CC05 CC06 CC13

Claims (2)

[Claims] A heating element for generating heat of a plurality of different energies; an additional resistor connected to the heating element; first switching means for controlling the heating element to an operating state or a non-operating state; And second switching means for controlling the additional resistor to an operation state or a non-operation state; first strobe signal input means for performing heat control of the heating element corresponding to first energy with respect to the first switching means; Second strobe signal input means for performing heat control of the heating element corresponding to second energy with respect to second switching means; and performing print control with the first energy, and performing print control of print data in a print control range of the corresponding print data. First heat generation time control means for controlling a heat generation time of the heating element based on the first strobe signal according to presence / absence; A second heating time control means for controlling the heating time of the heating element based on the second strobe signal in accordance with the presence or absence of printing data in a printing control range of the printing data. 2 power type thermal head. 2. A two-power thermal head according to claim 1, wherein said heating element and said additional resistor are constituted by thin film resistors formed on the same insulating substrate.