JPS6349423B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a thermal recording device widely used in facsimiles and the like, and particularly to a thermal recording device suitable for realizing an all-driver type thermal recording head having independent driver circuits corresponding to all heating elements. It relates to a recording device. [Background of the Invention] As a means of realizing high speed, low cost, and miniaturization of thermal recording, a method of realizing a driver chip with a built-in shift register on a substrate forming a heating resistor (driver-mounted thermal recording head) is becoming mainstream. An example of a head configuration using this type of system is given in Japanese Patent Application Laid-Open No. 1983-69186 ``Thermal Recording Head'' and the paper presented at the 1981 Image Engineering Conference ``Thermal Head for High-Speed Thermal Recording'' (pp. 169-172). It is stated in That is, it is basically based on a driver chip consisting of a shift register, a latch register, and an output driver, and some functions are added to this to simplify the head board wiring and increase the recording speed. FIG. 1 is a basic configuration diagram of a conventional head driver chip. In this figure, 100 is a shift register, 200 is a latch register, and 300 is an output driver, and the circuit is constructed by combining n sets (generally, n=8 to 32) of these.
The shift register 100 also has a serial data input terminal SI connected to the signal line 110, and a signal line 13 connected to the serial data input terminal SI.
The latch register 200 has a serial data output terminal SO connected to 0, a data transfer clock input terminal CP connected to the signal line 120, and a group of parallel data output terminals Q ₀ to Q _o connected to the signal line 140. A parallel data output terminal group Q ₀ -Q _o of the shift register 100 is connected to an input terminal group D ₀ -D _o , and has a latch strobe terminal T connected to a signal line 210 . Furthermore, latch register 2
The output of output terminal group Q ₀ ~Q _o of 00 is signal line 220
The output terminal group I ₁ to _{I o} of the output driver 300 via
is input to the signal line 310, and the corresponding drive circuit is driven when the AND condition with the output enable terminal E connected to the signal line 310 is satisfied, and the output terminal group is
The outputs O ₁ to _{O o} energize the corresponding output lines via signal line 320. A driver-equipped thermal recording head can be configured using such a driver chip, but recording control is also required to increase the recording speed, reduce the power supply capacity, and maintain the head temperature even when not recording. If you try to achieve higher quality by implementing heat pulse control to maintain the performance and chip failure detection control when the driver chip is actually mounted on the head, the following problems will become apparent. In other words, the method of providing a drive permission signal to the driver chip in response to the recorded image signal becomes too complicated. In order to provide a drive permission signal to the driver chips in response to the recording signal, it is necessary to control the output enable terminals 310 of each chip.
Assuming a head with 32 dots/chip and a recording width of JIS standard B4 size paper, 64 driver chips are required and wiring patterns for 64 enable signal lines must be prepared. The increase in head size due to this upgrade is about 10 mm in width, which is an increase of about 30% since the head before the upgrade was about 30 mm wide. Further, these enable line control circuits and connection means are required, which not only poses a problem in terms of cost but also in terms of reliability. Additionally, adding heat pulse control makes the logic even more complex, requiring additional hardware. In other words, in order to perform heat pulse control, a circuit that energizes all drivers in a given driver chip at once, regardless of the presence or absence of a recording signal, and its control are required, but the former is required to add functionality. Even if the necessary minimum amount is added, control requires a control signal input circuit and timing control in synchronization with switching and synchronization with the original recording operation, and this technique is not well known. Furthermore, head testing when the chip is actually mounted on the head is insufficient for conventional chips.
In other words, a chip failure can only be determined from the output terminal, but a shift register failure, which accounts for most of the logic, cannot be known unless information from all shift registers in multiple chips is output. It is necessary to repeat discovery and repair, and not only does this cost become a problem, but repeated repairs can also cause damage to normal parts. [Object of the Invention] An object of the present invention is to provide a thermal recording device equipped with a highly integrated head driver chip suitable for recording control. [Summary of the Invention] The present invention provides a shift register that includes a plurality of heat generating resistors and a shift register that is supplied with serial data for controlling whether or not to energize the plurality of heat generating resistors and converts the serial data into parallel data. , a latch register that holds the parallel data output of the shift register for a predetermined period of time, and a driver chip that includes a driver circuit that generates a drive signal to be supplied to the plurality of heating resistors in response to the parallel data output. In a thermal recording device in which the driver chip is divided into a plurality of sets corresponding to a plurality of heating resistors, each set of driver chips further includes a shift register for chip selection, and a shift register for chip selection. a latch register for chip selection that holds the output of the register for a predetermined time; and whether or not to supply the output of the drive signal of the driver circuit to the heating resistor in accordance with the output of the latch register for chip selection. and an input/output control circuit having a serial data input terminal, a serial data output terminal, a test signal input terminal, and an operation mode specification input terminal. At least one of the chip select transfer mode, image data transfer mode, and test mode is selected based on a mode designation signal commonly input to the input terminal, and in the chip select transfer mode, the shift register for chip select is selected. The chip select signal is connected between the serial data input terminal and the serial data output terminal, and the serial data output terminal of the previous stage and the serial data input terminal of the latter stage are connected, and the chip select signal is connected to the serial data at the beginning. The chip select signal is supplied to the input terminal and transferred to the chip select shift register and the chip select latch register of each set, and in the image data transfer mode, the shift register is connected to the serial data input terminal. and the serial data output terminal, and also connects the serial data output terminal of the previous stage and the serial data input terminal of the latter stage, and supplies the serial data to the serial data input terminal of the first stage. and transfer the serial data to the shift register and latch register of each set, and in the test mode, connect the shift register between the test signal input terminal and the serial data output terminal, and transfer the serial data to the shift register and latch register of each set. A test signal is commonly supplied to the test signal input terminal, and a test signal output is extracted from the serial data output terminal of each group to determine whether or not there is a failure in the shift register of each group. do. [Embodiment of the Invention] FIG. 2 is a block diagram showing an embodiment of the driver chip according to the present invention.
00 and 100', latch resistors 200 and 2
00', output driver 300', input/output control circuit 4
00 and ANDGATE 500, ORGATE 600
It is equipped with The input/output control circuit 400 includes a serial data input terminal SI connected to the signal line 110',
Data transfer clock input terminal CP connected to signal line 120', latch strobe input terminal T connected to signal line 210', input terminals 430 and 44.
Operation mode designation input terminal M0, M connected to
1. Test signal input terminal TS connected to signal line 310', transfer data output signal terminal SO connected to signal line 130', terminal groups SI1, CP1, SO1, T1 and connected to signal lines 410 and 420. S.I.
2, CP2, SO2, T2 and a chip enable control signal terminal EO connected to signal line 610. The AND gate 500 receives the output of the OR gate 600 and the input signal line 310', and its output is connected to one enable terminal EO of the driver circuit 300' through the signal line 510. Further, the OR gate 600 receives as input the chip enable control signal terminal EO of the input/output control circuit 400 and the output signal line 220' of the latch register 200'. Other parts having the same reference numbers as in FIG. 1 have the same functions. The input/output control circuit 400 selects the data inputted from the serial data input terminal SI or the data inputted from the test signal input terminal TS according to the designation signals inputted to the operation mode designation input terminals M0 and M1, and selects the data inputted from the test signal input terminal TS and outputs the selected data to the shift register 100. and 100', but the data transfer clock input from the clock input terminal CP is selectively applied to the shift register 100 or 100' according to the previous mode signal input, and the strobe signal input from the data strobe signal input terminal T is also applied to the shift register 100 or 100'. Signal also latch register 20
0 or 200', and the control circuit 50 of the output driver 300'
It also outputs control signals EO to 0 and 600.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to realize complex recording control with simple hardware. In other words, the driver chip uses a common input/output line and can realize a variety of operations by switching modes, which has the advantage of miniaturization and simplification of control hardware. Furthermore, even when chips are installed in the driver, there is an advantage that failures in each chip can be easily detected in the test mode. In addition, the present driver chip and recording control circuit are versatile and can be widely applied to facsimiles, printers, etc., so they can be expected to be effective in mass production and are suitable for LSI implementation. Also
Even when converted to LSI, it has the advantage of allowing a small chip size.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional driver chip.
FIG. 2 is a block diagram of an embodiment of the driver chip according to the present invention, FIGS. 3 to 7 are signal flow diagrams showing the data flow depending on the operation mode of the driver chip, and FIGS. A circuit diagram of the internal blocks of the driver chip, FIG. 10 is a block diagram showing the overall configuration of one embodiment of the recording control device according to the present invention, and FIG. 11 is a time chart thereof.
FIGS. 12 and 13 are flowcharts. 100...Shift register, 200...Latch register, 300'...Output driver, 100'...
...Shift register, 200'...Latch register,
400... input/output control circuit, 700... recording head, 900... signal source.

Claims (1)

[Scope of Claims] 1. A plurality of heating resistors, and a shift register that is supplied with serial data for controlling whether or not to energize the plurality of heating resistors and converts the serial data into parallel data; The driver chip includes a latch register that holds the parallel data output of the shift register for a predetermined period of time, and a driver circuit that generates a drive signal to be supplied to the plurality of heating resistors in response to the parallel data output, In a thermal recording device in which a driver chip is divided into a plurality of sets corresponding to a plurality of heating resistors, each set of driver chips further includes a shift register for chip selection, and a shift register for chip selection. A chip select latch register that holds the output for a predetermined period of time, and logic for determining whether or not to supply the output of the drive signal of the driver circuit to the heating resistor in accordance with the output of the chip select latch register. and an input/output control circuit having a serial data input terminal, a serial data output terminal, a test signal input terminal, and an operation mode specification input terminal, each set having an operation mode specification input terminal. At least one of the chip select transfer mode, image data transfer mode, and test mode is selected based on a mode designation signal commonly input to the chip select transfer mode. Connect between the data input terminal and the serial data output terminal, and also connect the serial data output terminal of the previous stage and the serial data input terminal of the latter stage, and send the chip select signal to the serial data input terminal of the first stage. and transfers the chip select signal to each set of the chip select shift register and the chip select latch register, and in the image data transfer mode, the shift register is connected to the serial data input terminal and the chip select latch register. and a serial data output terminal, and also connects the serial data output terminal of the previous stage and the serial data input terminal of the latter stage, and supplies the serial data to the serial data input terminal of the first stage, The serial data is transferred to the shift register and the latch register of each set, and in the test mode, the shift register is connected between the test signal input terminal and the serial data output terminal, and the test of each set is performed. A thermosensitive device characterized in that a test signal is commonly supplied to the signal input terminal, and the output of the test signal is extracted from the serial data output terminal of each group to determine whether or not there is a failure in the shift register of each group. Recording device.