JPS58205374A - Heat-sensing recorder - Google Patents

Abstract

PURPOSE:To attain a high speed recording and to prevent streaking phenomenon, by determining the power application time suitably to obtain a printing corresponding to a ''1'' signal just before a ''0'' signal, when ''1'', ''0'' appear in the same bit of a recording signal sequentially. CONSTITUTION:A driving circuit 3 applies power selectively to thermal resistive elements 1 arranged in parallel in a line in response to a series of recording signals. A shift register 11 stores a series of recording signal information to be applied to the driving circuit 3, and a shift register 12 stores a series of recording signal information after at least one unit time. The recording signal information of the shift registers 11, 12 is compared at each corresponding bit and the power application time at present to each thermal resistive element 1 is controlled that the power is not applied after at least one unit time and, power is applied after at least one unit time in a shorter time than the time the case with the power application at present time when the power is applied at present time.

Description

[Detailed description of the invention] The present invention relates to a thermal recording device.

The thermal recording method is a method of recording on thermal recording paper by arranging a large number of heating resistors, which are recording elements, in a row and selectively energizing them according to the recording signal to generate heat. , which has advantages such as ease of maintenance and clean records, is rapidly becoming popular as a recording method in facsimiles, etc. However, there is still a problem in terms of high speed, and for example, compared to electrostatic recording method, Double the recording time.

Therefore, various measures have been considered to increase the recording speed. One of them is to provide a separate drive circuit for each heat-generating resistor and transfer one line's worth of recording signals from a shift register to these drives in parallel. There is a simultaneous energization method that simultaneously energizes all the heat generating resistors according to the recording signal by supplying it to the drive circuit of be. With this method, the time required to energize all the heating resistors can be equal to the energizing time of one heating resistor, so, for example, the heating resistors can be divided into multiple groups and energized for each group using a matrix circuit. It is suitable for high-speed recording compared to the conventional matrix energization method. However, in order to effectively increase the recording speed using this method, the energization stop time must also be shortened in the energization repetition period.

However, if we simply shorten the energization stop time while the energization time is constant, the recorded signal corresponding to the same heating resistor will become two.
In the case of continuous black information for more than one line, if the same heating resistor is energized for several lines in succession, the heating resistor accumulates heat and becomes overheated. As a result, if the recording signal corresponding to the heating resistor is white information after two or more consecutive lines of black information, the dots on the thermal recording paper corresponding to the white information develop some color, which is the so-called trailing phenomenon. This may occur. In particular, when the color density of recording is increased by increasing the power applied to the heating resistor or the power application time, the trailing phenomenon occurs even if the number of consecutive energized lines is small (or even one line in some cases). may occur.

The present invention has been made to improve the above-mentioned drawbacks, and an object of the present invention is to provide a thermal recording device that is capable of high-speed recording and can prevent the four-tail phenomenon.

The above object of the present invention is to provide heating resistors arranged in parallel in - columns;
A drive circuit that selectively energizes these heating resistors in accordance with a series of recording signals, a first memory circuit that stores information on a series of recording signals to be supplied to these drive circuits, and a first memory circuit that stores information on a series of recording signals to be supplied to these drive circuits; a second storage circuit that stores a series of recording signal information that is stored at least one time later; and a second storage circuit that stores a series of recording signal information that is stored at least one time later; a comparison circuit for comparing
According to the comparison result of this comparison circuit, when current is applied to each heating resistor at the current time, 1! If j is not energized for at least one time and is energized at the current time, it is energized at least one time later, and controlled so that it is shorter than when it is energized at the current time as well. This is achieved by a thermosensitive recording device characterized by comprising a current application time control means.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail by way of preferred embodiments thereof, with reference to the drawings.

FIG. 1 shows the structure of an embodiment of a thermal recording apparatus according to the present invention. In the figure, 1 is a heating resistor of a thermal head for heat-sensitive recording.For example, in the case of an A4 size thermal head, 1728 heating resistors 1 are arranged in a row on the head substrate.One end of each of these heating resistors 1 is One end of the external power supply 2 is connected in common, and each other end is connected to the same number of drive circuits 3 as the heating resistors 1.
are connected to the other end of the power supply 2 via the respective terminals.

The drive circuit 3 is mainly composed of switching elements,
Each switching element is turned on by the coincident output of a recording signal supplied in parallel via a latch circuit, which will be described later, and an output permission signal D1 manually input via an output control signal terminal 4, and each heating resistor 1 is turned on. energize them individually.

5 is the recording signal input terminal, and V here is, for example, a black and white 2-speed facsimile machine with 1728 bits per line.
A series of recorded signals of the statue signal temple are input in series. This recording signal is input to a shift register 12, which is a second storage circuit, via an AND gate 17 and a 0)1 gate 18, which are controlled by a timing signal SIK input from a timing control terminal 6. . This shift register 12 has a capacity of 1728 bits, and in response to the clock signal CP input from the clock input terminal 8, the input recording signal is sequentially transferred to the right and stored for one line. The clock signal CP inputted from the clock input terminal 8 is controlled by the timing signal S1 inputted from the timing control terminal 6 and the timing signal 82 manually inputted from the timing control terminal 7 [therefore controlled by the output signal of the OR gate 19]. Through the AND gate 20,
The signal is input to the shift register 12. Therefore, the clock signal Cp is input to the shift register 12 only when the timing signal S1 or the timing signal S2 is "1".

At the same time that a recording signal is input from the recording signal input terminal 6 to the shift register 12 at the timing when the timing signal S1 is "1", the recording signal stored in the shift register 12 one time ago is transferred to the shift register 12. AN controlled by a timing signal S1 read out in series from the final stage on the right end and inputted from the timing control terminal 6.
The signal is inputted via the D gate 13 and the OR gate 15 to another shift register 11, which is a first storage circuit.

The shift register 11 sequentially transfers and stores the input recording signal to the right using the same clock signal CP as the shift register 12, and has a capacity of 1728 bits. The contents of the shift register 11 are output in parallel and sent to 1728 latch circuits 10 (latched to the latch control terminal 9).
The J signal is moved at the timing of the signal TL. 1. On the other hand, the contents of shift register 11 are also read out serially from the rightmost final stage, and the contents of shift register 11 are
It is compared with the recorded signal serially read out from the shift register IIK, and is manually input as shift register IIK replacement data through the ANL gate) 14 and OR gate 15 controlled by the timing signal S2 input from the timing control terminal 7. be done.

The recording signal serially outputted from the shift register 12 is input to the ANL gate 21, and at the same time, it is input manually to the shift register 12 again via the AND gate 16 and OR gate 18 which are controlled by the timing signal S2. be done.

Next, the operation of this embodiment will be explained with reference to the time chart of FIG. First, assume that the shift register 11 stores the recording signal of the i-th line, or the shift register 12 stores the recording signal of the i+1-th line, that is, one time later. In this state, the i-th
Assume that +2 line recording signals are manually input in series.

At this time, as shown in FIG. 2(a), the timing signal vsi at the "1" level is continuously input to the timing control terminal 6 while the recording signal for one line is input to the terminal 5. Therefore, the recording signal of the i+2th line passes through gates 17 and 18 and is read into the shift register 12 by the clock signal Cp vc. At the same time, while the timing signal S1 at the toe 9 timing control terminal 6Vcl'-IJ level is continuously input, the shift register
The recording signal of the i+1th line stored in 2 is game)
13.15, and is read into the shift register 11 by the clock signal CP.

When all the recording signals for one line are read into the shift register 11, the latch trigger signal TL is supplied via the latch circuit 10Vc terminal 9 as shown in FIG. Content is part 1
They are latched in parallel by the latch circuit 10. Immediately after the latch trigger signal TL, an output permission signal D1 having a pulse width of TI is supplied via the drive circuit 3iC terminal 4, as shown in FIG. 2(C). As a result, the drive circuit 3 changes the switching gate to P only when the latch circuit 10 gives "1" as a recording signal, that is, black information.
The heating resistor 1 is turned on for a period of time 1 to energize the heating resistor 1.

10,000, the contents of the shift register 11 are the latch circuit 10
Even after being latched by , the transfer operation is performed by the clock pulse CP, and the contents are serially read out from the 11th final stage. During this readout, as shown in FIG. 2(d), the timing control terminal 71C is manually supplied with the timing signal S2 at the "1" level. , the clock pulse Cp v is similarly compared with the recording signal serially read out from the shift register 12 at the gate 21 . That is, the recording signal of the i+1th line read from the shift register 11 and the recording signal of the i+2th line read from the shift register 12 are transmitted to the gate 21.
In the output of the gate 21, only the bit that is IIJ (black information) in the 1st+1st line and the i+2nd line becomes "1", and in all other cases, it becomes "1".
0'', passes through the gates 14 and 15, and is read into the shift register 11 again by the clock signal ePvc.

At the same time, while the "1" level timing signal S2 is continuously input to the timing control terminal 7, the recording signal of the i+2th line stored in the shift register 12 passes through 16.18. and clock signal cp
It is read into the shift register 12 again from K.

Therefore, at the end of the timing signal S2, the contents of the shift register 11 are sequentially replaced with the values obtained by comparing the information on the i+1st line and the 1+2nd line at the gate 21,
On the other hand, as for the contents of the shift register 12, the information of the i+2th line is inputted again.

When all the contents of the shift register 11 are directly converted by the output of the gate 21, the contents of the shift register 11 are latched by the latch trigger signal TL as shown in FIGS. 2(b) and 2(c), and then By supplying the output permission signal RI to the drive circuit 3, the heating resistor 1 is made to energize. At this time, the pulse width of the output permission signal 1) is T2 ('f's<T1). be. Therefore, the i-th
The energization time of the Xi+t line to the heating resistor 1 corresponding to the dot for which the image signal of the +1st line and the i+2th line is "1" (black information) is (T1+'l"2) The image signal of the i+1th line is " 1”, the 1 mark signal on the i+2th line is “0” (
11 to the corresponding heating resistor 1
The energization time of the +t line is TI.

Figure 3 shows these atoms. (a) shows an example of the change in information of the same pit in a recording signal for several consecutive lines, and (b) shows the change in the information on the heating resistor corresponding to the pit. Indicates the energization time.

As described above, according to the present invention, when rlJtrOJ appears sequentially in the same pit of a recording signal, "0" immediately after "1"
” The trailing phenomenon that occurs on the recording corresponding to the signal is “0”
When obtaining a print corresponding to the "1" signal just before the "1" signal, the signal after one time of the energization time given to the corresponding heating resistor is also "1".
When T1 is shorter than the energization time (Tl+Tz) when ``[T5]'', this can be prevented by appropriately setting the value of TI.

Note that the present invention can be implemented with various modifications as follows. That is, in the previous embodiment, the energization time was controlled according to the comparison result between the current recording signal information for one line and the recording signal information for one line after one time, but by adding the third storage circuit, The comparison may be performed including the recorded signal information two or more times later, and the energization time may be controlled according to the comparison result.

Furthermore, although the energization time was controlled by whether the number of energizations was one or two times, the energization time may be controlled in three or more stages by dividing the number of energizations into three or more times.

Figure 4 shows the recorded signal information of the current line after 1 time and after 2 hours.
This is an example in which the energization time is controlled in three stages by comparing with the recorded signal information after the time, (a) shows an example of the change in the information of the same bit in the recording signal for several consecutive lines, and (b) ) corresponds to that pit.When the recorded signal information after 1 time and 2 hours are both "1", the energization time of the current line is TI +T2+Tz, and if the recorded information of the current line is "1", then the recorded information after 1 time is is "1" and the recorded information after 2 hours is rOJ, the current line energization time TI + T2 The recorded information on the current line is "1" and the recorded information 1 time later is 1
0'', the energization time of the current line is T (regardless of the information recorded two hours later).

As explained above, the present invention provides an apparatus that is capable of high-speed recording and also enables thermosensitive recording without trailing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of a thermal recording device according to the present invention, FIGS. 2 and 3 are time charts for explaining its operation, and FIG. 4 is a diagram showing the operation of another embodiment of the present invention. It is a time chart for explanation. 1... Heat generating resistor, 3... Drive circuit,
1o...Latch circuit, 11...Shift register (first storage circuit), 12...Shift register (second storage circuit).

Claims (1)

[Claims] It stores heating resistors arranged in parallel in a row, a drive circuit that selectively energizes these heat generating resistors in accordance with a series of recording signals, and a series of recording signal information to be supplied to these drive circuits. a first storage circuit), a second storage circuit that stores a series of recorded signal information at least one time after the storage signal information stored in this storage circuit, and these first and second storage circuits. A comparison circuit compares the recorded signal information stored in the memory for each corresponding bit, and the comparison result of this comparison circuit determines that the heating resistors are not energized at least one time after the current time, and are not energized at the current time. The heat-sensitive thermosensitive device is characterized in that it is equipped with an energization time control means for controlling the energization time to be shorter than when energization is performed at the current time by energizing at least one time later when the energization is performed at the current time. Recording device.