JP2001008162A - Video edit method and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance quality of an image in the case of compressing or expanding the image in a vertical direction by dividing an image pattern of one frame into a plurality of sub image patterns and storing video data belonging to the same sub image pattern to a same row address of a memory so as to use a conventional image memory without increasing the scale of the device. SOLUTION: Data are written in a memory by dividing data into 24 blocks per one line. One block includes 30 samples. In the case of writing Y samples to the memory, first a load address enable signal (RAS) of the memory is fallen into an L level and a row address 21 is outputted in a timing when the RAS is set to L. Then a column address enable signal (CAS) is fallen to an L for each clock. Data of column addresses 22-0 to 22-9 are sequentially addressed to addresses in a timing when the CAS is set to L. The Y samples are given and stored in the memory in a timing when the data of the column addresses are given to the addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video editing apparatus and method for editing digital video data, and more particularly to a video editing apparatus and method suitable for non-linear editing for editing a plurality of material data on a computer. .

[0002]

2. Description of the Related Art In recent years, video editing apparatuses have been developed which perform image processing such as enlargement or reduction of video data and edit the image data. In such a video editing apparatus, a video signal is converted into digital video data, and image processing such as filtering is performed on the digital video data to perform editing such as enlargement or reduction.

FIG. 26 shows a conventional video editing apparatus.
This will be described with reference to FIG. FIG. 26 is a block diagram showing a configuration of a conventional video editing device. In FIG. 26, digital video data input to the video editing apparatus is converted into a luminance signal sample (hereinafter, referred to as Y sample) and two color difference signal samples (hereinafter, referred to as CR sample and CB sample) in a YC extraction circuit 202. Decomposed. Decomposed Y
The sample is delayed one line at a time by the two line buffers 203, 203, respectively. Original Y sample and 1
The Y sample delayed by two lines and the Y sample delayed by two lines are input to the vertical filter 204, where processing such as compression and expansion in the vertical direction is performed.

Similarly, processing such as compression and decompression in the vertical direction is performed on CR samples and CB samples by two line buffers 203 and 203 and a vertical filter 204, respectively. Y output from the vertical filter 204
The sample, the CR sample, and the CB sample are input to each horizontal filter 205, and each of them is subjected to horizontal compression and expansion processing. The output from each horizontal filter 205 is input to a YC assembling circuit 206, which assembles and outputs a digital video signal.

In a conventional video editing apparatus, digital video data is transmitted in units of lines. For this reason, in the conventional video editing device, processing in line units,
For example, horizontal shifting, compression or decompression processing was feasible. However, in the conventional video editing apparatus, the number of taps of the vertical filter 204 in the vertical direction is small, so that it is not possible to maintain a sufficient video quality for vertical compression and expansion. In addition, it is possible to increase the number of taps of the vertical filter substantially by increasing the number of stages of the line buffer to improve the image quality, but in that case, the scale of the line filter becomes large and the manufacturing cost increases. There was a problem that becomes high. In this conventional video editing apparatus, only compression and decompression processing is performed in the vertical direction. To perform processing such as image shift, it is necessary to additionally connect a device for performing the processing. was there.

Next, a conventional video editing apparatus having a configuration different from the above will be described with reference to FIG. FIG. 27 is a block diagram showing a conventional video editing apparatus using an image memory. In FIG. 27, digital video data input to the video editing apparatus is temporarily stored in a memory 220 constituted by a dynamic RAM. The editing circuit 221
It has image processing circuits such as a vertical filter, a horizontal filter, a vertical shifter, and a horizontal shifter.
3 to read and process samples of digital video data stored in the memory 220. For example, when the editing circuit 221 performs processing in the horizontal direction, the editing circuit 221 instructs the address control circuit 223 to read out each sample stored in the memory 220 in the horizontal direction. Address control circuit 22 that received the instruction
3 controls the address of the memory 220 so that the stored samples are read out in the horizontal direction. The editing circuit 221 performs a process such as filtering on the sample output from the memory 220, and writes the sample into the memory 220 again. At this time, each sample is stored in the memory 220 in the order of the input digital video data.

A general dynamic ram has a two-dimensional structure in which memory cells are composed of rows and columns. Access to the same row address is fast, but access to different column addresses is slow. FIG.
Is an example in which digital video data is mapped to the memory 220. In FIG. 28, the digital video data of this example has 480 lines and 720 columns of video data. One line of samples is mapped to one row address. In this case, reading or writing of one line can be performed continuously.
That is, 720 samples can be read at 722 clocks, including overhead reading. Here, it is assumed that the reading of the overhead can be performed in one clock by the precharge and the designation of the row address.

In order to perform a vertical process on the memory 220, if it is attempted to continuously read samples in the same column, continuous reading is performed because the row addresses of the samples in each line are all different. Could not do. To read one sample, three clocks including overhead are required. Therefore, in order to read all the samples of one frame (480 lines, 720 columns) from the memory 220 and further write the samples, the number of clocks shown in the following equation (1) was required.

[0009] 720 x 480 x 3 = 1036800 (clock) (1)

Since it is necessary to read 30 frames per second for digital video data of a moving image, a clock of 30 MHz or more is required as a memory clock. 27 MHz, which is an input / output clock of a normal digital video signal, could not cope. As a result, in order to edit such a video, a high-speed memory and a clock rate conversion circuit are required, and there has been a problem that the configuration of the apparatus becomes large and the apparatus becomes expensive.

[0011]

As described above,
The conventional video editing apparatus shown in FIG. 26 has a problem that the quality of an image during compression and expansion in the vertical direction is low. In order to improve the quality of this image, many line buffers are required and the scale is large. Therefore, there is a problem that the manufacturing cost is increased. Further, the conventional video editing apparatus shown in FIG. 27, which performs editing using an image memory, has a problem that access to the memory is slow and a high-speed memory is required to edit a moving image. The object of the present invention is
It is an object of the present invention to provide a video editing apparatus and a video editing method capable of improving the quality of an image at the time of compression and expansion in the vertical direction using a normal image memory without increasing the scale of the apparatus.

[0012]

A video editing method according to the present invention is a video editing method for editing digital video data, in which a screen of one frame of digital video data is divided into a plurality of sub-screens. Dividing a memory address into a row address as an upper address and a column address as a lower address, and storing digital video data of the same sub-screen in the one frame at the same row address in the memory; Accessing digital video data in the memory using an address. According to the video editing method described above, digital video data in a high-definition mode can be written and read using a memory having a normal number of clocks.

According to another aspect of the present invention, there is provided a video editing method in which one sample of digital video data for one pixel is n bits, and has a luminance signal sample and two color difference signal samples. A storing step of storing the digital video data in a memory having a data width of 4n bits; in the storing step, a luminance signal sample and two color difference signal samples are stored at the same address of the memory; According to the video editing method described above, a luminance signal sample and two chrominance signal samples are stored in one address of a memory having a data bit width of 4n bits, and a high-definition mode in a high-resolution mode is stored using a memory having a normal number of clocks. Image data can be written and read. as a result,
A video editing apparatus using an image memory with high image quality at the time of compression and expansion in the vertical direction can be realized using an ordinary memory.

Further, in the video editing method according to the invention according to another aspect, a luminance signal sample and two chrominance signal samples are divided for each sample of digital video data, multiplexed for each line, and multiplexed for each line. Stream) and two color difference signal streams (CR stream and CB stream), and a first step of forming a Y1 stream composed of Y1 samples obtained by editing the Y stream line by line. Editing process, C in which the CR stream is edited line by line
A second editing step of forming a CR1 stream composed of R1 samples, a third editing step of forming a CB1 stream composed of CB1 samples obtained by editing the CB stream line by line, the Y1 stream and the CR1 stream And a first accumulation step of accumulating the CB1 stream in the memory. The Y1 'stream composed of the Y1 samples of the same column address output in the first accumulation step is edited for each column address, and the A fourth editing step of forming the composed Y2 stream, a CR1 'stream composed of CR1 samples of the same column address output in the first accumulation step is edited for each column address, and composed of CR2 samples. Fifth Forming the Generated CR2 Stream Editing step, the CB1 'stream constituted by CB1 samples of the same column address outputted in the first accumulating process by editing each column address, which is constituted by CB2 Sample CB2
A sixth editing step of forming a stream, a second storage step of storing the Y2 stream, the CR2 stream, and the CB2 stream in a memory, and a Y2 sample of the same line output in the second storage step. And a CB2 'stream composed of a CB2 sample and a CR2' stream composed of CR2 samples, and the Y2 sample, the CR2 sample, and the CB2
An assembly process for multiplexing and outputting samples is provided. According to the video editing method described above, image data in the high-definition mode can be written or read using a memory having a normal number of clocks, and as a result, the image can be compressed or decompressed in the vertical direction. A video editing device using a high-quality image memory can be realized using a normal memory.

A video editing apparatus according to the present invention is a video editing apparatus for editing digital video data. The video editing apparatus includes a dividing circuit for dividing a screen of one frame of digital video data into a plurality of sub-screens, and a memory address. A storage circuit for dividing digital image data of the same sub-screen in the one frame into the same row address of the memory, divided into a row address as an upper address and a column address as a lower address; And the column address is used to access the digital video data in the memory. According to the video editing apparatus having the above-described configuration, digital video data of a high-definition mode moving image can be written or read using a memory having a normal number of clocks.

According to another aspect of the present invention, there is provided a video editing apparatus in which one sample of digital video data for one pixel is n bits and has a luminance signal sample and two color difference signal samples. The digital video data includes a memory having a data width of 4n bits, and is configured to store a luminance signal sample and two color difference signal samples at the same address of the memory. According to the video editing apparatus having the above configuration, a luminance signal sample and two color difference signal samples are stored in one address of a memory having a data bit width of 4n bits, and a high-definition memory is used by using a memory having a normal clock number. Mode image data can be written and read. As a result, it is possible to realize a video editing apparatus using an image memory with high image quality at the time of vertical compression and expansion using a normal memory.

Further, a video editing apparatus according to another aspect of the present invention is configured such that a digital signal is divided into a luminance signal sample and two chrominance signal samples for each sample of digital video data, multiplexed for each line, and multiplexed for each line. Stream) and two color difference signal streams (referred to as a CR stream and a CB stream), and a first circuit for forming a Y1 stream composed of Y1 samples obtained by editing the Y stream line by line. Editing circuit, C obtained by editing the CR stream line by line
A second editing circuit that forms a CR1 stream composed of R1 samples, a third editing circuit that forms a CB1 stream composed of CB1 samples obtained by editing the CB stream line by line, the Y1 stream and the CR1 stream And a first storage circuit for storing the CB1 stream in the memory, and a Y1 'stream composed of Y1 samples of the same column address output from the first storage circuit, edited for each column address, and A fourth editing circuit for forming the configured Y2 stream, a CR1 'stream composed of CR1 samples of the same column address output from the first storage circuit and edited for each column address, and composed of CR2 samples. Fifth Edit Round Forming the Performed CR2 Stream A sixth editing circuit that edits, for each column address, a CB1 ′ stream composed of CB1 samples of the same column address output from the first storage circuit to form a CB2 stream composed of CB2 samples; A second storage circuit for storing the Y2 stream, the CR2 stream, and the CB2 stream in a memory, and a Y2 ′ stream and a CR2 sample composed of Y2 samples of the same line output from the second storage circuit; Done C
C composed of R2 'stream and CB2 samples
It has an assembling circuit that receives the B2 ′ stream, multiplexes the Y2 sample, the CR2 sample, and the CB2 sample for each sample and outputs the result. According to the above-described video editing apparatus, it is possible to write and read high-definition mode image data using a memory having a normal number of clocks. As a result, it is possible to realize an inexpensive video editing apparatus using a normal image memory having high image quality at the time of vertical compression and expansion.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a video editing apparatus according to the present invention will be described below with reference to the accompanying drawings.

Embodiment 1 A video editing apparatus according to Embodiment 1 of the present invention will be described with reference to FIGS.
FIG. 1 is a block diagram illustrating a configuration of the video editing apparatus according to the first embodiment. In the first embodiment, the format of digital video data input from the outside is SMPTE 125M
Shall be stipulated. SMPTE 125M is CCIR Re
A format for transmitting digital video data according to comendation 601.

FIG. 2 is a diagram showing the structure of digital video data of SMPTE 125M. As shown in FIG. 2, one frame of video in this format is composed of two fields 21 and 22. The luminance signal of field 21 (hereinafter referred to as Y sample) is scanned by 232 lines, and each line is sampled into 858 pixels. The two color difference signals (CR and CB samples) in the field 21 are similarly scanned by 232 lines, and each line is sampled by 429 pixels.

Similar to field 21, field 22
Are scanned over 233 lines, each sampled at 858 pixels. Also, the CR sample and CB sample in field 22 are:
Similarly, scanning is performed with 233 lines, and each line has 429 lines.
Pixels are sampled into pixels. One frame of digital video data is sequentially transmitted in field order and line order. Each sample of one line is transmitted in the order of CB sample, Y sample, CR sample, and Y sample. Each sample in one line is divided into valid pixels and samples in horizontal retrace. Immediately before the first effective pixel in one line, the SAV signal (Start of Active Vide
o), and an EAV signal (End of Active video Signal) is arranged immediately after the last valid pixel sample.

In FIG. 1, a YC extraction circuit 1 converts input digital video data into Y samples, CR samples,
The sample is divided into CB samples, the Y sample of the effective pixel is output to the memory 2, the CR sample of the effective pixel is output to the memory 3, and the CB sample of the effective pixel is output to the memory 4.
At this time, the YC extraction circuit 1 outputs each sample to each of the memories 2, 3, and 4 while maintaining the order of the samples in the input digital video data.

FIG. 3 is a diagram showing a memory map of the memory 2 in the video editing apparatus according to the first embodiment. Here, the memory 2 is composed of a so-called dynamic ram that divides an address into a row address as an upper address and a column address as a lower address and inputs the divided addresses. It has 10 bits as a column address space and 10 bits as a row address space. In FIG. 3, 900 data from the column address 0 to 899 of the row address 0 are defined as a block 0 (B000). Hereinafter, column address 0 from row address 1 to row address 383
Each of the 900 pieces of data from to 899 is stored in block 1 (B
001) to block 383 (B383). These blocks 0 to 383 are referred to as bank 0.
Similarly, 900 data from column address 0 to 899 of the next row address 512 are stored in block 0 (B00
0). Hereinafter, 90 of column addresses 0 to 899 from the row address 513 to the row address 895 will be described.
Each of the 0 data is transferred from block 1 (B001) to block 3
83 (B383). Block 0 to block 383 from these row addresses 512 are referred to as bank 1.

FIG. 4 is a diagram showing a division state of effective pixels of one frame of digital video data in the YC extraction circuit 1 of the video editing apparatus according to the first embodiment. The YC extraction circuit 1 according to the first embodiment has 720 effective pixels in one line.
20 samples are divided into 24 blocks, and 480 samples, which are 480 effective lines, are divided into 16 blocks. As shown in FIG. 4, the divided blocks are numbered from left to right in the figure and further from top to bottom. In FIG. 4, the upper left block is block 0
(B000), the block on the upper right is block 23 (B02
3), the lower left block is block 360 (B360), and the lower right block is block 383 (B383). The Y sample of each block on the screen divided in this way is
It is stored in the corresponding block in the memory 2.

FIG. 5 is a diagram showing the structure of one divided block. FIG. 5A shows one block, and FIG. 5B shows the configuration of one block. As shown in FIG. 5, one divided block is 90 blocks.
It is composed of 0 (30 samples × 30 lines) samples, and each sample P is numbered. As shown in FIG. 5, one block is composed of 30 vertical lines and 30 horizontal lines.
The sample P (m,
(y, x) indicates line x and sample y of block m. Here, the line x is a line number counted from the top in the block, and the sample y is a sample number counted from the left in the block.

FIG. 6 is a diagram showing a memory map in the memory 2 in the video editing apparatus according to the first embodiment of each sample of the divided block m (Bm) shown in FIG. As shown in FIG. 6, the samples of the divided block m are all mapped to the row address m of the memory 2. The column address uses 0 to 899, assigns 0 to the sample at the upper left of the screen, and further assigns samples in the horizontal direction.
After allocating one line, it is sequentially allocated to the line one line below. Memory 3 for storing CR samples, CB
In the memory 4 for storing the samples, the respective memory mapping is performed in the same manner. However, since the number of CR samples and CB samples is 360 samples, which is half of the number of Y samples in one line, the number of blocks in the horizontal direction of the screen is 12 each.

The Y sample digital video data is read from the memory 2 and input to the editing circuit 5. The editing circuit 5 performs image processing such as filtering, shifting, and the like on the input Y sample data string, and outputs the result to the memory 8. At this time, if the editing performed by the editing circuit 5 is processing for a line, for example, compression or expansion in the horizontal direction of the screen, the address control circuit 11 sequentially outputs the addresses of the Y samples of each line to the memory 2 and simultaneously outputs the addresses. Activate the enable signal. As a result, the memory 2 outputs Y samples of each line. The editing circuit 5 performs image processing such as compression, expansion, or shift on the Y samples of each line output from the memory 2 and outputs the processed Y samples to the memory 8. The address control circuit 11 controls the address of the memory 8 and the write enable signal so that the edited Y sample output from the editing circuit 5 is recorded in the memory 8.

If the editing performed by the editing circuit 5 is processing for a column of the screen, for example, compression or expansion in the vertical direction of the screen, the address control circuit 11 sequentially stores the addresses of the Y samples of each column on the screen in the memory 2. Output, and at the same time, activates the output enable signal. As a result, the memory 2 sequentially outputs the Y samples of each column. The editing circuit 5 performs image processing such as compression, expansion, or shift on the Y samples for each column output from the memory 2,
Output to the memory 8. The address control circuit 11 controls the address of the memory 8 and the write enable signal so that the edited Y sample output from the editing circuit 5 is recorded in the memory 8.

If the editing performed by the editing circuit 5 is a screen shift process, the address control circuit 11 performs the reading start position of the address of each Y sample on the screen from the screen position to be shifted. The editing circuit 5 generates data at a screen position where no Y sample exists, and outputs the data to the memory 8 together with the shifted Y sample. If the editing performed by the editing circuit 5 is the rotation of the screen, the address control circuit 11 controls the address of the memory 2 so as to read the Y sample according to the rotation angle given from the memory 2. Editing circuit 5
Performs processing such as filtering on the input Y sample and outputs the result to the memory 8. The processing of compression, expansion, shift, rotation, and the like of these Y samples can be performed in combination.

Similarly, for the CR samples stored in the memory 3, the address control circuit 11 controls the address of the memory 3 and the read enable signal. The editing circuit 6 reads a CR sample from the memory 3 and edits the CR sample. Further, the address control circuit 1
1 controls the address of the memory 9 and the write enable signal, so that the CR sample edited by the editing circuit 6 is written into the memory 9 and the CR sample is subjected to editing processing such as compression, decompression, shift, and rotation. Similarly, the address control circuit 11 controls the address of the memory 4 and the read enable signal with respect to the CB samples stored in the memory 4. The editing circuit 7 reads the CB sample from the memory 4 and edits the CB sample in the editing circuit 7. Further, the address control circuit 11 controls the address of the memory 10 and the write enable signal, and writes the CB sample edited by the editing circuit 7 to the memory 10 to edit the CB sample such as compression, expansion, shift, rotation, etc. Processing is performed.

The address control circuit 11 is connected to each of the memories 8,
By controlling the addresses 9 and 10 and the read enable signal, samples are read from the memories 8, 9 and 10 and output to the YC assembly circuit 12. YC assembly circuit 1
2 assembles each input sample into a digital video signal and outputs it. As described above, according to the video editing apparatus of the first embodiment, it is possible to edit input digital video data and output it as a digital video signal.

In the SMPTE 125M format, one frame of data is composed of 525 lines of data.
One line of data consists of 858 samples. Where C
Since the sampling frequency of the R sample and the CB sample is half of the frequency of the Y sample, the total amount of data in one frame is 900,900 samples. Accordingly, the memories 2, 3, 4, 8, 8 in the video editing apparatus of the first embodiment
9 and 10 indicate that writing and reading of at least 900 900 samples of data are performed for one frame period (33.37 m).
s). Further, since each data is transmitted by a 27 MHz data clock, it is required to operate the entire system at 27 MHz from the point of synchronization.

Writing of data to the memory 2 is performed by dividing into 24 blocks per line. One block contains 30 samples, and writing one block takes 32 clocks. FIG. 7 is a timing chart of writing data of the Y sample to the memory 2 in the video editing apparatus according to the first embodiment. In FIG. 7, writing of data on line 0 is performed by dividing into 24 blocks, and one block includes 30 samples. Hereinafter, the writing of the Y sample to the memory 2 will be described. As shown in FIG. 7, first, a row address enable signal of the memory 2 (hereinafter referred to as Row Addres
s Enable Signal: described as RAS) and set to L. At the timing when RAS is set to L, the row address 21 is output to the address. The address 0 in FIG. 7 is a row address for recording block 0.

Thereafter, a column address enable signal (hereinafter, referred to as CAS) falls to L at each clock. At the timing when CAS is set to L, 0 to 0 of the column address 22
Up to 29 are sequentially output. 0 to 29 in address
Is a column address for recording the first 30 samples. At the timing when the column address is input to the address, the Y sample is input to the memory 2 and recorded. After the Y sample at address 29, which is the last CAS, is input, the RAS is raised to H, so that 3
Writing 32 samples requires 32 clocks.
Also, since one line has 24 blocks, writing 768 clocks is required for writing the Y sample of one line. Also, since one frame is composed of 480 lines,
368640 clocks are required to write a frame.

Next, considering the writing of the line m in the writing of the Y sample into the memory 2 as described above, the nth input row address RAn is represented by the following equation (2).

RAn = m / 30 + n (2)

Hereinafter, "/" indicates integer division (rounded down to the nearest whole number). The column address CAmp input to the p-th write in the n-th block in the write of the line m is represented by the following equation (3).

CAmp = m mod 30 × 30 + p (3)

In the equation (3), m mod 30 is
Indicates a remainder obtained by dividing m by 30, and has the same meaning in the following equation. Next, the timing when the Y samples stored in the memory 2 are read in the vertical direction for each column will be described. Reading of column 0 is performed for each line divided into 16 blocks. One block contains 30 samples. First, the RA of the memory 2
S is dropped to L. At the timing when RAS is set to L, the row address 21 is output to the address. The address 0 in FIG. 7 indicates a row address from which block 0 is read. After that, CAS falls to L every clock. At that timing, the column address 22
Is output. After CAS is set to L, the data of the corresponding address is output from the memory 2. Finally, since RAS rises to H, 32 clocks are required to read 30 samples. Since one line has 16 blocks, reading one line requires 512 clocks. Also, since one frame consists of 720 columns,
Reading one frame requires 368640 clocks.

Next, when reading the column m in reading the Y sample from the memory 2 as described above, the nth input row address RAn is expressed by the following equation (4).

RAn = m mod 30 + n × 30 (4)

The column address CAmp input to the p-th of the n-th block read of the column m read is:
It is represented by the following equation (5).

CAmp = m mod 30 + p × 30 (5)

As described above, in the video editing apparatus of the first embodiment, writing and reading of one
It requires 280 clocks. The number of clocks is 27 MH
Since the number of clocks in one frame period of the system operated by the data clock of z is less than 900900, the video editing apparatus according to the first embodiment is realized as a system. Next, the reading in the horizontal direction for each line will be described. The horizontal reading for each line is performed at the same timing as the writing for each line. In this read operation, the sample is read from the memory 2 instead of the operation of writing the sample performed in the above-described write operation to the memory 2. At this time, the address output to the memory 2 complies with the above-described equations (2) and (3) as in the case of writing. The required number of clocks at this time is 3
Since it is 68640 clocks, writing and reading can be performed sufficiently within one frame period even if reading is performed in the horizontal direction for each line.

The memory 8 may be written by the editing circuit 5 line by line or column by column. Both timings are the same as those of the memory 2 for reading line by line and writing column by column. . When outputting from the memory 8 to the YC assembly circuit 12,
Reading is performed line by line. In this case, the timing is the same as when reading is performed for each line of the memory 8. Therefore,
The memory 8 can also operate at a clock frequency of 27 MHz. Regarding the memory 3 for processing the CR sample, the editing circuit 6, the memory 9, and the memory 4, the editing circuit 7, and the memory 10 for processing the CB sample, the number of samples in the line direction is 360 times smaller than that of the memory 2.
Other than the sample, the processing is performed in the same manner as the memory 2, the editing circuit 5, and the memory 8 described above.

The YC assembling circuit 12 outputs the input Y sample, CR sample, and CB sample as digital video data. At this time, necessary horizontal blanking and vertical blanking signals are generated, and the signals are synchronized and output at the timing shown in FIG. As described above, according to the video editing apparatus of the first embodiment, it is possible to construct an image editing apparatus that can operate at 27 MHz, which is the same as the clock frequency for inputting and outputting digital video data to and from the memory.

Embodiment 2 Hereinafter, Embodiment 2 according to the present invention will be described.
Will be described with reference to FIGS. 8 to 25. FIG. 8 is a block diagram illustrating a configuration of the video editing apparatus according to the second embodiment. 8, the video editing apparatus according to the second embodiment includes a start detection circuit 101 that generates a start signal from input digital video data, and divides the digital video data into Y samples, CR samples, and CB samples according to the start signal. In addition, it has a YC extraction circuit 102 for dividing one frame of digital video data into 11 in the line direction and 21 in the column direction. As described above, the YC extraction circuit 102 divides a luminance signal stream (hereinafter, referred to as a Y stream) and two color difference signal streams (hereinafter, referred to as a CR stream and a CB stream). The Y stream is composed of a plurality of Y samples in the line direction. Similarly, each CR stream and CB stream are
It is composed of a plurality of CR samples and a plurality of CB samples on the line. The YC extraction circuit 102
The divided samples are connected to horizontal compression circuits 103, 104, and 105 that perform image processing in the horizontal direction on each sample. Each horizontal compression circuit 103, 104, 105 is connected to line buffers 106, 107, 108. The line buffers 106, 107, and 108 are connected to a multiplexing circuit 121 that multiplexes each sample. The multiplexing circuit 121
It is connected to a memory 110 via a data bus 109.

The input / output of the memory 110 is controlled by the memory control circuit 111. The memory 110 is connected to the data bus 1
Vertical compression circuit 1 for performing vertical image processing via
12 is connected. The vertical compression circuit 112 is connected to the column buffer 113. Column buffer 113
Are connected to a memory 115 via a data bus 114. The input and output of the memory 115 are controlled by the memory control circuit 116. The memory 115 is connected to the line buffers 117, 118, 119 via the data bus 114. Line buffers 117, 118 and 119 are Y
It is connected to the C assembly circuit 120.

The operation of the video editing apparatus according to the second embodiment will be described below with reference to FIGS. In the second embodiment, the start detection circuit 101 and the YC extraction circuit 10
The bit width of one sample of the digital video data input to 2 is 10 bits. The start detection circuit 101
A start signal such as a frame head signal and a line head signal is generated from the digital video data, and the start signal is output to the YC extraction circuit 102, the memory control circuit 111, the vertical compression circuit 112, the memory control circuit 116, and the YC assembly circuit 120. I do. The YC extraction circuit 102 divides the input digital video data into Y samples, CR samples, and CB samples according to the input start signal,
Each sample is divided into horizontal compression circuits 103, 104, 1
Output to 05. At this time, the YC extraction circuit 102 simultaneously outputs a write enable signal for each sample.

The horizontal compression circuit 103 performs image processing such as horizontal compression and expansion from the input Y sample,
The sample is converted into one sample, and the Y1 sample is output to the line buffer 106. The horizontal compression circuit 103 outputs to the line buffer 106 the samples other than the pixel samples in the Y samples, that is, the Y samples during the vertical blanking and the horizontal blanking. At this time, the horizontal compression circuit 103 outputs a write enable signal to the line buffer 106 in accordance with the output of the Y1 sample. The Y1 sample output to the line buffer 106 outputs two adjacent samples at the same time. Therefore, the line buffer 106 has a data width of 20 bits and, of the two adjacent samples, the Y buffer on the left side on the screen.
One sample is stored in the upper 10 bits, and the Y1 sample on the right is stored in the lower 10 bits.

Horizontal compression circuit 104 for CR samples
Performs image processing such as horizontal compression and decompression of an input CR sample in the same manner as the horizontal compression circuit 103 for the Y sample, converts the input CR sample into a CR1 sample, and, together with a write enable signal, a line buffer 107. Output to The horizontal compression circuit 105 for CB samples is
The input CB sample is subjected to image processing such as compression and expansion in the horizontal direction, converted into a CB1 sample, and output to the line buffer 108 together with a write enable signal.

Line buffer 106 for Y sample
Temporarily hold the input Y1 sample according to the input write Y enable signal. Similarly, the line buffers 107 and 108 temporarily hold the CR1 sample and CB1 sample respectively input according to the input write CR enable signal and write CB enable signal. The line buffers 106, 107, 108
The Y1 sample, the CR1 sample, and the CB1 sample held in accordance with the read enable signal output from the memory control circuit 111 are output to the multiplexing circuit 121. The multiplexing circuit 121 multiplexes each input sample and outputs the multiplexed sample to the data bus 109.

FIG. 9 is a block diagram showing a multiplexing circuit 121 according to the second embodiment. In this multiplexing circuit 121, the upper 20 bits include the Y1 sample, and the next 10 bits include C1.
The R1 sample is stored in the lower 10 bits, and the CB1 sample is stored. The samples stored as described above are output to the data bus 109. The multiplexed samples output to the data bus 109 are stored in the memory 110. Further, the samples multiplexed in the column direction are read from the memory 110 by the read enable signal output from the memory control circuit 111, and
12 is output.

The memory 110 has a capacity for storing samples for at least two frames. The memory area for the first frame in the memory area for two frames is bank 0, and the memory area for the next one frame is bank 1 And The bit width in the memory 110 is 40 bits. The memory control circuit 111 includes the line buffers 106, 1
07, 108 and the memory 11
Control the address and control signals of 0. As described above, the memory control circuit 111 controls each signal, so that samples for one frame are read out from the line buffers 106, 107, and 108 during a certain one frame period, and
At the same time, the data is recorded as 0, and one frame of data is read from the memory 110 and output to the vertical compression circuit 112 during the same one frame period. The signal generation timing of the memory control circuit 111 follows the start signal output from the start detection circuit 101.

The samples are input to the vertical compression circuit 112 in the order in the column direction. The vertical compression circuit 112 compresses or expands each column, and outputs the compressed or expanded sample to the column buffer 133. However, the vertical compression circuit 112 outputs the sample in the vertical blanking and the horizontal blanking to the column buffer 113 as it is. The vertical compression circuit 112 outputs a sample and outputs a write enable signal to the column buffer 113. These compression and expansion timings operate based on a start signal input from the start detection circuit 101.

The column buffer 113 buffers the sample input when the write enable signal is active. The column buffer 113 outputs the buffered sample to the data bus 114 when the read enable signal is input from the memory control circuit 116. The compressed or expanded Y1 sample of the vertical compression circuit 112 is a Y2 sample, and the CR1 sample is a CR2 sample.
Let the sample and CB1 sample be CB2 samples.

The samples output to the data bus 114 are recorded in the memory 115. Next, samples are sequentially read from the memory 115 in the line direction and output to the line buffers 117, 118, and 119. Memory 1
Reference numeral 15 has a sample capacity of at least two frames, and the first one frame in the memory area for two frames is bank 0, and the next one frame is bank 1.
The bit width in the memory 115 is 40 bits. The memory control circuit 116 controls a read enable signal of the column buffer 113, an address and control signal of the memory 110, and a write enable signal of the line buffers 117, 118, and 119. As described above, the memory control circuit 116 controls each signal so that a certain 1
During one frame period, samples of one frame are read from the column buffer 113 and recorded in the memory 115, and one frame of data is read from the memory 115 during the same one frame period to read out the line buffers 117, 118,
119 is output. The signal generation timing of the memory control circuit 111 follows the start signal output from the start detection circuit 101.

The line buffer 117 is a memory control circuit 1
Y2 input according to the write enable signal of No. 16
Buffer the sample. The line buffer 117 outputs the buffered Y2 sample according to the read enable signal of the YC assembly circuit 120.
Further, the line buffer 118 is connected to the memory control circuit 116.
Buffering the input CR2 sample according to the write enable signal of Also, line buffer 1
Reference numeral 18 outputs the retained CR2 sample in accordance with the read enable signal of the YC assembly circuit 122. Also,
The line buffer 119 buffers the input CB2 sample in accordance with the write enable signal of the memory control circuit 116. Further, the line buffer 119 outputs the held CB2 sample according to the read enable signal of the YC assembly circuit 122. The YC assembly circuit 120 includes line buffers 117, 118, 1
The Y2 sample, the CR2 sample, and the CB2 sample stored in 19 are read, converted into a digital video signal, and output.

FIG. 10 is a diagram showing a memory map of the memory 110 in the video editing apparatus according to the second embodiment. FIG.
In the example, the data width of the memory 110 is 40 bits, the upper 20 bits record two Y1 samples, the lower 10 bits record a CR1 sample, and the lower 10 bits record a CB1 sample. In the memory 110, the bit width of the row address is 8 bits, and the bit width of the column address is 10 bits. The memory for one frame in the memory 110 is divided into 231 blocks. One block occupies one row address and has fields from 0 to 974 in column address. As shown in FIG. 10, the memory 110 has a memory area of two frames, and the memory areas are called a bank 0 and a bank 1, respectively.

As described above, digital video data is
One frame of Y samples has 525 lines, and one line is composed of 858 samples. One frame of the CR sample and the CB sample has 525 lines, and one line is composed of 329 samples. The Y1 sample and the Y2 sample converted from the Y sample, the CR1 sample and the CR2 sample converted from the CR sample, and the CB1 and CB2 samples converted from the CB sample have the same configuration. Hereinafter, each sample in column x and line y is referred to as Y (x,
y), CR (x, y) and CB (x, y).

The digital video data of one frame is divided into 11 in the line direction and 21 in the column direction. FIG.
FIG. 1 is a diagram showing an arrangement of divided blocks in the memory 110. As shown in FIG. 11, the divided blocks are sequentially numbered from left to right and further from top to bottom. In the memory 110, digital video data of a corresponding block number is recorded. In FIG. 11, one block includes 78 Y1 samples in the line direction and 39 C1 samples.
It consists of R1 and CB1 samples, and the column direction is 21
It consists of samples. In the following description, one sample in a block m (Bm) is referred to as P (m, x, y).
Is displayed. The sample represented by P (m, y, x) includes two Y1 samples, a CR1 sample, and CB1.
Samples are stored.

For example, if y is an even number, P (m, y,
x) includes Y1 (m, y / 2 + 233, Δm × 39 +
x｝ × 2) and Y1 (m, y / 2 + 233, ｛mx39)
+ X｝ × 2 + 1) and CR1 (m, y / 2 + 233, m
× 39 + x) and CB1 (m, y / 2 + 233, m × 3
9 + x) are stored. Further, if y is an odd number, P (m, y, x) contains Y1 (m, y /
2, {m × 39 + x} × 2) and Y1 (m, y / 2,
{M × 39 + x} × 2 + 1) and CR1 (m, y / 2,
m × 39 + x) and CB1 (m, y / 2, m × 39 +
Four samples of x) are stored. Also, m, x, y
Satisfies 0 ≦ m <231, 0 ≦ x <39, and 0 ≦ y <25.

FIG. 12 is a diagram showing the arrangement of each sample in the block m of the memory 110. Here, the block m is recorded at the row address m of the memory 110. P
The column address C for recording (m, y, x) is represented by the following equation (6).

C = x × 39 + y (6)

The column address 975 and thereafter are not used. FIG. 13 is a block diagram showing a configuration of the YC extraction circuit 102. In FIG. 13, the input digital video data is used as it is as a Y sample in the horizontal compression circuit 10.
3, to the horizontal compression circuit 104 as a CR sample,
The data is output to the horizontal compression circuit 105 as a sample. The start signal input from the start detection circuit 101 is input to the counter 130 of the YC extraction circuit 102. The counter 130 is a 2-bit counter, and the count is incremented by one every clock using a start signal as a trigger signal. The value of the counter 130 is output to the Y enabler 131, the CR enabler 132, and the CB enabler 133 in the YC extraction circuit 102.

FIG. 14 shows the digital video data input to the YC extraction circuit 102 and the horizontal compression circuits 103, 10
4 and 105 and each enabler 1
It is a figure which shows the output timing of enable signals etc. which are output from 31, 132, 133. As shown in FIG. 14, the Y enabler 131 outputs a Y enable signal to the horizontal compression circuit 103 when the counter is 1 or 3. The CR enabler 132 outputs a CR enable signal to the horizontal compression circuit 104 when the counter is 2. CB
The enabler 133 outputs a CB enable signal to the horizontal compression circuit 105 when the counter is 0.

FIGS. 15A, 15B and 15C are block diagrams showing the configurations of the horizontal compression circuits 103, 104 and 105, respectively. In FIG. 15A, the horizontal compression circuit 103 extracts a Y sample from the input digital video data having the Y sample and the Y enable signal, and compresses it in the line direction by the filter 141 according to a parameter given in advance. Alternatively, perform stretching.
In the filter 141, the compressed or expanded Y1
The sample is output to the Y assembly circuit 14 together with the Y enable signal.
2 is output. The Y assembling circuit 142 multiplexes two adjacent Y1 samples and outputs the multiplexed sample to the line buffer 106 together with the write Y enable signal. The horizontal compression circuit 103 outputs the input Y1 sample to the line buffer 106 as it is for the horizontal blanking and vertical blanking samples.

In FIG. 15B, the horizontal compression circuit 1
Reference numeral 04 extracts a CR sample from the input digital video data having the CR sample and the CR enable signal, and performs compression or expansion in the line direction by the filter 143 according to a parameter given in advance. The compressed or decompressed CR1 sample is
Output to the line buffer 107 together with the enable signal. The horizontal compression circuit 104 outputs the input CR1 sample to the line buffer 107 as it is for the horizontal blanking and vertical blanking samples.

In FIG. 15C, the horizontal compression circuit 1
Reference numeral 05 extracts a CB sample from the input digital video data having a CR sample and an enable signal, and performs compression or expansion in the line direction according to a parameter given in advance. CB1 compressed or expanded
The sample is output to the line buffer 108 together with the write CB enable signal. The horizontal compression circuit 105
For the samples of horizontal blanking and vertical blanking, the input CB samples are output to the line buffer 108 as they are.

FIG. 16 is a block diagram showing a configuration of the memory control circuit 111. In FIG. 16, the counter 51
Is a counter that increments (counts up) the input start signal for each clock to form a counter value. The counter value of the counter 51 is output to a row address decoder 52, a column address decoder 53, and an enable control circuit 55. The row address decoder 52 generates a row address of the memory 110. In the column address decoder 53, a column address of the memory 110 is generated. The generated row address and column address are multiplexed by the address multiplexing circuit 54 and output to the address input terminal of the memory 110 (FIG. 8). The enable control circuit 55 outputs an output enable signal OE of the memory 110, a write enable signal WE, a row address enable signal RAS, a column address enable signal CAS, and a read enable signal to the line buffers 106, 107 and 108 from the input counter value. Generate each.

FIG. 17 is a timing chart showing writing of one line of the memory 110. One line of data is recorded over 11 blocks. Here, 1
The writing of a block will be described. In one block, 39 samples of the same line are recorded. Since these 39 samples are arranged at the same row address, burst writing is possible. In FIG.
First, the row address enable signal RAS falls to L, and the first row address RA0 is output to the address of the memory 110. Thereafter, the column address enable signal CAS is activated every clock, and the column addresses CA0, CA1, CA2,.
・, CA38 is output. Thereafter, the row address enable signal RAS is disabled. After the column address CA38 is output to the address of the memory 110, the column address enable signal rises, and the line buffers 106, 107, 10
By activating the read enable signal of No. 8, data of the same line in one block is output to the data bus 109.

By performing the above processing for 11 blocks, a sample of one line is written to the memory 110. The time required for this writing is 41 clocks for writing one block in the case of a 27 MHz clock,
The time is 16.7 μsec for 11 blocks in one line.
When writing the line m, the n-th row address R
An is represented by the following equation (7).

RAn = m / 11 + n (7)

The p-th column address CAmp of the n-th block is represented by the following equation (8).

CAmp = m mod 11 + p (8)

FIG. 18 is a timing chart for reading samples of two columns from the memory 110. Samples for two columns are distributed over 21 blocks. The reading of one block will be described with reference to FIG. One block contains 2 samples of the same column.
Five are recorded. Since these 25 samples are arranged at the same row address, burst reading is possible. In FIG. 18, first, the row address enable signal RAS falls to L, and the first row address RA0 is output to the address of the memory 110.
After that, the column address enable signal CA
Activate S and column address CA
0, CA1, CA2,..., CA24. Thereafter, the row address enable signal RAS is disabled. Each time the column address enable signal CAS is activated, address data is output from the memory 110 to the data bus 109.

By performing the above processing for 21 blocks, a sample of two columns is read from the memory 110. The time required for this reading is 27 clocks for reading one block in the case of 27 MHz,
In the case of a block, this is 21 μsec. When reading the column m, the n-th row address RAn is expressed by the following equation (9).

RAn = m / 21 (9)

The p-th column address CAmp of the n-th block is represented by the following equation (10).

CAmp = m mod 21 + p (10)

The memory control circuit 111 performs writing of 525 lines and reading of 858 columns during one frame period (33.3 ms). At this time, line writing for one frame and column reading for one frame are performed for different banks, so that rewriting during reading of the same frame does not occur. In addition, the entire screen is shifted in the horizontal direction by shifting the row address and the column address according to a horizontal offset given in advance when reading a column. Specifically, when reading the column m, the offset s is added to m.
And the row address RAn and the column address CA
By performing the operation of mp, it is possible to shift the screen by 2 m columns.

FIG. 19 is a timing chart of the memory control signal for one frame period. First, one frame is 52
Divide into five. One line is written in the first half of the divided period, and two columns are read in the second half. This timing follows the start signal input to the memory control circuit 111.

FIG. 20 is a block diagram showing a detailed configuration of the vertical compression circuit 112. 20, the digital video data input from the data bus 109 is divided into Y1 samples, CR1 samples, and CB1 samples. The column Y1 is further divided into even-numbered samples and odd-numbered samples. The even-numbered (including 0) Y1 samples are supplied to the compression circuit 161 by the odd-numbered Y1 samples.
One sample is output to the compression circuit 162, the CR1 sample is output to the compression circuit 163, and the CB1 sample is output to the compression circuit 164. The vertical compression circuit 112 divides the sample by dividing the most significant 10 bits of the bit field of the data bus 109 into the compression circuit 161, the next 10 bits into the compression circuit 162, and the next 10 bits into the compression circuit 1
63, by inputting the least significant 10 bits to the compression circuit 164.

The compression circuit 161 performs compression or expansion in the column direction based on the input data and the start signal according to parameters given in advance. The compressed or decompressed Y2 sample of the even-numbered column is output to the column buffer 113 (FIG. 8) together with the write enable signal. The compression circuit 162 performs compression or expansion in the column direction from the input data and the start signal in accordance with parameters given in advance. The Y2 samples of the odd-numbered compressed or expanded columns are output to the column buffer 113 together with the write enable signal. The compression circuit 163 performs compression or expansion in the column direction based on the input data and the start signal according to parameters given in advance. The compressed or decompressed CR2 sample is output to the column buffer 113 together with the write enable signal. Compression circuit 16
Reference numeral 4 performs compression or expansion in the column direction from the input data and the start signal in accordance with parameters given in advance. The compressed or expanded CB2 sample is sent to the column buffer 1 together with the write enable signal.
13 is output.

Compression circuits 161, 162, 163, 164
Is the Y2 sample output from the compression circuit 161 at the top of the 40-bit signal to the column buffer, the Y2 sample output from the compression circuit 162 is the next 10 bits, and the next 10 bits. The CR2 sample is multiplexed with the bits and the CB2 sample is multiplexed with the least significant 10 bits and output to the column buffer 113. The column buffer 113 temporarily holds each input sample according to the write enable signal. The memory map of the memory 115 is the same as the memory map of the memory 110 described above.

FIG. 21 is a block diagram showing a detailed configuration of the memory control circuit 116. In FIG. 21, a counter 171 is a counter which receives a start signal and increments (counts up) every clock to form a count value. The counter value of the counter 171 is
The signals are output to the row address decoder 172, the column address decoder 173, and the enable control circuit 175, respectively. In the row address decoder 172, the memory 115
Is generated. The column address decoder 173 generates a column address of the memory 115. The row address and the column address are multiplexed by the address multiplexing circuit 174 and output to the address input terminal of the memory 115.

The enable control circuit 175 determines the output enable signal O of the memory 115 from the input counter value.
E, write enable signal WE, row address enable signal RAS, column address enable signal CAS
Generate The enable control circuit 175 generates a write enable signal for the line buffers 117, 118, and 119 and a read enable signal for the column buffer 113.

FIG. 22 is a timing chart for writing data in two columns of the memory 115. Two columns of data are distributed over 21 blocks. Here, writing of one block will be described. In one block, 25 samples of the same column are recorded. These 25 samples are arranged at the same row address. In FIG. 22, first, the row address enable signal RAS falls to L, and the first row address RA0 is output to the address of the memory 115. Thereafter, the column address enable signal CAS is activated every clock, and the column addresses CA0, CA1, CA2,
... Output CA24. Thereafter, the row address enable signal RAS is disabled. In addition, a read enable signal for the column buffer 113 is output one clock before the column address enable signal CAS is activated so that the address data is output to the data bus 114 every time the column address enable signal CAS is activated. , Data is read from the column buffer 113.

By performing the above processing for 21 blocks, samples of two columns are read from the column buffer 113 and written to the memory 115. The time required for writing to this memory 115 is 2 blocks for one block.
7 clocks, 21 μsec for 21 blocks. When writing the column m, the n-th row address RAn is expressed by the following equation (11).

RAn = m / 21 (11)

The p-th column address CAmp of the n-th block is represented by the following equation (12).

CAmp = m mod 21 + p (12)

FIG. 23 is a timing chart for reading one line of the memory 115. One line of data is recorded over 11 blocks. Here, 1
The reading of the blocks will be described. In one block, 39 samples of the same line are recorded. These 39 samples are arranged at the same row address.
In FIG. 23, first, the row address enable signal RAS falls to L, and the first row address RA0 is output to the address of the memory 115. Thereafter, the column address enable signal CAS is activated every clock, and the column addresses CA0, C
A1, CA2,..., CA38 are sequentially output. Thereafter, the row address enable signal RAS is disabled. Next, the column address enable signal CAS
Are activated and the line buffers 117, 118,.
The write enable signal 119 is activated.
As described above, when the write enable signal becomes active, one block of data output to the data bus 114 is written to the line buffers 117, 118, and 119.

By performing the above processing for 11 blocks, a sample of one line is read from the memory 110,
Writing to the line buffers 117, 118, 119 is performed. The line buffers 117, 118, 119
The time required to write data into a block is 41 clocks for writing one block in the case of a 27 MHz clock, and 11
In the block, it is 16.7 μsec. When reading the line m, the n-th row address RAn is represented by the following equation (13).

RAn = m / 11 + n (13)

The p-th column address CAmp of the n-th block is represented by the following equation (14).

CAmp = m mod 11 + p (14)

The memory control circuit 116 reads 525 lines and writes 858 columns during one frame period (33.3 ms). At this time, line reading for one frame and column writing for one frame are performed for different banks, so that rewriting during reading of the same frame does not occur. In addition, the entire screen is shifted in the vertical direction by shifting the row address and the column address according to a vertical offset given in advance when reading a line. Specifically, when reading out the line m, the screen can be shifted by m lines by adding the offset s to the m and calculating the row address RAn and the column address CAmp.

FIG. 24 is a timing chart of the memory control signal for one frame period. In FIG. 24, first, 1
The frame is divided into 525. One line is read in the first half of the divided period, and two columns are written in the second half. This timing follows the start signal input to the memory control circuit 116.

FIG. 25 is a block diagram showing details of the YC assembly circuit 120. In FIG. 25, the counter 181
Is a counter that increments by one every clock according to the input start signal. Enabler 182
Generates an enable signal for reading Y2 samples, CR2 samples, and CB2 samples from the line buffers 117, 118, and 119 according to the count value of the counter 181.

The luminance conversion circuit 183 is connected to the line buffer 1
The Y2 sample output from 17 is subjected to luminance conversion and output to the selector 186 as a Y3 sample. Color difference conversion circuit 1
84 converts the color space between the CR2 sample output from the line buffer 118 and the CB2 sample output from the line buffer 119, and outputs the result to the selector 186 as a CR3 sample and a CB3 sample. The blanking generation circuit 185 generates horizontal and vertical blanking signals required for digital video data. Selector 18
Numeral 6 assembles and outputs a digital video signal by selecting a Y3 sample, a CR3 sample, a CB3 sample, and horizontal and vertical blanking signals according to the value of the counter 181.

As described above, according to the video editing apparatus of the second embodiment, an image editing apparatus capable of operating at the same 27 MHz as the input / output clock frequency of digital video data can be obtained while maintaining sufficient video quality. It can be constructed without providing special devices.

[0103]

As described above, the present invention has the following effects as described in detail in the embodiments. The video editing method of the present invention comprises:
When one frame screen is divided into a plurality of sub-screens and video data is stored in the memory, video data belonging to the same sub-screen is stored in the same row address of the memory. According to this video editing method, the normal clock frequency of 27 MHz
Image processing such as compression and decompression in the vertical direction and the horizontal direction using the memory described above, and video editing can be performed with high quality. Further, according to the video editing apparatus of the present invention, a filter capable of obtaining a desired quality in processing such as compression and decompression can be configured, and in memory access, burst access in either the line direction or the column direction is possible. In addition, a low-cost video editing device capable of performing a memory operation synchronized with 27 MHz of digital video data can be realized.

[Brief Description of the Drawings]

FIG. 1 is a block diagram of a video editing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a format of an input signal in Embodiment 1 according to the present invention.

FIG. 3 is a memory map of a memory according to the first embodiment of the present invention.

FIG. 4 is a block layout diagram of a screen according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a sample arrangement of divided blocks according to the first embodiment of the present invention.

FIG. 6 is a memory map of a sample according to the first embodiment of the present invention.

FIG. 7 is a timing chart in the memory according to the first embodiment of the present invention.

FIG. 8 is a block diagram of a video editing apparatus according to a second embodiment of the present invention.

FIG. 9 is a block diagram illustrating details of a multiplexing circuit 121 according to a second embodiment of the present invention.

FIG. 10 is a memory map of a memory 110 according to a second embodiment of the present invention.

FIG. 11 is a block layout diagram of a screen according to a second embodiment of the present invention.

FIG. 12 is a memory map of a sample according to the second embodiment of the present invention.

FIG. 13 is a YC extraction circuit 102 according to a second embodiment of the present invention.
FIG. 4 is a block diagram showing the details of.

FIG. 14 is a timing chart of the YC extraction circuit according to the second embodiment of the present invention.

FIG. 15 is a horizontal compression circuit 103 according to the second embodiment of the present invention.
FIG. 4 is a block diagram showing the details of.

FIG. 16 is a memory control circuit 11 according to a second embodiment of the present invention.
FIG. 2 is a block diagram showing the details of No. 1;

FIG. 17 is a timing chart of line writing in the memory 110 according to the second embodiment of the present invention.

FIG. 18 is a timing chart of column reading in the memory 110 according to the second embodiment of the present invention.

FIG. 19 is a timing chart for the data bus 109 according to the second embodiment of the present invention.

FIG. 20 is a vertical compression circuit 112 according to the second embodiment of the present invention.
FIG. 4 is a block diagram showing the details of.

FIG. 21 is a memory control circuit 11 according to a second embodiment of the present invention.
FIG. 6 is a block diagram showing the details of FIG.

FIG. 22 is a timing chart of column writing in the memory 115 according to the second embodiment of the present invention.

FIG. 23 is a timing chart of line reading in the memory 115 according to the second embodiment of the present invention.

FIG. 24 is a timing chart for the data bus 114 according to the second embodiment of the present invention.

FIG. 25 is a YC assembly circuit 120 according to the second embodiment of the present invention.
FIG. 4 is a block diagram showing the details of.

FIG. 26 is a block diagram illustrating a configuration of a conventional video editing device.

FIG. 27 is a block diagram showing a configuration of a conventional video editing device using a memory.

FIG. 28 is a memory map of a memory of a conventional video editing device using a memory.

[Explanation of symbols]

1, 102 YC extraction circuit 2, 3, 4, 8, 9, 10 Memory 5, 6, 7 Editing circuit 11 Address control circuit 12, 120 YC assembly circuit 51, 130, 171, 181 Counter 52, 172 Row address decoder 53 , 173 column address decoder 54, 174 address multiplexing circuit 55, 175 enable control circuit 101 start detection circuit 103, 104, 105 horizontal compression circuit 106, 107, 108, 117, 118, 119 line buffer 109, 114 data bus 110, 115 Memory 111, 116 Memory control circuit 112 Vertical compression circuit 113 Column buffer 121 Multiplexer 130 Counter 131 Y enabler 132 CR enabler 133 CB enabler 141, 143, 144 Filter 142 Y assembly circuit 61,162,163,164 compression circuit 182 enabler 183 luminance conversion circuit 184 color difference conversion circuit 185 blanking generation circuit 186 selector

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) BA01 CA01 ED09 GA02 GA05 GA20 GA31 HA01 KB05 KC08 KC09 KE09 KE12 KE13

Claims (13)

[Claims] 1. A video editing method for editing digital video data, comprising: dividing a screen of one frame of digital video data into a plurality of sub-screens; Storing the digital video data of the same sub-screen in the one frame at the same row address of the memory, and accessing the digital video data of the memory using the row address and the column address; A video editing method, comprising: 2. The digital video data 1 for one pixel.
A storing step of storing 4: 2: 2 digital video data having n bits and a luminance signal sample and two color difference signal samples in a memory having a data width of 4n bits; A luminance signal sample and two color difference signal samples are stored at the same address. 3. A sample of digital video data is divided into a luminance signal sample and two color difference signal samples, multiplexed on a line-by-line basis, and a luminance signal stream (hereinafter, referred to as a Y stream) and two color difference signal streams (CR). Stream, CB stream), a first editing step of forming a Y1 stream composed of Y1 samples obtained by editing the Y stream for each line, and a CR stream edited for each line. A second editing step of forming a CR1 stream composed of CR1 samples, a third editing step of forming a CB1 stream composed of CB1 samples obtained by editing the CB stream line by line, the Y1 stream and the CR1 stream And the CB
A first accumulation step of accumulating one stream in a memory; a Y1 'stream composed of Y1 samples of the same column address output in the first accumulation step, edited for each column address, and composed of Y2 samples. A fourth editing step of forming a Y2 stream, wherein the CR1 ′ stream composed of CR1 samples of the same column address output in the first accumulation step is edited for each column address, and is composed of CR2 samples. A fifth editing step of forming a CR2 stream, a CB1 ′ stream composed of CB1 samples of the same column address output in the first accumulation step, edited for each column address, and a CB2 composed of CB2 samples. A sixth editing step of forming a stream; Ream, the CR2 stream and the CB
A second accumulation step of accumulating the two streams in the memory, and Y of the same line output in the second accumulation step.
Y2 'stream composed of two samples and CR2
CR2 'stream composed of samples and CB2
An image editing method, comprising: assembling a CB2 ′ stream composed of samples, and multiplexing and outputting the Y2 sample, the CR2 sample, and the CB2 sample for each sample. 4. A video editing apparatus for editing digital video data, comprising: a dividing circuit for dividing a screen of one frame of digital video data into a plurality of sub-screens; A storage circuit that divides the digital video data of the same sub-screen in the one frame into the same row address of the memory, and divides the digital video data of the same sub-screen in the one frame into the same row address using the row address and the column address. A video editing device configured to access digital video data in the memory. 5. One digital video data of one pixel
A memory having a data width of 4n bits for 4: 2: 2 digital video data having n bits and having a luminance signal sample and two color difference signal samples, and a luminance signal sample and 2 at the same address of the memory; A video editing device configured to accumulate two color difference signal samples. 6. A luminance signal stream (hereinafter, referred to as a Y stream) and two chrominance signal streams (CR) are divided for each sample of digital video data into a luminance signal sample and two chrominance signal samples, multiplexed for each line, and multiplexed. Stream, and CB stream), a first editing circuit that forms a Y1 stream composed of Y1 samples obtained by editing the Y stream for each line, and a CR stream that is edited for each line. A second editing circuit that forms a CR1 stream composed of CR1 samples; a third editing circuit that forms a CB1 stream composed of CB1 samples obtained by editing the CB stream line by line; the Y1 stream and the CR1 stream And the CB
A first storage circuit for storing one stream in a memory; a Y1 'stream composed of Y1 samples of the same column address output from the first storage circuit, edited for each column address, and composed of Y2 samples. A fourth editing circuit forming a Y2 stream, wherein the CR1 'stream composed of CR1 samples of the same column address output from the first storage circuit is edited for each column address, and composed of CR2 samples. A fifth editing circuit for forming a CR2 stream, a CB1 'stream composed of CB1 samples of the same column address output from the first storage circuit and edited for each column address, and a CB2 composed of CB2 samples. A sixth editing circuit forming a stream, the Y2 stream and the CR2 stream and the CB
A second storage circuit for storing two streams in a memory, and a CR2 'stream and a CB2 sample composed of a Y2' stream composed of Y2 samples and CR2 samples of the same line output from the second storage circuit, The configured CB2 'stream is input,
A video editing apparatus comprising: an assembling circuit that multiplexes and outputs the Y2 sample, the CR2 sample, and the CB2 sample for each sample. 7. The first storage circuit has a first memory for storing a Y1 sample, a second memory for storing a CR1 sample, and a third memory for storing a CB1 sample, The first memory, the second memory, and the third memory are configured to divide and access respective addresses into a row address as an upper address and a column address as a lower address, thereby forming one frame. The Y1 samples are divided into grids to form sub-screens, and all the Y1 samples forming each sub-screen are stored at the same row address in the first memory, and the CR1 samples forming one frame are divided into grids. All CR1 samples constituting each sub-screen are accumulated at the same row address of the second memory, and constitute one frame. Of the CB1 sample to be divided into a grid pattern to form a sub-screen, and all the CB1s constituting each sub-screen are stored in the same row address of the third memory.
7. The video editing apparatus according to claim 6, wherein the video editing apparatus is configured to store samples. 8. The second storage circuit has a fourth memory for storing a Y2 sample, a fifth memory for storing a CR2 sample, and a sixth memory for storing a CB2 sample. The fourth memory, the fifth memory, and the sixth memory are configured to divide and access respective addresses into a row address as an upper address and a column address as a lower address, and constitute one frame. The Y2 samples are divided into grids to form sub-screens, and all the Y2 samples forming each sub-screen are stored in the same row address of the fourth memory, and the CR2 samples forming one frame are divided into grids. All CR2 samples constituting each sub-screen are accumulated at the same row address in the fifth memory, and constitute one frame. The CB2 samples to be divided are divided into a grid pattern to form sub-screens, and all CB2 samples constituting each sub-screen are stored in the same row address of the sixth memory. 6. The video editing device according to item 6. 9. The first storage circuit comprises: two Y1 samples adjacent to each other on the same line;
A multiplexing circuit for multiplexing one CR1 sample near the sample and one CB1 sample near the Y1 sample on the screen;
7. The video editing apparatus according to claim 6, further comprising a seventh memory for storing one sample at the same address. 10. The second storage circuit includes two Y2 samples adjacent to each other on the same line and the Y2 sample on a screen.
One CR2 sample near two samples and one CB2 sample near the Y2 sample on the screen
7. The video editing apparatus according to claim 6, further comprising a multiplexing circuit for multiplexing the sample and an eighth memory for storing the multiplexed four samples at the same address. 11. The first storage circuit stores the Y1 stream, the CR1 stream, and the CB1 stream in the first half of one line of input digital video data, and stores one line of the input digital video data. Outputs the Y1 ′ stream, the CR1 ′ stream, and the CB1 ′ stream in the second half of the above, and the second storage circuit outputs the Y2 stream and the C2 stream in the first half of one line of the input digital video data.
The R2 stream and the CB2 stream are accumulated, and the Y2 ′ stream, the CR2 ′ stream, and the C2 stream are stored in the latter half of one line of the input digital video data.
The video editing apparatus according to claim 6, wherein the video editing apparatus is configured to output a B2 'stream. 12. The seventh memory, wherein the Y1 sample forming one frame is divided into a grid to form a sub-screen,
In the same row address, all Y1s constituting each sub-screen are
10. The video editing apparatus according to claim 9, wherein the video editing apparatus is configured to accumulate samples, CR1 samples and CB1 samples. 13. The eighth memory, wherein the Y2 sample forming one frame is divided into a grid to form a sub-screen,
In the same row address, all the Y2
The video editing apparatus according to claim 10, wherein the video editing apparatus is configured to accumulate samples, CR2 samples, and CB2 samples.