JPH05207425A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To generate a field memory coping with a change in data quantity of a color difference signal, if any, depending on the difference from the broadcast system in the field memory used for a decoder for high definition television receiver. CONSTITUTION:The memory is provided at least with a 1st data shift register RD1 storing data by one line of a memory cell block NC1 selected by a count of an internal address counter newly, a 2nd data shift register RDA storing data of other line of the memory cell block MC1 selected through the correction of the count of an internal address counter AC and a 3rd data shift register RD2 storing remaining picture data by one scanning line of the TV signal from a memory cell block MC2, and implements changeover control of an output multiplexer OM selectively outputting the output data from the plural data shift registers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory suitable as a field memory used in a high definition television decoder.

[0002]

2. Description of the Related Art In a conventional field memory, as shown in FIG. 6, write data shift registers WD1 and WD2 for sequentially shifting input / output data in a shift register.
And read data shift registers RD1, RD2
, Memory cells MC1 and MC2, and sense amplifier SA
1, SA2, an internal address counter AC, a line address decoder LA that selects a word line according to the value of the address counter, and an input buffer that switches input data to each of the write data shift registers WD1 and WD2 according to the value of the address counter. An input demultiplexer ID, and an output multiplexer OM that switches the output data from the read data shift registers RD1 and RD2 according to the value of the address counter AC and outputs the data to the outside.
And a control circuit CC for controlling the field memory. The control circuit CC generates WCK1 and WCK2 based on the write clock signal WCK. WCK1 is a signal that clocks only while input data is input to the write data shift register WD1, and WCK2 is a signal that clocks only while input data is input to the write data shift register WD2. A transfer gate TG is connected between each data shift register WD1, WD2, RD1, RD2 and the sense amplifier SA1, SA2 or the memory cell MC1, MC2.

The control circuit CC also generates RCK1 and RCK2 based on the read clock signal RCK.
RCK1 is a signal for clocking only while the data in the read data shift register RD1 is sequentially output to the output multiplexer OM, and RCK2 is the data in the read data shift register RD2 sequentially output to the output multiplexer OM. It is a signal that clocks only during the period.

The write and read data shift registers are constructed, for example, as shown in FIG. In FIG. 7, a portion surrounded by a broken line is a shift register for one unit, and several shift registers are connected in series to form data shift registers WD1, WD2, RD1, RD2.

Next, a data write operation and a data read operation will be described with reference to FIG. Input data is sequentially input from the input terminal Din in synchronization with the clock signal WCK and transmitted to the input demultiplexer ID. The input demultiplexer ID is, for example, from the data shift register WD2 for writing to the data shift register WD for writing according to the value of the internal address counter AC.
Switch to 1 and transmit. The input data is sequentially shifted in the write data shift register WD1 in synchronization with the clock signal WCK1. When the data shift register WD1 for writing is filled with the input data, the input demultiplexer ID changes the input data to the data shift register W for writing according to the value of the internal address counter AC.
The data shift register WD2 for writing is switched from D1 and transmitted. Data shift register W for writing
While the input data is being input to D2, the data stored in the write data shift register WD1 is set to an arbitrary level selected by the line address decoder LA via the transfer gate TG when the control signal WDT1 becomes high level. Are written at once to the memory cell MC1 connected to the word line. On the read side as well as on the write side, the data of the memory cell MC1 on an arbitrary word line selected by the line address decoder LA is read data at once through the transfer gate TG by setting the control signal RDT1 to high level. It is transferred to the shift register RD1.

The read data shift register RD1 sequentially shifts the data in the read data shift register RD1 in synchronization with the clock signal RCK1. The shifted data is sequentially transmitted to the output multiplexer OM via the read data bus RB1. The output multiplexer OM switches from the read data bus RB2 to the read data bus RB1 according to the value of the internal address counter AC and outputs the data in synchronization with the clock signal RCK to the outside. While the data stored in the read data shift register RD1 is sequentially output, in the read data shift register RD2, the data of the memory cell on an arbitrary word line selected by the line address decoder LA is previously stored in RDT2. To a high level, the data has been transferred through the transfer gate TG, and after the data stored in the read data shift register RD1 has been output, it is switched to the read data shift register RD2. Next, the data stored in the read data shift register RD2 is sequentially shifted in the read data shift register RD2 in synchronization with the clock signal RCK2 and transmitted to the output multiplexer OM.

Next, a case where a high definition television (HDTV) uses the above conventional field memory as an image memory will be described. Current television, namely NTS
The image data of the C method is data in which the color difference signal and the luminance signal are mixed. High-definition television (HDTV) image data is divided into a color difference signal and a luminance signal, and is divided into a region C for storing the color difference signal and a region Y for storing the luminance signal in the memory cell of the field memory as shown in FIG. I know. The motion correction function, which is one of the functions for achieving high image quality in high definition television, corrects only the data of the luminance signal.

In this case, the read data may be the xth line in the color difference signal area C and the x + y line in the luminance signal area Y for correction. When the read data lines are different in the area C and the area Y, in the field memory divided into two as shown in FIG. 6, the data of the color difference signal and the data of the luminance signal are stored in the portion of the memory cell MC1. Therefore, the lines of read data in the areas C and Y are different. Therefore, data for one line of the memory cell MC1 is read at a time by the read data register RD1.
Therefore, serial data cannot be read because it cannot be transferred to.

Therefore, as shown in FIG. 9, the memory cells MC1 corresponding to the memory capacity corresponding to the area C are allocated in advance,
The color difference signal data of the xth line is transferred to the read data shift register RD1, and the luminance signal data of the x + y line is read data shift registers RD2, RD3.
The data can be read out by storing in the. Further, the external input signal OSn is input to the control circuit CC and the internal address counter AC is supplied to give information on how much the line address of the luminance signal data should be corrected with respect to the line address of the color difference signal data to be read. Is a memory cell MC to be read according to the value of OSn
2, the line address of MC3 data is corrected.

[0010]

In this conventional semiconductor memory, in order to perform the above-mentioned motion correction, the area C for storing the data of the color difference signal is divided in advance on the hardware. In this way, in the MUSE system, which is a high definition television broadcasting system adopted in Japan, the area C is used.
Since the length of one line of the above is 200 pixels, the field memory may be created by setting the length of one line of the memory cell MC1 of FIG. 9 to 200 pixels, but other high-definition televisions adopted in other countries. In the broadcasting system of, the length of one line in the area C is not limited to 200 pixels. Therefore, if the length of one line in the area C is fixed by hardware like the conventional semiconductor memory, the There is a problem that the combined field memory cannot be used as a field memory for other broadcasting systems.

The present invention has been made in view of the above problems, and even if the broadcasting system is different, it is possible to perform processing such as motion correction without separately manufacturing a memory adapted to the system. An object of the present invention is to provide a semiconductor memory with improved versatility of the memory.

[0012]

A semiconductor memory according to the present invention is a first-in first-out memory (FIFO memory) system in which data is output in the order in which data is input, and image data for one scanning line of a TV signal is stored in a plurality of memories. In a semiconductor memory that divides and stores in a cell block, a first data shift register that stores data for one line of an arbitrary memory cell block selected by a value of an internal address counter, and the value of the internal address counter is corrected As a result, a second data shift register for storing data for another line of the selected memory cell block and a second data shift register for storing the remaining image data of one scanning line of the TV signal from another memory cell block. Output data from the data shift register 3 and a plurality of the data shift registers That an output multiplexer, an external input control signal, and performs switching control of the output data of the first data shift register and the second data shift register by the output multiplexer.

[0013]

According to the present invention, the first data shift register stores data for one line of the selected specific memory cell block, and the second data shift register stores another line of the specified memory cell block. Stores minute data. Then, the output multiplexer is controlled by the external input control signal to switch the output data of the first data shift register and the second data shift register.
Data for one line can be transferred from the memory cell to the first data shift register or the second data shift register at one time. In the present invention, this data transfer can be switched by software.

[0014]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a semiconductor memory according to an embodiment of the present invention. In the present embodiment, in addition to the conventional semiconductor memory shown in FIG. 6, control is newly performed by switching the third read data shift register RDA and the color difference signal data and the luminance signal data by the output multiplexer OM. And an external input signal SW for. Further, RCK1 is input to the read data shift register RDA as a read clock signal, and the read data shift register RDA is synchronized with the clock signal RCK1 in the same manner as the read data shift register RD1. Are sequentially shifted. Between the read data shift register RDA and the memory cell MC1,
There is a transfer gate TGA, and this transfer gate TGA is controlled by a read data transfer signal RDTA signal.

FIG. 2 is a block diagram of the read side of the memory cell MC1 of the semiconductor memory according to the embodiment of the present invention. The external input signal SW is, for example, as shown in the timing chart of FIG. 3, a signal which becomes high at the clock for reading the luminance signal.

Next, data writing and reading operations in the semiconductor memory configured as described above will be described.

The data write operation is similar to that of the conventional example. Therefore, the data read operation will be described below mainly with reference to FIG. The xth line of the color difference signal data stored in the area C of the memory cell MC1 and the xth line of the luminance signal data stored in the area Y of the memory cell MC1 are not corrected by the correction.
The case of serially reading the data changed to the (x + y) th line will be described. Internal address counter AC
When the line address decoder LA selects the x-th line according to the value of, the first to n-th data on the x-th line of the memory cell MC1 is read data transfer signal RDT.
When A is at high level and RDT1 is at low level, the data is transferred to the read data shift register RDA at once through the transfer gate TGA.

When this transfer is completed, the internal address counter AC then outputs the address corrected by the value of the external input signal OSn to the line address decoder LA,
The line address decoder LA selects the (x + y) th line. The first x + y line of the memory cell MC1
The data from the nth to the nth is the read data transfer signal RDT
When 1 becomes high level and RDTA becomes low level, the data is transferred to the read data shift register RD1 at once through the transfer gate TG. As a result, the read data shift register RDA stores the data of the xth line of the memory cell MC1, and the read data shift register RD1 stores the data of the x + y line of the memory cell MC1. become.

When the read clock signal RCK1 is input to the read data shift register RD1 and the data shift register RDA, the data shift register RD1
The data in the data shift register RDA and the data in the data shift register RDA are sequentially shifted in the data shift register in synchronization with the clock and transmitted to the output multiplexer OM.

The output multiplexer OM outputs the data transmitted from the read data shift register RDA to the first to p-th output data by the external input signal SW, and the p + 1-th to the n-th outputs. Up to the output data, read data shift register RD
The data transmitted from 1 is output. This makes the first
The data of the color difference signal of the x-th line of the memory cell MC1 is output to the p-th to p-th output data, and the luminance signal of the x + y-th line of the memory cell MC1 is continuously output to the p + 1-th to n-th output data The data of is output.

Next, a second embodiment of the present invention will be described with reference to FIG.

Generally, in a television memory, a data write operation and a data read operation are synchronized, and a write clock signal and a read clock signal can be shared. Therefore, in the second embodiment, the write clock signal and the read clock signal are shared and input as the CLK signal, and the control circuit outputs the clock signal C.
LK1 and CLK2 are generated. CLK1 is a signal that clocks only while data is input / output to / from the data shift register D1 and data shift register DA, and CLK2 is a signal that clocks only while data is input / output to / from the data shift register D2. In addition, the data shift register D
1. The data shift register D2 is used for both writing and reading. As a result, the number of data shift registers can be reduced. In the second embodiment, the write data to the memory cell MC1 is input to the data shift register D1 via the write data bus WB1 so that the transfer control of the write data to the memory cell MC1 is controlled by the DT1 signal. I have to. However, the write data bus may be connected to the data shift register DA so that the write data is input to the data shift register DA, and the transfer control of the write data to the memory cell MC1 may be controlled by the DTA signal. ..

Next, the data write and read operations in the second embodiment will be described.

Input data is sequentially input from the input terminal Din in synchronization with the clock signal CLK and transmitted to the input demultiplexer ID. The input demultiplexer ID switches and transmits, for example, input data from the data shift register D2 to the data shift register D1 according to the value of the internal address counter AC. The input data is sequentially input and shifted in the data shift register D1 in synchronization with the clock signal CLK1.

Next, the shift operation will be described.
As shown in FIG. 5A, data to be read next is transferred from the memory cell MC1 into the data shift register D1 while the data shift register D2 is performing the data input / output operation. Therefore, when one new data is input from the write data bus WB1 in synchronization with the clock signal CLK1, the stored data becomes 1
Output to the read data bus RB1 [see FIG. 5 (b)].

In this way, the data shift register D
If you input clocks for the number of registers in 1,
All the data stored in the data shift register 1 is transmitted to the output multiplexer, and the data in the data shift register 1 is the newly input data [see FIG. 5 (c)].

As described above, the data shift register 1 can simultaneously perform data input / output.

When the data input / output operation shifts to the data shift register D2, the data in the data shift register D1 is connected to an arbitrary word line selected by the write address decoder when DT1 goes high. It is transferred to the memory cells at once. When the write operation to the memory cell MC1 is completed, the data is transferred from the memory cell MC1 to the data shift register D1 and the data shift register DA, and the data is read out. The read operation is the same as in the first embodiment.

As described above, the write data is written only to the data shift register D1, and the read data is read by switching the output data of the data shift register D1 and the data shift register DA by the output multiplexer OM. Therefore, in the second embodiment, when the write operation and the read operation are synchronized, it is possible to reduce one external input terminal for the clock signal and the data shift registers WD1 and WD2 for writing, and to reduce the element formation area. There is an advantage that it can be reduced.

[0031]

As described above, according to the present invention, in the method of storing the image data of one scanning line of the TV signal by dividing it into a plurality of memory cell blocks and storing the image data, the area C for storing the data of the color difference signal is stored. By correcting the value of the internal address counter and the first data shift register that stores the data for one line of the selected arbitrary memory cell block according to the value of the internal address counter without dividing on hardware. A second data shift register that stores data for another line of the selected memory cell block, and third data that stores the remaining image data for one scanning line of the TV signal from another memory cell block. An output multi, which has at least a shift register and is capable of switching and outputting output data from a plurality of data shift registers. Since it is equipped with an input terminal for an external input signal that controls the switching of the lexer, even if the data amount of the color difference signal differs depending on the broadcasting system, a semiconductor that newly matches the data amount of the color difference signal of another broadcasting system is newly added. The semiconductor memory of the present invention can be used for motion compensation without manufacturing a memory, and is excellent in versatility.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor memory according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a read side of a memory cell MC1 of this embodiment.

FIG. 3 is a timing diagram of an SW signal and output data Don in this embodiment.

FIG. 4 is a block diagram showing a semiconductor memory according to a second embodiment of the present invention.

5A, 5B, and 5C are diagrams for explaining the operation of the data shift register D1 of this embodiment.

FIG. 6 is a block diagram showing a conventional semiconductor memory.

FIG. 7 is a block diagram showing the configuration of the same data shift register.

FIG. 8 is a diagram showing a storage distribution of color difference signal data (C area) and luminance signal data (Y area) in a conventional memory cell.

FIG. 9 is a block diagram showing another conventional semiconductor memory.

[Explanation of symbols]

SW: External input signal for controlling data switching OSn: External input signal for inputting correction amount in motion correction WCK: Write clock signal RCK: Read clock signal OE (negative logic); Output enable signal WE (negative logic) ); Write enable signal WRST (negative logic); Write reset signal RRST (negative logic); Read reset signal Din; Data input signal Don; Data output signal WDT1, WDT2; Write data transfer control signal RDT1 output from the control circuit , RDT2, RDTA; read data transfer control signals output from the control circuit DT1, DT2, DTA; write / read data transfer control signal output from the control circuit C; color difference signal data stored in the memory cells Region Y; in memory cell Area in which data of luminance signal is stored; input demultiplexer OM; output multiplexer MC1, MC2, MC3; memory cell LA; line address decoder AC; internal address counter RD1, RD2, RDA; read data shift register WD1, WD2; write data shift register D1, D2, DA; data shift register

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 5/907 B 7916-5C

Claims (1)

[Claims] 1. A semiconductor memory in which image data for one scanning line of a TV signal is divided and stored in a plurality of memory cell blocks in a first-in first-out memory system in which data is output in an input order, and an internal address counter A first data shift register that stores data for one line of an arbitrary memory cell block selected by a value, and another one line of the selected memory cell block by correcting the value of the internal address counter. Output from a plurality of the data shift registers, a second data shift register for storing the above data, a third data shift register for storing the remaining image data for one scanning line of the TV signal from another memory cell block, It has an output multiplexer for switching and outputting data, and the output is controlled by an external input control signal. The semiconductor memory is characterized in that the output multiplexer switches the output data of the first data shift register and the second data shift register by a power multiplexer.