JP2001004709A - Composite substrate body and method for inspecting the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compact composite substrate body which makes a gate element hardly broken and a method for inspecting the substrate body. SOLUTION: In a method for inspecting composite substrate body, a desired bump junction 42 and the ground GND1 of a master chip 34 are selectively conducted by using a register 68, and an N-channel MOSFFT 62 and, at the same time, a prescribed voltage is made to be applied across the ground GND1 and the ground GND2 of a sub-chip 36. Under such a condition, the bump junction 42 can be inspected for connected state by measuring the current I flowing in the forward direction of a diode D4. Since the connected state of each bump junction can be inspected without providing pads correspondingly to the bump junction, a laminated chip 32 can be made compact. In addition, since the installation of a gate element such as the transfer gate, etc., to an input-output pad 38 is not required, the possibility of the gate element being broken by a surge voltage is also eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite substrate and a method for inspecting the same, and more particularly, to a technique for inspecting a connection state between connection terminals.

[0002]

2. Description of the Related Art A technique for obtaining a single stacked chip by stacking a plurality of IC chips one above the other (chip-on-chip technique) is known. In chip-on-chip technology,
For example, the input / output pad of one IC chip is gold (A
u), and the input / output pads of the other IC chip are formed of tin (Su), and these pads are electrically connected to each other by using a eutectic bump bonding technique. ing.

FIG. 11 is a diagram showing a part of a circuit near a junction of such a laminated chip 2. In the laminated chip 2, the child chip 6 is superimposed on the parent chip 4, and the input / output pads 8 of the parent chip 4 and the input / output pads 10 of the child chip 6 are joined by a bump joining technique, so that the bump joint 12 is formed. Has formed. A test pad 14 is connected to the input / output pad 8 of the parent chip 4.

[0004] Between the input / output line 16 of the parent chip 4 and the power supply VDD1 and ground GND1 for the parent chip 4, protection diodes (or parasitic diodes) D1 and D2 are inserted in opposite directions. Similarly, the input / output line 18 of the child chip 6 and the power supply VD
A protection diode (or a parasitic diode) D3 is connected between D2 and the ground GND2 in the reverse direction.
D4 is inserted.

The power supply VDD1 and the ground GND1 for the parent chip 4 and the power supply VDD for the child chip 6
2 and the ground GND2 are connected to power supply pads (not shown) provided on the parent chip 4, respectively.

To perform an OS (disconnection / short circuit) inspection of the bump bonding portion 12, first, the input / output lines 16
The input / output line 16 is turned into a high-impedance state by turning off the transmission gate 20 provided for the input / output line. Next, for example, the potential of the power supply pad (not shown) connected to the ground GND2 for the child chip 6 is adjusted to be higher than the potential of the inspection pad 14 by the voltage V1. Here, the voltage V1 is slightly higher than the forward threshold voltage Vt of the diode D4. At this time, the current I flowing due to the voltage V1 is measured.

If the bonding state of the bump bonding portion 12 is good, the current I falls within a predetermined range determined by the forward characteristics of the diode D4. When the bump bonding portion 12 is in a disconnected state, the current I is significantly lower than the predetermined range. If the bump joint 12 is short-circuited with another bump joint (not shown), the current I greatly exceeds the predetermined range.

In this manner, an OS (disconnection / short circuit) inspection can be performed for each bump joint 12.

[0009]

However, the conventional OS inspection method as described above has the following problems. In the conventional inspection method, it is necessary to provide the same number of inspection pads 14 as the number of the bump bonding portions 12 on the parent chip 4. In this case, when the number of the bump bonding portions 12 increases, the number of the test pads 14 also needs to increase, and the chip size of the parent chip 4 increases.

When a surge voltage is applied to the inspection pad 14, the transmission gate 20 of the parent chip 4 may be broken.

[0011] The present invention solves such a problem,
It is an object of the present invention to provide a composite substrate that is compact and has a gate element that is not easily broken, and a method for inspecting the composite substrate.

[0012]

Means for Solving the Problems, Functions and Effects of the Invention
The composite substrate according to claim 1, wherein the first substrate includes one or more first connection terminals, and the second substrate includes one or more second connection terminals corresponding to the first connection terminals. Are connected to each other by connecting corresponding connection terminals to each other.
A first power supply line that can be input or output from the outside, and a selective conduction unit that can selectively bring a desired first connection terminal and the first power supply line into a substantially conductive state. , The second substrate is provided independently of the first power supply line and provided with a second power supply line that can be input or output from the outside, and a second terminal and the second power supply line. And a substantial diode interposed in the opposite direction.

[0013] Therefore, the desired first portion can be formed by the selective conducting portion.
And the first power supply line is selectively made substantially conductive, a predetermined voltage is applied between the first power supply line and the second power supply line, and the substantial diode is provided. By measuring the current flowing in the forward direction, the connection state of the connection portion between the desired first connection terminal and the second connection terminal corresponding to the first connection terminal can be inspected.

That is, since the connection state of each connection portion can be inspected without providing an inspection pad corresponding to each connection portion, the size of the composite substrate can be reduced. In addition, since it is not necessary to provide a gate element such as a transmission gate at the first connection terminal, there is no possibility that the gate element is damaged by a surge voltage or the like.

In the composite substrate according to the second aspect, the selective conducting portion includes a transistor for substantially bringing the first connection terminal and the first power supply line into a conducting state in an ON state, and a transistor for a desired transistor only. And a transistor control unit capable of turning on the transistor.

Therefore, the desired first connection terminal and the first power supply line can be easily and substantially made conductive by turning on only the desired transistor by the transistor control unit. Can be.

According to a third aspect of the present invention, there is provided a method for inspecting a composite substrate, comprising: a first substrate having at least one first connection terminal and a first power supply line capable of inputting or outputting from outside; One or more second connection terminals corresponding to the terminals;
A second power supply line, which is provided independently of the power supply line of the second power supply line and can be input or output from the outside, and a substantial diode inserted in a reverse direction between the second terminal and the second power supply line. A method for inspecting a connection state between connection terminals in a composite board body in which corresponding second connection terminals are connected to each other by connecting the corresponding first connection terminals to each other.
And the first power supply line is selectively made substantially conductive, and a predetermined potential difference is applied between the first power supply line and the second power supply line to provide a dual power supply. The connection state of the connection terminal is inspected by measuring a current flowing between the lines.

Therefore, the connection state of each connection portion can be inspected without providing an inspection pad corresponding to the connection portion between the first connection terminal and the second connection terminal corresponding to the first connection terminal. Therefore, the size of the composite substrate can be reduced. Also, since there is no need to provide a gate element such as a transmission gate at the first connection terminal,
There is no possibility that the gate element is destroyed by a surge voltage or the like.

In the claims, the term "substrate" is a concept including not only an IC chip on which a semiconductor element and the like are formed but also a substrate (including a film-like substrate) for mounting the IC chip and the like. .

The term "power supply line" refers to a line for supplying power, and is a concept including a power line and a ground line.

The term "diode inserted in the opposite direction between the terminal and the power supply line" refers to a diode inserted in a direction in which no current flows from the power supply line to the terminal in a normal power supply state.

[0022]

FIG. 2 is a drawing showing a sectional structure of a laminated chip 32 which is a composite substrate according to an embodiment of the present invention. The laminated chip 32 is obtained by arranging a child chip 36 as a second substrate on a parent chip 34 as a first substrate.

An input / output pad 38 (see FIG. 1), which is a first connection terminal provided on the parent chip 34, and a child chip 36
Input / output pad 40 as a second connection terminal provided in
(See FIG. 1) are respectively joined by a bump joining technique to form a bump joint portion 42.

As shown in FIG. 2, near the outer periphery of the parent chip 34, a power supply pad 44, which is a bonding pad connected to the ground GND1 for the parent chip 34, and a power supply VDD1 for the parent chip 34 are connected. A large number of bonding pads are provided in addition to the power supply pad 50 as the bonding pad.

The laminated chip 32 is placed on a frame 90, for example. The bonding pads such as the power supply pad 44 and the power supply pad 50 of the multilayer chip 32
It is connected to a wiring 92 provided on the frame 90 via a bonding wire 94.

FIG. 1 is a diagram showing a part of a circuit near the junction of such a laminated chip 32. As shown in FIG. As mentioned above,
Of the input / output pads 38 of the parent chip 34 and the input / output pads 40 of the child chip 36, the input / output pads of one chip are made of gold (Au), and the input / output pads of the other chip are made of tin (Su). Then, these pads are connected to each other by using a bump (bump) bonding technique using eutectic to form a bump bonding portion 42.

Between the input / output line 46 of the parent chip 34 and the power supply VDD1 and ground GND1 for the parent chip 34, protection diodes (or parasitic diodes) D1 and D2 are inserted in opposite directions. Similarly,
Between the input / output line 48 of the child chip 36 and the power supply VDD2 and the ground GND2 for the child chip 36, protection diodes (or parasitic diodes) D3 and D4 are inserted in the opposite directions.

A power supply line for the parent chip 34;
The power supply VDD1 and the ground GND1 are connected to the power supply pad 50 and the power supply pad 44, which are bonding pads provided on the parent chip 34, respectively, as described above.

A power supply line for the child chip 36,
The power supply VDD2 and the ground GND2 are connected to a power supply pad 56 and a power supply pad 58, which are bonding pads provided on the parent chip 34, via a bump joint 52 and a bump joint 54, respectively.

The input / output line 46 of the parent chip 34 is a line for performing input and output. A CMOS inverter 60 is inserted in the input / output line 46. C
The MOS inverter 60 includes an N-channel MOSFET 62 and a P-channel MOSFET
64.

FIG. 3 shows the possible logical values of the line OC and the data output line OUT and the CMOS inverter 60.
6 is a table showing the relationship with the output of FIG. When the line OC is set to the logic “H”, the output mode is set, and the data on the data output line OUT is output to the input / output line 46 as it is.

On the other hand, when the line OC is set to the logic "L", the input mode is set, and the output terminal of the CMOS inverter 60 is
Regardless of the data content of the data output line OUT,
The state becomes a high impedance state. Therefore, the data input from the input / output line 46 is sent to the data input line IN via the buffer 66.

The configuration of the input / output lines 48 of the child chip 36 is the same as the configuration of the input / output lines 46 of the parent chip 34.

In FIG. 1, only the input / output line 46 and the input / output line 48 are illustrated as the input / output line of the parent chip 34 and the input / output line of the child chip 36, respectively, for convenience of explanation. , The parent chip 34 and the child chip 36 are provided with many similar input / output lines (not shown), respectively.
Each is connected via a bump joint (not shown).

FIG. 4 is a diagram showing a configuration of the register 68 which is a transistor control unit built in the parent chip 34. The register 68 includes a register input terminal 70 and a number of register output terminals 72a, 72b, 72c,.
It has.

A desired value can be set in the register 68 via the register input terminal 70. The register output terminal 72a is connected to the data output line OUT (see FIG. 1) of the input / output line 46 of the parent chip 34.
The other register output terminals 72b, 72c,... Are also connected to data output lines (not shown) of other input / output lines (not shown) of the parent chip 34, respectively.

The logical value corresponding to the value set in the register 68 is output to the data output line OUT of the input / output line 46 of the parent chip 34 and the data output line of the other input / output lines. For example, as shown in FIG. 4, when the binary number “011... 1” is set in the register 68, the logical values of the register output terminals 72a, 72b, 72c,. "," H ", ...,"
H ”. That is, the input / output line 4 of the parent chip 34
6, only the data output line OUT becomes logic "L",
Data output line O of other input / output lines of the parent chip 34
All the UTs become logic "H".

Next, the OS of the bump joint 42 (disconnection /
A method for performing a (short circuit) inspection will be described. To perform the OS test, first, as shown in FIG. 5, each of the power supplies E1, E2, E
3, and ammeter 76 are connected.

The voltages of the power supplies E1, E2, E3 are adjusted so as to be V1, V2, V2-V1, respectively. Here, the voltage V1 is slightly higher than the forward threshold voltage Vt of the diode D4 (see FIG. 1) (see FIG. 6). The voltage V2 is a high-potential-side power supply voltage for operating the multilayer chip 32.

By setting the voltages of the power supplies E1, E2, and E3 in this manner, the ground GN for the child chip 36 is set.
The potential of the power supply pad 58 connected to D2 is changed to the power supply pad 4 connected to the ground GND1 for the parent chip 34.
4 becomes higher by the voltage V1 than the potential of the fourth voltage. The power supply pad 50 connected to the power supply VDD1 for the parent chip 34
And the power supply pad 56 connected to the power supply VDD2 for the child chip 36 have the same potential.

Next, the data pad 7 shown in FIG.
By applying appropriate signals to 8a, 78b,..., The laminated chip 32 is operated in the following OS detection mode. That is, first, the line OC of the child chip 36 shown in FIG. 1 is set to logic “L”. Thereby, the child chip 36
Output terminal of the CMOS inverter 74 is in a high impedance state. At the same time, the line OC of the parent chip 34 is set to logic “H”. Thereby, the CMOS of the parent chip 34
Inverter 60 is in the output mode.

Here, as shown in FIG.
Are set to binary numbers "011... 1". Thus, the register output terminals 72a, 72b, 72c,.
Are “L”, “H”, “H”,.
・, Becomes "H". That is, only the data output line OUT of the input / output line 46 of the parent chip 34 becomes logic “L”, and all the data output lines OUT of the other input / output lines of the parent chip 34 become logic “H”.

That is, the input / output lines 46 of the parent chip 34
N channel MO constituting CMOS inverter 60 of FIG.
Only the SFET 62 is turned on, and all the N-channel MOSFETs (not shown) constituting the CMOS inverters of the other input / output lines of the parent chip 34 are turned off.

Therefore, at this time, as shown in FIG. 5, when the current flowing into the power supply pad 58 is measured by the ammeter 76, as shown in FIG. GND2, diode D4, input / output line 48, bump junction 42, input / output line 46, N-channel MOSFET 62, ground G
The current I flowing to the power supply pad 44 can be known via ND1.

FIG. 6 shows diodes D1, D2, D3, D
4 is a drawing showing voltage-current characteristics of No. 4. When a voltage V1 such that a current flows in the forward direction of the diode D4 is applied between the power supply pad 58 and the power supply pad 44 shown in FIG. 1, the bonding state of the bump bonding portions 54 and 42 is good. Then, as shown in FIG. 6, the current I becomes a predetermined value I ≒ I1 determined by the forward characteristic of the diode D4.

On the other hand, if the bump joint 54 or the bump joint 42 is disconnected, the current I becomes IＩ0. If the bump joint 54 and the bump joint 42 are short-circuited, or if the bump joint 54 or the bump joint 42 is short-circuited to another bump joint (not shown), the current I is considerably larger than I1 (2 of I1).
More than twice).

As described above, by measuring the current I, the OS (open circuit / short circuit) inspection of the bump joint 42 can be performed.

Next, the same inspection is performed by setting the binary number to be set in the register 68 shown in FIG.
(Disconnection / short circuit) inspection can be performed. In this manner, by performing the same inspection while changing the binary number set in the register 68, all the bump joints are
OS (disconnection / short circuit) inspection can be performed.

In this embodiment, the ground GND1 for the parent chip 34 corresponds to the first power supply line, and the ground GND2 for the child chip 36 corresponds to the second power supply line. The diode D4 corresponds to a substantial diode. Further, the above-described register 68 and the N-channel MOSFET 62 correspond to a selection conducting section.

As described above, in this embodiment, the parent chip 34 includes the ground GND1 that can be input or output from the outside, the desired input / output pad 38, and the ground GND.
A resistor 68 and an N-channel MOSFET 62 capable of selectively making ND1 substantially conductive are provided. The child chip 36 is connected to the ground GN.
A ground GND2 which is provided independently of D1 and which can be input or output from the outside, and a diode D4 inserted in the opposite direction between the input / output pad 40 and the ground GND2 are provided.

Therefore, the desired input / output pad 38 can be formed by using the resistor 68 and the N-channel MOSFET 62.
And the ground GND1 are selectively made substantially conductive, and a predetermined voltage is applied between the ground GND1 and the ground GND2. By measuring the current flowing in the forward direction of the diode D4, Bump joint 4 connecting desired input / output pad 38 and input / output pad 40
2 can be checked.

That is, the connection state of each bump joint can be inspected without providing an inspection pad corresponding to each bump joint, so that the laminated chip 32 can be made compact. Also, input / output pad 3
Since there is no need to provide a gate element such as a transmission gate in 8, there is no possibility that the gate element is destroyed by a surge voltage or the like.

By turning ON only the N-channel MOSFET 62 connected to the desired input / output pad 38 by the register 68, the desired input / output pad 38 and the ground GND1 can be easily brought into conduction. Can be.

In the above embodiment, the child chip 36
The potential of the ground GND2 for the parent chip 34 is made different from the potential of the ground GND1 for
Although the method for performing the inspection has been described, the present invention is not limited to this. For example, as shown in FIGS. 7 to 9, the potential of the power supply VDD2 for the child chip 36 and the parent chip 3
It is also possible to make the OS inspection of the bump bonding portion different from the potential of the power supply VDD1 for the fourth.

In this case, as shown in FIG. 9, the power supplies E1, E2, E3 and the ammeter 76 are connected.

The voltages of the power supplies E1, E2, E3 are adjusted so as to be 0, V2, V2-V1, respectively. Here, the voltage V1 is slightly higher than the forward threshold voltage Vt of the diode D3 (see FIG. 7) (see FIG. 6). Further, the voltage V2 is the same as in the above-described embodiment.
This is a high-potential-side power supply voltage for operating the multilayer chip 32.

By setting the voltages of the power supplies E1, E2, and E3 in this manner, the power supply VDD1 for the parent chip 34 is set.
The potential of the power supply pad 50 connected to the
Voltage V1 higher than the potential of the power supply pad 56 connected to the power supply VDD2. A power supply pad 58 connected to the ground GND2 for the child chip 36,
The power supply pad 44 connected to the ground GND1 for the parent chip 34 has the same potential.

Next, the data pad 7 shown in FIG.
By applying appropriate signals to 8a, 78b,..., The laminated chip 32 is operated in the following OS detection mode. That is, first, as in the case of the above-described embodiment, the line OC of the child chip 36 shown in FIG.
To As a result, the output terminal of the CMOS inverter 74 of the child chip 36 enters a high impedance state. At the same time, the line OC of the parent chip 34 is set to logic “H”. As a result, the CMOS inverter 60 of the parent chip 34
Output mode.

Here, as shown in FIG.
Are set to binary numbers "100 ... 0". Thus, the register output terminals 72a, 72b, 72c,.
Are "H", "L", "L",.
・, "L". That is, only the data output line OUT of the input / output line 46 of the parent chip 34 becomes logic “H”, and all the data output lines OUT of the other input / output lines of the parent chip 34 become logic “L”.

That is, the input / output lines 46 of the parent chip 34
P-channel MO constituting CMOS inverter 60 of FIG.
Only the SFET 64 is turned on, and all the P-channel MOSFETs (not shown) constituting the CMOS inverters of the other input / output lines of the parent chip 34 are turned off.

Therefore, at this time, as shown in FIG. 9, when the current flowing from the power supply pad 56 is measured by the ammeter 76, as shown in FIG.
From the power supply VDD1, the P-channel MOSFET 64,
I / O line 46, bump joint 42, I / O line 4
8, diode D3, power supply VDD2, bump joint 52
, The current I flowing through the power supply pad 56 can be known.

When a voltage V1 such that a current flows in the forward direction of the diode D3 is applied between the power supply pad 50 and the power supply pad 56 shown in FIG. If the state is good, the current I becomes a predetermined value I 値 determined by the forward characteristic of the diode D3.
I1 (see FIG. 6).

On the other hand, if the bump joint 52 or the bump joint 42 is disconnected, the current I becomes IＩ0. If the bump joint 52 and the bump joint 42 are short-circuited, or if the bump joint 52 or the bump joint 42 is short-circuited with another bump joint (not shown), the current I is considerably larger than I1 (2 of I1).
More than twice).

As described above, by measuring the current I, the OS (disconnection / short-circuit) inspection of the bump joint 42 can be performed.

Next, by making the binary number set in the register 68 shown in FIG. 8 "010... 0" and performing the same inspection, the OS inspection can be performed on another bump joint. Thus, register 6
By performing the same inspection while changing the binary number set to 8, the OS inspection can be performed for all the bump joints, as in the above-described embodiment.

In this embodiment, the power supply VDD1 for the parent chip 34 corresponds to the first power supply line, and the power supply VDD2 for the child chip 36 corresponds to the second power supply line. The diode D3 corresponds to a substantial diode. Further, the above-described register 68 and the P-channel MOSFET 64 correspond to a selection conducting section.

In each of the above embodiments, the input / output pad 3
N-channel MOSFET 62 or P-channel MOSF forming CMOS inverter 60 connected to
The case where the ET64 is used has been described as an example, but the transistors forming the selective conduction unit are not limited to these.

For example, as shown in FIG. 10A, an N-channel MOSFET having a drain connected to a pull-up resistor R1 and a source connected to a ground GND1.
80 is provided on the parent chip 34, and the drain is connected to the input / output pad 38.
ET80 can also be used as a transistor that forms a selective conduction unit.

As shown in FIG. 10B, an open-drain N-channel MOSFET 82 having a source connected to the ground GND 1 is provided on the parent chip 34, and the drain is connected to the input / output pad 38. Can be used as a transistor constituting a selective conduction portion.

The N-channel MOSFET shown in FIG. 10A
Both ON / OFF of 80 and ON / OFF of N-channel MOSFET 82 shown in FIG. 10B are controlled by a register 68 provided in the parent chip 34.

In each of the above embodiments, the register 68 is provided in the parent chip 34 and the child chip 36 is provided.
Of the bump junction is measured by measuring the current flowing through the diode D4 or the diode D3. However, the present invention is not limited to this.

For example, it is also possible to provide a configuration in which the register 68 is provided in the child chip 36 and the current flowing through the diode D2 or the diode D1 of the parent chip 34 is measured, so that the OS inspection of the bump junction is performed.

In each of the above-described embodiments, the first connection terminal and the first connection terminal in the ON state are used as the selective conduction portion.
The above description has been made with reference to an example in which a transistor that substantially turns on the power supply line and a transistor control unit that can turn on only the desired transistor are turned on. However, the selective conduction unit is not limited to this. Not something. What is essential is that the selective conduction section is capable of selectively bringing the desired first connection terminal and the first power supply line into a substantially conductive state.

Further, in each of the above embodiments, the laminated chip in which the parent chip and the child chip (that is, two chips) are laminated using the chip-on-chip technique has been described as an example of the composite substrate. The present invention can be applied to a stacked chip in which three or more chips are stacked, or a stacked chip in which a plurality of child chips are mounted on one parent chip.

Further, the composite substrate to which the present invention can be applied is not limited to a laminated chip formed by using a chip-on-chip technique. For example, tab (ta
The present invention can be applied to, for example, a film-shaped substrate on which one or more semiconductor chips are mounted by using a pe automated bonding) technique.

Further, in each of the above embodiments, the case where a bump bonding technique is used as a technique for connecting the connection terminals of the chip (substrate) is described as an example.
The present invention is not limited to this. For example, when connecting the connection terminals using solder bonding technology,
The present invention is applicable to a case where connection terminals are connected using any connection technology, such as a case where connection terminals are connected using anisotropic conductive rubber or a case where connection terminals are connected using wire bonding technology. Can be applied.

[Brief description of the drawings]

FIG. 1 is a diagram showing a part of a circuit near a joint of a laminated chip 32 which is a composite substrate according to an embodiment of the present invention.

FIG. 2 is a drawing showing a cross-sectional configuration of a laminated chip 32.

FIG. 3 is a table showing a relationship between possible logical values of a line OC and a data output line OUT and an output of a CMOS inverter 60;

FIG. 4 is a diagram showing a configuration of a register 68 which is a transistor control unit built in a parent chip 34;

FIG. 5 is a view for explaining an OS (disconnection / short-circuit) inspection method for a bump joint, which is an inspection method for a composite substrate according to an embodiment of the present invention.

FIG. 6 is a diagram showing voltage-current characteristics of diodes D1, D2, D3, and D4.

FIG. 7 is a view showing a part of a circuit in the vicinity of a bonding portion of the laminated chip 32, and is a view for explaining an OS inspection method of a bump bonding portion according to another embodiment of the present invention.

FIG. 8 is a view showing a configuration of a register 68, for explaining an OS inspection method for a bump joint according to another embodiment of the present invention.

FIG. 9 is a view for explaining an OS inspection method for a bump joint according to another embodiment of the present invention.

FIGS. 10A and 10B are diagrams showing another example of a transistor constituting a selective conduction unit.

FIG. 11 is a diagram showing a part of a circuit near a junction of a conventional laminated chip 2.

[Explanation of symbols]

 32 laminated chip 34 parent chip 36 child chip 38 input / output pad 42 bump junction 62 N channel MOSFET 68: Register D4: Diode GND1: Ground GND2: Ground I: Current

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Claims (3)

[Claims] A first substrate provided with one or more first connection terminals and a second substrate provided with one or more second connection terminals corresponding to the first connection terminals correspond to each other. A composite board body in which connection terminals are connected to each other and connected to each other, wherein the first board includes a first power supply line capable of being input or output from the outside, a desired first connection terminal, and a first power supply. And a selective conducting portion capable of selectively bringing the line into a substantially conducting state. The second substrate is provided independently of the first power supply line and can be externally input or output. A composite substrate comprising: a power supply line; and a substantial diode inserted in a reverse direction between the second terminal and the second power supply line. 2. The composite substrate according to claim 1, wherein said selective conducting portion is a transistor that substantially turns on said first connection terminal and said first power supply line in an ON state. And a transistor control unit capable of turning ON only the transistor. A first power supply line having at least one first connection terminal and a first power supply line capable of inputting or outputting from outside;
And a second power supply line provided independently of one or more second connection terminals and the first power supply line corresponding to the first connection terminal and capable of inputting or outputting from the outside, and a second power supply line. A second substrate having a substantial diode inserted in a reverse direction between the terminal and the second power supply line; A connection state of the first power supply line and the first power supply line, and selectively connect the desired first connection terminal and the first power supply line to a substantially conductive state. Providing a predetermined potential difference between the power supply lines and measuring a current flowing between the two power supply lines to test a connection state of the connection terminals.