JPH09116096A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can be tested for its performance as it remains mounted on a printed board, etc., and which works normally without grounding terminal pads for testing which have high input impedances, etc., after the performance test. SOLUTION: This integrated circuit has terminal pads for addressing 7, 8 which are ones for testing that have high input impedances and a terminal pad for testing 9. In the integrated circuit, field effect transistors FET1-FET3 which work as impedance reducing circuits that reduce input impedances of the terminal pads for addressing 7, 8 and the terminal pad for testing 9.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit having a test terminal pad having a high input impedance.

[0002]

2. Description of the Related Art For example, a general-purpose E ² PROM chip adopting an I ² C bus interface system,
There is a semiconductor integrated circuit having a terminal pad for testing with high input impedance. To configure a simple information storage device using such a semiconductor integrated circuit,
The E ² PROM chip is mounted on a printed circuit board.

However, conventionally, in the manufacturing process of the information storage device, the E mounted on the printed circuit board is used.
^{2 It} has been difficult to easily check whether the PROM chip is functioning normally. That is, since a plurality of test terminal pads are connected to the ground terminal via a printed wiring or the like, it is difficult to easily perform a function check using the test terminal pads.

This is because the input impedance of the test terminal pads is high, and unless these are connected to the ground terminal, the operation of the E ² PROM chip becomes unstable and does not operate normally.

In order to solve this problem, in the process of manufacturing the information storage device, E ² PR is printed on the printed circuit board.
It is conceivable to mount the OM chip, check the function of the E ² PROM chip, and then connect the test terminal pad to the ground terminal via a jumper wire.

This method will be specifically described with reference to FIG. A general-purpose E ² PROM chip 101 adopting the I ² C bus interface system is a printed circuit board 102.
Mounted on top. The E ² PROM chip 101 has
The ground terminal pad 103, the logic power supply terminal pad 104, the clock signal terminal pad 105, the data in / out terminal pad 106, the plurality of address terminal pads 107 and 108, and the test terminal pad 10.
9 are provided, and a ground terminal 111, a logic power supply terminal 112, a clock signal terminal 113, and a data in / out terminal 114 are provided on the printed circuit board 102 as external connection terminals. As the internal terminals, a plurality of address terminals 115 and 116 and a test terminal 117 are provided.

The grounding terminal pad 103 and the grounding terminal 111 are connected to the wire 1 for wire bonding.
21 and the printed wiring 122 are connected,
The logic power supply terminal pad 104 and the logic power supply terminal 112 are connected by a wire 123 for wire bonding.
And the printed wiring 124. Clock signal terminal pad 105 and clock signal terminal 11
3 is connected via a wire 125 for wire bonding and a printed wiring 126, and the data-in / out terminal pad 106 and the data-in / out terminal 114 are connected to the wire 1 for wire bonding.
27 and the printed wiring 128 are connected.
The address terminal pad 107 and the address terminal 115 are connected via a wire bonding wire 129 and a printed wiring 130, and the address terminal pad 108 and the address terminal 116 are wire bonding wires. 131 and printed wiring 132
And are connected through. Test terminal pad 109
The test terminal 117 and the test terminal 117 are connected via a wire bonding wire 133 and a printed wiring 134.

The address terminal 115 is used for the printed wiring 1.
Printed wiring 122 through 41 and jumper wires 142
The address terminal 116 is connected to the printed wiring 122 via the printed wiring 143 and the jumper wire 144. The test terminal 117 is connected to the printed wiring 122 via the printed wiring 145 and the jumper wire 146.

That is, E ² P is formed on the printed circuit board 102.
Equipped with ROM chip 101, E ² PROM chip 10
After connecting each terminal pad of No. 1 and the bonding portion of each printed wiring on the printed board 102 by wire bonding, the address terminal pads 107 and 108 and the test terminal pad 10 which are terminal pads for testing.
The function check of the E ² PROM chip 101 is performed using the address terminals 115 and 116 and the test terminal 117 connected to the printed circuit board 141,1.
The bonding portions of 43, 145 and the bonding portion of the printed wiring 122 are jumper wires 142, 144, 146.
To connect.

[0010]

However, in such a method, not only the cost of the jumper wires 142, 144, 146 themselves is required but also the jumper wire 14 is required.
Both ends of 2, 144, 146 are printed wiring 141, 1
Bonding portions 43 and 145 and printed wiring 12
There is a problem in that an extra step for soldering the second bonding portion and inspecting the quality of the connection is additionally required, which causes a significant increase in manufacturing cost. In addition, the characteristics may change after manufacturing due to deterioration of the jumper wires 142, 144, 146.

The present invention was devised under the circumstances as described above, and the function check can be easily performed in a state where it is mounted on a printed circuit board or the like, and after that, for a test with a high input impedance. It is an object of the present invention to provide a semiconductor integrated circuit which functions normally even if the terminal pad is not grounded.

[0012]

DISCLOSURE OF THE INVENTION In order to solve the above problems, the present invention employs the following technical means.

That is, the semiconductor integrated circuit provided by the first aspect of the present invention is a semiconductor integrated circuit having a test terminal pad with a high input impedance, and lowers the input impedance of the test terminal pad. It is characterized by the built-in impedance reduction circuit.

According to this semiconductor integrated circuit, since the impedance reducing circuit for lowering the input impedance of the test terminal pad is built-in, the function check can be easily performed in a state where it is mounted on a printed circuit board, and then the input impedance is reduced. Highly functional terminal pads function normally even if they are not grounded. That is, by properly designing the impedance reduction circuit, the input impedance of the test terminal pad can be
The function can be checked and the range can be adjusted so as not to adversely affect the normal operation of the semiconductor integrated circuit. By doing so, the processing after the function check becomes unnecessary.

In the preferred embodiment, the impedance reduction circuit is a pull-down circuit comprised of field effect transistors.

That is, by using the field effect transistor as the resistor, the area occupied by the impedance reduction circuit on the chip of the semiconductor integrated circuit can be reduced.

In another preferred embodiment, the impedance reduction circuit is a pull-down circuit including a resistor.

In another preferred embodiment, the impedance reduction circuit is a pull-up circuit composed of field effect transistors.

That is, depending on the circuit configuration of the semiconductor integrated circuit, normal operation may be ensured by pulling up the test terminal pad after the function check. In such a case, the impedance reducing circuit is pulled up. Use a circuit.

In another preferred embodiment, the impedance reduction circuit is a pull-up circuit including a resistor.

Other features and advantages of the present invention will become apparent from the detailed description given below with reference to the accompanying drawings.

[0022]

2 DETAILED DESCRIPTION OF THE INVENTION is a plan view of an information storage device using the semiconductor integrated circuit of the present invention, in this embodiment, E ² employing the I ² C bus interface system as a semiconductor integrated circuit A PROM chip is used.

An E ² PROM chip 1 adopting the I ² C bus interface system is mounted on a printed circuit board 2. The E ² PROM chip 1 includes a ground terminal pad 3, a logic power supply terminal pad 4, a clock signal terminal pad 5, a data in / out terminal pad 6,
A plurality of address terminal pads 7 and 8 and a test terminal pad 9 are provided, and on the printed circuit board 2,
A ground terminal 11, a logic power supply terminal 12, a clock signal terminal 13, and a data in / out terminal 14 are provided as external connection terminals, and a plurality of address terminals 15, 16 and 16 are provided as internal terminals. A test terminal 17 is provided.

The ground terminal pad 3 and the ground terminal 11 are connected via a wire 21 for wire bonding and a printed wiring 22, and the logic power terminal pad 4 and the logic power terminal 12 are connected to each other. Wire 23 for wire bonding and printed wiring 24
And are connected through. The clock signal terminal pad 5 and the clock signal terminal 13 are connected via a wire 25 for wire bonding and a printed wiring 26, and the data-in / out terminal pad 6 and the data-in / out terminal 14 are connected. Are connected via a wire 27 for wire bonding and a printed wiring 28. Address terminal pad 7 and address terminal 1
5 is connected via a wire 29 for wire bonding and a printed wiring 30, and the address terminal pad 8 and the address terminal 16 are connected via a wire 31 for wire bonding and a printed wiring 32. It is connected. The test terminal pad 9 and the test terminal 17 are connected via a wire 33 for wire bonding and a printed wiring 34.

The wire 21 has one end bonded to the ground terminal pad 3 and the other end bonded to the bonding portion 22 a of the printed wiring 22. The wire 23 has one end bonded to the logic power supply terminal pad 4 and the other end bonded to the bonding portion 24 a of the printed wiring 24. Wire 25
One end is bonded to the clock signal terminal pad 5, and the other end is bonded to the bonding portion 26 a of the printed wiring 26. The wire 27 has one end bonded to the data-in / out terminal pad 6 and the other end bonded to the bonding portion 28 a of the printed wiring 28. The wire 29 has one end bonded to the address terminal pad 7 and the other end bonded to the bonding portion 30 a of the printed wiring 30. The wire 31 has one end bonded to the address terminal pad 8 and the other end bonded to the bonding portion 32 a of the printed wiring 32. Wire 33
Has one end bonded to the test terminal pad 9,
The other end is bonded to the bonding portion 34 a of the printed wiring 34.

FIG. 1 is a circuit diagram of a main part of a semiconductor integrated circuit according to the present invention. A circuit body 41 is a general-purpose E adopting a conventional I ² C bus interface system.
² Same as PROM chip. The feature of this semiconductor integrated circuit is that the field effect transistor FET is connected to the circuit wiring 42 connecting the address terminal pad 7 and the circuit body 41.
The drain of the field effect transistor FET2 is connected to the circuit wiring 43 that connects the drain of 1 and connects the address terminal pad 8 and the circuit body 41, and connects the test terminal pad 9 and the circuit body 41. Circuit wiring 44
Is connected to the drain of the field effect transistor FET3. Field effect transistor FET1,
Sources of FET2 and FET3 are ground terminal pads 3
Is connected to the ground, and the gates of the field effect transistors FET1, FET2, and FET3 are connected to the logic power supply terminal pad 4 to supply the logic power supply V _DD . These field-effect transistors FET1, FET2, FET3 are MOS type N-channel field-effect transistors, and have long channel lengths.

That is, the field effect transistor FET
1, FET2, FET3 function as a resistor,
A pull-down circuit is configured as an example of an impedance reducing circuit that lowers the input impedance of the address terminal pads 7 and 8 and the test terminal pad 9.
Therefore, by making the channel length longer,
The resistance value is higher than that of a normal field effect transistor. These field effect transistors FET1 and F
With respect to the resistance value by the ET2 and the FET3, the function check of the circuit body 41 can be performed well, and further, after the function check, the address terminal pads 7 and 8 and the test terminal pad 9 are not grounded. Circuit body 41
Is set to such a range that the input impedance of the address terminal pads 7 and 8 and the test terminal pad 9 is lowered to such an extent that the normal operation is performed.

Next, the operation will be described. At the time of manufacturing the information storage device shown in FIG. 2, the E ² PROM chip 1 is die-bonded to a predetermined portion on the printed board 2 and wire bonding is performed to a required portion. Through the above steps, the information storage device shown in FIG. 2 is obtained. Next, the function check of the E ² PROM chip 1 is performed using the address terminals 15 and 16 and the test terminal 17. The manufacturing of the information storage device is completed by the above steps, and the step of connecting the address terminals 15 and 16 and the test terminal 17 to the printed wiring 22 by a jumper wire or the like and grounding is unnecessary. That is, as shown in FIG. 1, E ² PRO
Field effect transistors FET1 and F are provided inside the M chip 1.
Since the ET2 and the FET3 are provided, the input impedance of the address terminal pads 7 and 8 and the test terminal pad 9 is lowered, so that the address terminal 1
Even if the terminals 5 and 16 and the test terminal 17 are left ungrounded, the normal operation of the E ² PROM chip 1 is not hindered.

As described above, the field effect transistors FET1 and FET2 that form the pull-down circuit functioning as an impedance reducing circuit that lowers the input impedance of the address terminal pads 7 and 8 and the test terminal pad 9 that are the test terminal pads. , FET3 is built-in, so E ² PROM can be mounted on the printed circuit board 2
The function check of the chip 1 can be performed easily, and the E ² PROM chip 1 can function normally even if the subsequent processing such as grounding the address terminal pads 7 and 8 and the test terminal pad 9 is not performed. That is, by appropriately setting the resistance values of the field effect transistors FET1, FET2, FET3, the input impedances of the address terminal pads 7 and 8 and the test terminal pad 9 can be changed to E ² P
Function check of ROM chip 1 is possible and E ² PR
It can be adjusted within a range that does not adversely affect the normal operation of the OM chip 1. By doing so, the processing after the function check becomes unnecessary.

As shown in FIG. 3, resistors R1, R2, R3 may be used instead of the field effect transistors FET1, FET2, FET3 as a pull-down circuit functioning as an impedance reducing circuit. That is, one end of the resistor R1 is connected to the circuit wiring 42 that connects the address terminal pad 7 and the circuit body 41, and the resistor R is connected to the circuit wiring 43 that connects the address terminal pad 8 and the circuit body 41.
2, one end of the resistor R3 is connected to the circuit wiring 44 connecting the test terminal pad 9 and the circuit body 41, and the other ends of the resistors R1, R2 and R3 are connected to the ground terminal pad 3. Ground by making it conductive. Of course, regarding the resistance values of the resistors R1, R2, and R3, the function check of the circuit body 41 can be satisfactorily performed, and further, after the function check, the address terminal pads 7 and 8 and the test terminal pad 9 are
Is set to a range in which the input impedance of the address terminal pads 7 and 8 and the test terminal pad 9 is lowered to such an extent that the circuit main body section 41 normally operates even if no processing such as grounding is performed. .

Even in this case, the same effect as when the field effect transistors FET1, FET2, FET3 are used as the pull-down circuit functioning as the impedance reducing circuit can be obtained. However, rather than the resistors R1, R2, R3, the field effect transistors FET1, FET2, FET
Since the area occupied in the E ² PROM chip 1 can be made smaller, the field effect transistor FE is
It is preferable to use T1, FET2 and FET3.

Depending on the circuit configuration of the circuit body 41, normal operation can be ensured by pulling up the address terminal pads 7 and 8 and the test terminal pad 9 which are the test terminal pads after the function check. In such a case, as the impedance reducing circuit, for example, a pull-up circuit including field effect transistors FET4, FET5, FET6 as shown in FIG. 4 and resistors R4, R5, R6 as shown in FIG. A pull-up circuit consisting of Of course, regarding the resistance values of the field effect transistors FET4, FET5, FET6 or the resistors R4, R5, R6, the function check of the circuit body 41 can be satisfactorily performed, and further, after the function check, the address terminal pads 7 and 8 and the test terminals are used. The address terminal pads 7, to the extent that the circuit body 41 normally operates normally without performing processing such as grounding the terminal pads 9,
8 and the test terminal pad 9 are set to a range that reduces the input impedance.

In FIG. 4, the address terminal pad 7 is used.
The drain of the field effect transistor FET4 is connected to the circuit wiring 42 connecting the circuit main body 41 with the circuit wiring 43 connecting the address terminal pad 8 and the circuit main body 41. The field effect transistor FET is connected to the circuit wiring 44 that is connected and connects the test terminal pad 9 and the circuit body 41.
The drains of 6 are connected. The gates of the field effect transistors FET4, FET5, FET6 are grounded by being connected to the ground terminal pad 3, and the sources of the field effect transistors FET4, FET5, FET6 are connected to the logic power supply terminal pad 4. The logic power supply V _DD is supplied. These field effect transistors FET4, FET5, FET6 are MO
It is an S-type P-channel field effect transistor and has a long channel length.

In FIG. 5, the address terminal pad 7
To the circuit wiring 42 connecting the circuit main body 41 with the resistor R4.
To the circuit wiring 43 connecting the address terminal pad 8 and the circuit body 41 to the circuit wiring 44 connecting the test terminal pad 9 and the circuit body 41. Connect one end of resistor R6 to
The power supply V _DD is supplied by connecting the other ends of 4, R5 and R6 to the logic power supply terminal pad 4.

The specific circuit configuration of the impedance reduction circuit is not limited to the above-mentioned embodiments, and various circuit configurations can be adopted.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a main part of a semiconductor integrated circuit of the present invention.

FIG. 2 shows E ² as an example of a semiconductor integrated circuit of the present invention.
It is a top view of the information storage device which used the PROM chip.

FIG. 3 is a circuit diagram of a main part of a semiconductor integrated circuit according to another embodiment.

FIG. 4 is a circuit diagram of a main part of a semiconductor integrated circuit according to still another embodiment.

FIG. 5 is a circuit diagram of a main part of a semiconductor integrated circuit according to still another embodiment.

FIG. 6 is an E ² PR as an example of a conventional semiconductor integrated circuit.
It is a top view of the information storage device using an OM chip.

[Explanation of symbols]

1 E ² PROM chip 7 address terminal pad 8 address terminal pad 9 test terminal pad FET1 to FET6 field effect transistors R1 to R6 resistance

Claims (5)

[Claims] 1. A semiconductor integrated circuit having a test terminal pad with a high input impedance, wherein an impedance reduction circuit for reducing the input impedance of the test terminal pad is incorporated. 2. The semiconductor integrated circuit according to claim 1, wherein the impedance reduction circuit is a pull-down circuit including a field effect transistor. 3. The semiconductor integrated circuit according to claim 1, wherein the impedance reduction circuit is a pull-down circuit including a resistor. 4. The semiconductor integrated circuit according to claim 1, wherein the impedance reduction circuit is a pull-up circuit including a field effect transistor. 5. The semiconductor integrated circuit according to claim 1, wherein the impedance reduction circuit is a pull-up circuit including a resistor.