JP2000357909A - Manufacture of chip-like electronic component - Google Patents

Manufacture of chip-like electronic component

Info

Publication number
JP2000357909A
JP2000357909A JP11167967A JP16796799A JP2000357909A JP 2000357909 A JP2000357909 A JP 2000357909A JP 11167967 A JP11167967 A JP 11167967A JP 16796799 A JP16796799 A JP 16796799A JP 2000357909 A JP2000357909 A JP 2000357909A
Authority
JP
Japan
Prior art keywords
chip
substrate
shaped
shaped substrate
base material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11167967A
Other languages
Japanese (ja)
Other versions
JP3632504B2 (en
Inventor
Yasuhiro Tanaka
康廣 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP16796799A priority Critical patent/JP3632504B2/en
Publication of JP2000357909A publication Critical patent/JP2000357909A/en
Application granted granted Critical
Publication of JP3632504B2 publication Critical patent/JP3632504B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To easily form the side conductor pattern of chip-like electronic parts with satisfactory positional accuracy. SOLUTION: A base material substrate body 6 for forming plural chip-like substrate bodies 2 constituting chip-like electronic components is prepared. The plural base material substrate bodies 6 are laminated. The laminated body of the base material substrate bodies 6 is divided at every row group 10 or column group 11 of the chip-like substrate body 2. A side conductor pattern is formed in the side forming areas 12 of the chip-like substrate bodies 2 in the row group 10 or the column group 11 of the chip-like substrate bodies 2. Namely, the side conductor pattern is formed into the chip-like substrate bodies 2, before the respective chip-like substrate bodies 2 are separated. The row group 10 or the column group 11 of the chip-like substrate bodies 2 are divided by each column or row in the chip-like substrate bodies 2 and the laminated bodies 13 of the chip-like substrate bodies 2 are formed. Then, the laminated bodies 13 of the chip-like substrate bodies 2 are separated by each chip-like substrate body 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、チップ状アンテナ
素子等のチップ状電子部品の製造方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a chip-shaped electronic component such as a chip-shaped antenna element.

【0002】[0002]

【従来の技術】図3にはチップ状電子部品であるチップ
状アンテナ素子の一例が示されている。この図3に示す
ように、このチップ状アンテナ素子1は表面実装タイプ
のアンテナ素子であり、チップ状基板体2を有してい
る。このチップ状基板体2はセラミックス等の誘電体に
より形成されており、その側面には、放射電極3と接地
電極4と給電電極5が形成されている。この図3に示す
例では、上記放射電極3は上記チップ状基板体2の側面
2aから側面2bを経て側面2cに至る領域に形成さ
れ、上記接地電極4は上記放射電極3に連通してチップ
状基板体2の側面2dの全面に形成されている。また、
給電電極5は上記放射電極3の端部3aと接地電極4の
端部4aとによって挟まれた領域に形成され、該給電電
極5は上記放射電極3および接地電極4と互いに間隔を
介して配置形成されている。
2. Description of the Related Art FIG. 3 shows an example of a chip antenna element which is a chip electronic component. As shown in FIG. 3, the chip-shaped antenna element 1 is a surface-mount type antenna element and has a chip-shaped substrate 2. The chip-shaped substrate 2 is formed of a dielectric material such as ceramics, and a radiation electrode 3, a ground electrode 4, and a power supply electrode 5 are formed on side surfaces thereof. In the example shown in FIG. 3, the radiation electrode 3 is formed in a region extending from the side surface 2 a to the side surface 2 c via the side surface 2 b of the chip-shaped substrate 2, and the ground electrode 4 communicates with the radiation electrode 3 and It is formed on the entire side surface 2 d of the substrate 2. Also,
The power supply electrode 5 is formed in a region sandwiched between the end 3a of the radiation electrode 3 and the end 4a of the ground electrode 4, and the power supply electrode 5 is arranged at an interval from the radiation electrode 3 and the ground electrode 4. Is formed.

【0003】上記構成のチップ状アンテナ素子1におい
て、上記給電電極5には電圧印加手段(図示せず)が導
通接続され、この電圧印加手段によって給電電極5に電
圧が印加されると、放射電極3の端面3aと給電電極5
の端面5aとの間に静電容量が発生し、この静電容量に
よる容量結合によって、放射電極3が励振され、共振型
の表面実装型のアンテナとして動作する。
In the chip-shaped antenna element 1 having the above structure, a voltage applying means (not shown) is electrically connected to the power supply electrode 5, and when a voltage is applied to the power supply electrode 5 by the voltage application means, the radiation electrode is turned off. 3 and the power supply electrode 5
A capacitance is generated between the end face 5a and the radiating electrode 3 due to capacitive coupling by the capacitance, and the antenna operates as a resonance type surface mount antenna.

【0004】上記構成のチップ状アンテナ素子1は次に
示すように製造されていた。まず、図4の(a)に示す
ような母材基板体6から複数のチップ状基板体2を図4
の(b)に示すように切り出し、次に、個々のチップ状
基板体2毎に、チップ状基板体2の側面に上記したよう
な放射電極3、接地電極4、給電電極5を形成する。
[0004] The chip-shaped antenna element 1 having the above configuration has been manufactured as follows. First, a plurality of chip-like substrate bodies 2 are separated from a base material substrate body 6 as shown in FIG.
(B), and the radiation electrode 3, the ground electrode 4, and the power supply electrode 5 as described above are formed on the side surface of the chip-shaped substrate 2 for each chip-shaped substrate 2.

【0005】上記放射電極3や接地電極4や給電電極5
の形成手法には様々な手法があるが、次に示すように形
成される。例えば、まず、上記チップ状基板体2の表面
全面に導電材料を形成し、次に、その導電材料の表面
に、フォトレジスト法を用いて、エッチングレジストを
放射電極3、接地電極4、給電電極5の形成領域に被覆
形成する。そして、上記エッチングレジストが被覆され
ていない部分の導電材料をエッチング液によりエッチン
グ除去する。このようにして、放射電極3、接地電極
4、給電電極5が形成される。
[0005] The radiation electrode 3, the ground electrode 4, and the power supply electrode 5
Although there are various methods for forming the image, the following method is used. For example, first, a conductive material is formed on the entire surface of the chip-shaped substrate body 2, and then, using a photoresist method, an etching resist is applied to the surface of the conductive material by using the radiation electrode 3, the ground electrode 4, and the power supply electrode. A coating is formed on the formation region of No. 5. Then, a portion of the conductive material which is not covered with the etching resist is removed by etching with an etching solution. Thus, the radiation electrode 3, the ground electrode 4, and the power supply electrode 5 are formed.

【0006】このように、放射電極3、接地電極4、給
電電極5を形成した後には、必要に応じて、放射電極3
と給電電極5の間に発生する静電容量を所定値にするた
めの調整が行われる。つまり、放射電極3と給電電極5
間の静電容量が所定値よりも上回っているときには、放
射電極3と給電電極5の一方あるいは両方をトリミング
して放射電極3の端面3aと給電電極5の端面5aとの
間の間隔を広げたり、あるいは、上記トリミングによっ
て放射電極3の端面3aと給電電極5の端面5aの対向
面積を減少させて上記放射電極3と給電電極5間の静電
容量を所定値に向けて小さくする方向に調整する。ま
た、チップ状基板体2の表面処理等が適宜行われて、チ
ップ状アンテナ素子1の製造が完了する。
After the radiation electrode 3, the ground electrode 4, and the power supply electrode 5 are formed as described above, the radiation electrode 3, the
An adjustment is made to make the capacitance generated between the power supply electrode 5 and the power supply electrode 5 a predetermined value. That is, the radiation electrode 3 and the feeding electrode 5
When the capacitance between the electrodes is larger than a predetermined value, one or both of the radiation electrode 3 and the power supply electrode 5 are trimmed to increase the distance between the end face 3a of the radiation electrode 3 and the end face 5a of the power supply electrode 5. Or, by reducing the facing area between the end face 3a of the radiation electrode 3 and the end face 5a of the power supply electrode 5 by the trimming, in a direction to decrease the capacitance between the radiation electrode 3 and the power supply electrode 5 toward a predetermined value. adjust. In addition, the surface treatment of the chip-shaped substrate body 2 is appropriately performed, and the manufacture of the chip-shaped antenna element 1 is completed.

【0007】[0007]

【発明が解決しようとする課題】従来では、上記のよう
に、母材基板体6からチップ状基板体2を切り出した後
に、その切り出したチップ状基板体2の側面に上記放射
電極3、接地電極4、給電電極5を形成していた。しか
しながら、チップ状基板体2は非常に微細であり、その
微細なチップ状基板体2の側面に前記フォトレジスト法
等を利用した電極形成加工を施して上記放射電極3、接
地電極4、給電電極5を位置精度良く形成するのは非常
に困難であった。
Conventionally, as described above, after the chip-shaped substrate 2 is cut out from the base material substrate 6, the radiation electrode 3 and the ground are provided on the side surfaces of the cut-out chip-shaped substrate 2. The electrode 4 and the power supply electrode 5 were formed. However, the chip-shaped substrate body 2 is very fine, and the side surfaces of the fine chip-shaped substrate body 2 are subjected to an electrode forming process using the photoresist method or the like, and the radiation electrode 3, the ground electrode 4, and the power supply electrode are formed. It was very difficult to form 5 with good positional accuracy.

【0008】また、上記のように、個々のチップ状基板
体2毎にそれぞれ上記電極3,4,5を形成するので、
生産性が非常に低いという問題があった。
Further, as described above, the electrodes 3, 4, and 5 are formed for each individual chip-shaped substrate 2, so that
There was a problem that productivity was very low.

【0009】そこで、上記チップ状基板体2を治具に並
べて複数のチップ状基板体2に上記放射電極3や接地電
極4や給電電極5を一括的に形成することが考えられる
が、チップ状基板体2を治具の所定位置に精度良く並べ
なければならず、その作業は面倒である上に、慎重にチ
ップ状基板体2を治具に並べてもチップ状基板体2が所
定値からずれて配置される場合が多く、この位置ずれに
起因してチップ状基板体2の側面に位置精度良く放射電
極3、接地電極4、給電電極5を形成することができな
いという問題が生じてしまう。
In view of this, it is conceivable to arrange the chip-shaped substrate bodies 2 on a jig and collectively form the radiation electrode 3, the ground electrode 4, and the power supply electrode 5 on a plurality of chip-shaped substrate bodies 2. The substrate 2 must be accurately arranged at a predetermined position on the jig, and the work is troublesome. In addition, even if the chip-like substrate 2 is carefully arranged on the jig, the chip-like substrate 2 is deviated from a predetermined value. In many cases, the radiation electrode 3, the ground electrode 4, and the power supply electrode 5 cannot be formed on the side surface of the chip-shaped substrate 2 with high positional accuracy due to the positional shift.

【0010】本発明は上記課題を解決するために成され
たものであり、その目的は、チップ状基板体の側面に側
面導体パターンを容易に、しかも、位置精度良く形成す
ることを可能とするチップ状電子部品の製造方法に関す
るものである。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to make it possible to easily form a side conductor pattern on the side surface of a chip-shaped substrate body with high positional accuracy. The present invention relates to a method for manufacturing a chip-shaped electronic component.

【0011】[0011]

【課題を解決するための手段】上記目的を達成するため
に、この発明は次に示すような構成をもって前記課題を
解決する手段としている。すなわち、第1の発明は、チ
ップ状基板体の側面には導電材料が予め定められたパタ
ーンでもって形成されて側面導体パターンが構成されて
いるチップ状電子部品の製造方法であって、複数の上記
チップ状基板体を形成するための母材基板体を用意し、
まず、上記複数の母材基板体を積層し、次に、上記母材
基板体の積層体を予め定めたチップ状基板体の行列配置
の行又は列群毎に切り分け、その後、上記チップ状基板
体の行又は列群における各チップ状基板体の側面形成領
域にそれぞれ上記側面導体パターンを形成し、然る後
に、上記チップ状基板体の行又は列群をチップ状基板体
の列又は行毎に切り分けてチップ状基板体の積層体と成
し、次に、そのチップ状基板体の積層体を各チップ状基
板体毎に分離する構成をもって前記課題を解決する手段
としている。
In order to achieve the above-mentioned object, the present invention provides means for solving the above-mentioned problems with the following arrangement. That is, a first invention is a method of manufacturing a chip-shaped electronic component in which a conductive material is formed on a side surface of a chip-shaped substrate body in a predetermined pattern to form a side-surface conductor pattern. Prepare a base material substrate for forming the chip-shaped substrate,
First, the plurality of base material substrate bodies are stacked, and then, the stacked body of the base material substrate bodies is divided into predetermined rows or columns of a matrix arrangement of chip-shaped substrate bodies, and thereafter, the chip-shaped substrate bodies are separated. The above-mentioned side conductor pattern is formed in each of the side surface forming regions of each chip-shaped substrate body in the row or column group of the body, and thereafter, the row or column group of the chip-shaped substrate body is divided into columns or rows of the chip-shaped substrate body. This is a means for solving the above-mentioned problem by a structure in which a laminate of chip-shaped substrate bodies is formed by dividing the chip-shaped substrate body, and then the laminate of chip-shaped substrate bodies is separated for each chip-shaped substrate body.

【0012】第2の発明は、上記第1の発明の構成を備
え、母材基板体を複数積層する際には、それら複数の母
材基板体を接合材料を用いて一体化する構成とし、チッ
プ状基板体の積層体を各チップ状基板体毎に分離する際
に、上記接合材料の接合力を低下させてチップ状基板体
の積層体を各チップ状基板体毎に分離することを特徴と
して構成されている。
According to a second aspect of the present invention, there is provided the configuration of the first aspect of the invention, wherein when a plurality of base material substrates are stacked, the plurality of base material substrates are integrated using a bonding material. When separating the laminated body of the chip-shaped substrate into each chip-shaped substrate, the bonding force of the bonding material is reduced to separate the laminated body of the chip-shaped substrate into each chip-shaped substrate. Is configured as

【0013】第3の発明は、上記第1又は第2の発明の
構成を備え、チップ状電子部品はチップ状アンテナ素子
であることを特徴として構成されている。
According to a third aspect of the present invention, there is provided the configuration of the first or second aspect, wherein the chip-shaped electronic component is a chip-shaped antenna element.

【0014】上記構成の発明において、例えば、母材基
板体の積層体を予め定めたチップ状基板体の行列配置の
行又は列群毎に切り分けた後に、そのチップ状基板体の
行又は列群における各チップ状基板体の側面形成領域に
それぞれ側面導体パターンを形成する。つまり、各チッ
プ状基板体毎に分離する前に、各チップ状基板体に側面
導体パターンを形成する。
In the invention having the above-described structure, for example, after the stacked body of the base material substrate is cut into predetermined rows or columns of the matrix arrangement of the chip-shaped substrate, the rows or columns of the chip-shaped substrate are separated. A side conductor pattern is formed in each of the side surface forming regions of each chip-shaped substrate body. That is, before separating each chip-shaped substrate, a side conductor pattern is formed on each chip-shaped substrate.

【0015】上記のようにチップ状基板体の行又は列群
における各チップ状基板体の側面形成領域にそれぞれ側
面導体パターンを形成した後に、各チップ状基板体毎に
分離する。このようにして、チップ状電子部品を製造す
る。
After the side conductor patterns are formed in the side surface forming regions of each chip substrate in the row or column group of the chip substrate as described above, each chip substrate is separated. Thus, a chip-shaped electronic component is manufactured.

【0016】上記チップ状基板体の行又は列群はチップ
状基板体よりも大きく、チップ状基板体の行又は列群に
おける各チップ状基板体には、微細なチップ状基板体毎
に側面導体パターンを形成する場合よりも容易に、か
つ、位置精度良く側面導体パターンを形成することが可
能である。
The row or column group of the chip-shaped substrate is larger than the chip-shaped substrate, and each chip-shaped substrate in the row or column group of the chip-shaped substrate is provided with a side conductor for each fine chip-shaped substrate. It is possible to form the side conductor pattern more easily and with higher positional accuracy than when forming the pattern.

【0017】このため、チップ状基板体を大型化するこ
となく、チップ状基板体の側面に複雑な側面導体パター
ンを形成することが可能となり、チップ状電子部品に対
して要求される側面導体パターンの複雑化(回路網の高
密度化)に十分に対応することが可能なチップ状電子部
品を提供することができる。
For this reason, it is possible to form a complicated side conductor pattern on the side surface of the chip substrate without enlarging the chip substrate, and the side conductor pattern required for the chip electronic component can be formed. It is possible to provide a chip-shaped electronic component capable of sufficiently coping with the complexity of the semiconductor device (increasing the density of a circuit network).

【0018】また、上記したように、各チップ状基板体
毎に分離する前にチップ状基板体に側面導体パターンを
形成するので、複数のチップ状基板体に側面導体パター
ンを一括的に形成することができ、このことに起因して
チップ状電子部品の生産性を飛躍的に向上させることが
できる。
Further, as described above, since the side conductor pattern is formed on the chip substrate before separation into each chip substrate, the side conductor pattern is collectively formed on a plurality of chip substrates. As a result, the productivity of chip-shaped electronic components can be significantly improved.

【0019】[0019]

【発明の実施の形態】以下に、この発明に係る実施形態
例を図面に基づき説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0020】この実施形態例では、前記図3に示すよう
なチップ状電子部品であるチップ状アンテナ素子を対象
としている。つまり、チップ状基板体2を有し、該チッ
プ状基板体2の側面には導電材料が予め定めたパターン
でもって露出形成されて側面導体パターンである放射電
極3と接地電極4と給電電極5が形成されているチップ
状電子部品を対象としている。この実施形態例では、上
記チップ状アンテナ素子の製造工程に特徴があり、以下
に、その特徴的なチップ状アンテナ素子の製造工程を説
明する。
This embodiment is directed to a chip antenna element which is a chip electronic component as shown in FIG. That is, it has a chip-shaped substrate 2, and a conductive material is exposed and formed on a side surface of the chip-shaped substrate 2 in a predetermined pattern to form a radiation electrode 3, a ground electrode 4, and a power supply electrode 5 which are side conductor patterns. It is intended for a chip-shaped electronic component on which is formed. This embodiment is characterized in the manufacturing process of the above-mentioned chip-shaped antenna element, and the manufacturing process of the characteristic chip-shaped antenna element will be described below.

【0021】まず、チップ状アンテナ素子のチップ状基
板体2を複数形成するための図4に示すような母材基板
体6を用意する。次に、図1の(a)に示すように、複
数の母材基板体6を積層する。この場合、複数の母材基
板体6は接合材料を用いて一体化される。上記接合材料
は、例えば、有機接着剤や、糊や、油脂や、樹脂や、鑞
付け材等であり、酸性あるいはアルカリ性の溶剤や、水
や、有機溶剤や、熱や、光等によって接合力が低下する
接合材料である。
First, a base material body 6 as shown in FIG. 4 for forming a plurality of chip-like substrate bodies 2 of chip-like antenna elements is prepared. Next, as shown in FIG. 1A, a plurality of base material substrates 6 are stacked. In this case, the plurality of base material substrates 6 are integrated using a bonding material. The bonding material is, for example, an organic adhesive, a glue, a fat, a resin, a brazing material, or the like, and has a bonding strength of an acidic or alkaline solvent, water, an organic solvent, heat, light, or the like. This is a bonding material having a reduced value.

【0022】その後、図1の(b)に示すように、上記
母材基板体6の積層体を予め定めたチップ状基板体2の
行列配置の行群10毎に、あるいは、図1の(c)に示
すような列群11毎に切り分ける。なお、上記母材基板
体6の積層体を切り分ける手法にはワイヤーカット等の
様々な手法があり、ここでは、それら手法のうちの何れ
の手法を用いて母材基板体6の積層体を切り分けてもよ
く、その切り分け手法の説明は省略する。
Thereafter, as shown in FIG. 1B, the laminated body of the base material substrates 6 is divided into predetermined rows and columns 10 of the matrix arrangement of the chip-shaped substrate 2, or as shown in FIG. It is divided for each column group 11 as shown in c). Note that there are various methods such as wire cutting for separating the stacked body of the base material substrate 6. Here, any of these methods is used to separate the stacked structure of the base material substrate 6. The description of the dividing method may be omitted.

【0023】次に、上記チップ状基板体2の行群10あ
るいは列群11における各チップ状基板体の側面形成領
域12にそれぞれ予め定められた側面導体パターンを形
成する。この側面導体パターンの形成手法には様々な手
法があり、ここでは、それら手法のうちの何れの手法を
用いてもよく、その説明は省略する。
Next, predetermined side conductor patterns are formed in the side surface forming regions 12 of each chip substrate in the row group 10 or the column group 11 of the chip substrate 2, respectively. There are various methods for forming the side-surface conductor pattern. Here, any of these methods may be used, and description thereof will be omitted.

【0024】図3に示すチップ状アンテナ素子1は、チ
ップ状基板体2の4側面の全てに側面導体パターンが形
成されているので、この工程では、チップ状基板体2の
4側面のうちの2側面に側面導体パターンが形成される
こととなる。
In the chip-shaped antenna element 1 shown in FIG. 3, since the side conductor patterns are formed on all four side surfaces of the chip-shaped substrate 2, in this step, of the four side surfaces of the chip-shaped substrate 2, Side conductor patterns are formed on the two side surfaces.

【0025】然る後に、図1の(d)に示すように、上
記チップ状基板体2の行群10又は列群11を各チップ
状基板体の列あるいは行毎に切り分けてチップ状基板体
2の積層体13を形成する。この切り分けによって露出
したチップ状基板体2の側面形成領域に残りの側面導体
パターンを形成する。この工程における側面導体パター
ン形成手法に関しても、上記同様に、複数の形成手法の
中から適宜に選択された手法によって側面導体パターン
を形成してよく、ここでは、その説明は省略する。
Thereafter, as shown in FIG. 1D, the row group 10 or the column group 11 of the chip substrate 2 is divided into columns or rows of each chip substrate to form a chip substrate. A second laminate 13 is formed. The remaining side conductor pattern is formed in the side surface forming region of the chip-shaped substrate body 2 exposed by the cutting. As for the side conductor pattern forming method in this step, the side conductor pattern may be formed by a method appropriately selected from a plurality of forming methods, as described above, and the description thereof is omitted here.

【0026】次に、図1の(e)に示すように、例えば
溶剤や熱や光等を利用した所定の手法によって前記接合
材料の接合力を低下させて上記チップ状基板体の積層体
13を各チップ状基板体2毎に分離する。
Next, as shown in FIG. 1E, the bonding force of the bonding material is reduced by a predetermined method using, for example, a solvent, heat, light, or the like to reduce the bonding strength of the chip-like substrate 13. Is separated for each chip-shaped substrate 2.

【0027】その後、必要に応じて、前記したような放
射電極3と給電電極5間の静電容量を調整するためのト
リミングを行ったり、導体パターン保護用の部材や機能
強化用のメッキを施す等の表面処理を行う。
Thereafter, if necessary, trimming for adjusting the capacitance between the radiation electrode 3 and the feed electrode 5 as described above is performed, or a member for protecting the conductor pattern or plating for enhancing the function is applied. And other surface treatments.

【0028】上記のような製造工程により、チップ状電
子部品の製造が完成する。
Through the above manufacturing steps, the manufacture of the chip-shaped electronic component is completed.

【0029】この実施形態例によれば、チップ状基板体
2の行群10又は列群11や、チップ状基板体2の積層
体13の状態で、各チップ状基板体2に側面導体パター
ンを形成する構成であり、そのチップ状基板体2の行群
10又は列群11や、チップ状基板体2の積層体13は
チップ状基板体2よりも大きく、上記チップ状基板体2
の行群10又は列群11や、チップ状基板体2の積層体
13の状態での各チップ状基板体2には、非常に微細な
チップ状基板体2に側面導体パターンを形成する場合に
比べて、容易に側面導体パターンを形成することができ
る。しかも、各チップ状基板体2に位置精度良く側面導
体パターンを形成することができる。
According to this embodiment, in the state of the row group 10 or the column group 11 of the chip-shaped substrate body 2 and the stacked body 13 of the chip-shaped substrate body 2, the side conductor pattern is formed on each chip-shaped substrate body 2. The row group 10 or the column group 11 of the chip-shaped substrate 2 and the stacked body 13 of the chip-shaped substrate 2 are larger than the chip-shaped substrate 2.
The row group 10 or the column group 11 and the respective chip-shaped substrate bodies 2 in the state of the stacked body 13 of the chip-shaped substrate bodies 2 are used when forming a side conductor pattern on a very fine chip-shaped substrate body 2. In comparison, the side conductor pattern can be easily formed. Moreover, the side conductor pattern can be formed on each chip-shaped substrate 2 with high positional accuracy.

【0030】このように、チップ状基板体2の側面に位
置精度良く側面導体パターンを形成することができるの
で、側面導体パターンの位置ずれに起因したチップ状電
子部品の歩留まり低下の問題を防止することができる。
As described above, since the side conductor pattern can be formed on the side surface of the chip-shaped substrate body 2 with high positional accuracy, the problem of a decrease in the yield of chip-shaped electronic components due to the displacement of the side conductor pattern can be prevented. be able to.

【0031】また、上記のように、この実施形態例で
は、チップ状基板体2の行群10又は列群11やチップ
状基板体2の積層体13の状態で、つまり、個々のチッ
プ状基板体2毎に分離する前に側面導体パターンを形成
するので、複数のチップ状基板体2に一括的に側面導体
パターンを形成することができることとなり、従来のよ
うに、母材基板体6から切り出された微細な各チップ状
基板体2毎に1個ずつ側面導体パターンを形成する場合
に比べて、格段に、チップ状電子部品の生産性を向上さ
せることができる。
As described above, in this embodiment, in the state of the row group 10 or the column group 11 of the chip-like substrate 2 and the stacked body 13 of the chip-like substrate 2, that is, each chip-like substrate 2 Since the side conductor pattern is formed before separation for each body 2, the side conductor pattern can be collectively formed on a plurality of chip-shaped substrate bodies 2. The productivity of chip-shaped electronic components can be remarkably improved as compared with the case where one side conductor pattern is formed for each fine chip-shaped substrate body 2 obtained.

【0032】上記のように、チップ状電子部品の歩留ま
り向上と生産性向上によって、チップ状電子部品の価格
を抑制することができる上に、上述したように、複雑な
側面導体パターンを容易に形成することができるので、
安価で、高性能なチップ状アンテナ素子1を提供するこ
とが可能になるという画期的な効果を得ることができ
る。
As described above, by improving the yield and productivity of the chip-shaped electronic components, the price of the chip-shaped electronic components can be suppressed, and as described above, a complicated side conductor pattern can be easily formed. So you can
An epoch-making effect of being able to provide an inexpensive and high-performance chip-shaped antenna element 1 can be obtained.

【0033】なお、この発明は、上記実施形態例に限定
されるものではなく、様々な実施の形態を採り得る。例
えば、上記実施形態例では、図3に示すようなチップ状
アンテナ素子1を例にして説明したが、本発明は、チッ
プ状アンテナ素子1に限定されるものではなく、チップ
状基板体2の側面に側面導体パターンが形成されている
チップ状電子部品であれば適用することができる。
It should be noted that the present invention is not limited to the above embodiment, but can adopt various embodiments. For example, in the embodiment described above, the chip-shaped antenna element 1 as shown in FIG. 3 has been described as an example, but the present invention is not limited to the chip-shaped antenna element 1, and the chip-shaped substrate 2 The present invention can be applied to any chip-shaped electronic component having a side surface conductive pattern formed on the side surface.

【0034】チップ状基板体2に導体パターンが形成さ
れて回路網が形成されているチップ状電子部品に、本発
明を適用する場合には、上記したように、チップ状基板
体2の側面に複雑な側面導体パターンを容易に、しか
も、位置精度良く形成することができるので、チップ状
基板体2を大型化することなく、複雑な側面導体パター
ンを容易に製造することが可能となり、ますます要求さ
れる導体パターンの複雑化(回路網の高密度化)に十分
に対応できるチップ状電子部品を得ることができる。
When the present invention is applied to a chip-like electronic component having a circuit pattern formed by forming a conductor pattern on the chip-like substrate 2, as described above, the side surface of the chip-like substrate 2 Since complex side conductor patterns can be formed easily and with high positional accuracy, complicated side conductor patterns can be easily manufactured without increasing the size of the chip-shaped substrate 2. It is possible to obtain a chip-shaped electronic component that can sufficiently cope with the required complexity of the conductor pattern (higher density of a circuit network).

【0035】例えば、図3に示す例では、チップ状基板
体2の表面(上面)と底面には導電材料が形成されてい
なかったが、チップ状基板体2の表面と底面の一方又は
両方に導電材料を予め定められたパターンでもって形成
して導体パターンを形成してもよい。
For example, in the example shown in FIG. 3, no conductive material is formed on the surface (upper surface) and the bottom surface of the chip-shaped substrate 2, but one or both of the surface and the bottom of the chip-shaped substrate 2 are provided. A conductive pattern may be formed by forming a conductive material in a predetermined pattern.

【0036】このように、チップ状基板体2の表面と底
面の一方又は両方に導体パターンが形成される場合に
は、まず、母材基板体6における各チップ状基板体2の
表面形成領域又は底面形成領域にそれぞれ予め定められ
た導体パターンを一括的に形成し、その後に、図1の
(a)に示すように、複数の母材基板体6を積層する。
As described above, when the conductor pattern is formed on one or both of the surface and the bottom surface of the chip-shaped substrate 2, first, the surface-forming region of each chip-shaped substrate 2 in the base material substrate 6 or A predetermined conductor pattern is collectively formed in each of the bottom surface forming regions, and thereafter, a plurality of base material substrates 6 are stacked as shown in FIG.

【0037】また、チップ状電子部品の側面導体パター
ンの形状は図3に示す側面導体パターンの形状に限定さ
れることなく、適宜の形状を採り得ることが可能であ
る。
Further, the shape of the side conductor pattern of the chip-shaped electronic component is not limited to the shape of the side conductor pattern shown in FIG. 3, but can take an appropriate shape.

【0038】さらに、上記実施形態例では、チップ状基
板体2の4側面の全てに導電材料が形成されて側面導体
パターンが形成されていたが、チップ状基板体2の4側
面のうちの選択された3面以下の側面に側面導体パター
ンを形成してもよい。
Further, in the above embodiment, the conductive material is formed on all four side surfaces of the chip-shaped substrate body 2 to form the side-surface conductor pattern. The side conductor pattern may be formed on the three or less sides.

【0039】さらに、上記実施形態例では、チップ状基
板体2は誘電体により構成されていたが、チップ状基板
体2は、例えば、ガラス、セラミックス、シリコン、樹
脂、絶縁材が被覆された金属材等の様々な材料の中から
選定された適宜の材料により構成してよい。
In the above embodiment, the chip-shaped substrate 2 is made of a dielectric material. However, the chip-shaped substrate 2 may be made of, for example, glass, ceramics, silicon, resin, or a metal coated with an insulating material. It may be made of an appropriate material selected from various materials such as materials.

【0040】さらに、上記実施形態例では、チップ状基
板体2は1枚の基板により構成されていたが、例えば、
チップ状基板体2は複数の基板が積層形成された構成と
してもよい。この場合には、チップ状基板体2を構成す
る基板(以下、チップ構成基板と記す)を複数形成する
ための基板が複数枚用意され、それら基板が積層されて
母材基板体6が形成される。
Further, in the above embodiment, the chip-shaped substrate 2 is constituted by one substrate.
The chip-shaped substrate 2 may have a configuration in which a plurality of substrates are stacked. In this case, a plurality of substrates for forming a plurality of substrates (hereinafter, referred to as chip configuration substrates) constituting the chip-shaped substrate body 2 are prepared, and the substrates are stacked to form the base material substrate body 6. You.

【0041】このように、チップ状基板体2がチップ構
成基板の積層体により構成される場合には、上記チップ
構成基板の表面と底面の一方あるいは両方に導体パター
ンが形成されていてもよい。また、チップ構成基板には
必要に応じてスルーホールが形成されていてもよく、こ
のように形成することにより、チップ状基板体2の内部
に回路を構成することができ、より一層の回路網の高密
度化を図ることができる。
As described above, when the chip-shaped substrate 2 is formed of a laminate of chip-configured substrates, a conductor pattern may be formed on one or both of the front and bottom surfaces of the chip-configured substrate. Further, through holes may be formed in the chip-constituting substrate as necessary. By forming in this way, a circuit can be formed inside the chip-shaped substrate body 2 and a further circuit network Density can be increased.

【0042】さらに、上記実施形態例では、母材基板体
6の積層体を、チップ状基板体2の1行の行群10、あ
るいは、1列の列群11毎に切り分けていたが、例え
ば、チップ状基板体2の4側面のうちの3面以下の側面
に側面導体パターンを形成する場合には、母材基板体6
の積層体を、図2の(a)に示すようにチップ状基板体
2の2行の行群10、あるいは、図2の(b)に示すよ
うにチップ状基板体2の2列の列群11毎に、切り分け
てもよい。
Further, in the above embodiment, the laminated body of the base material substrate 6 is divided into one row group 10 or one column group 11 of the chip-shaped substrate body 2. In the case where the side conductor pattern is formed on three or less of the four side surfaces of the chip-shaped substrate body 2, the base material substrate body 6
The stacked body of FIG. 2 is divided into two rows 10 of the chip-shaped substrate 2 as shown in FIG. 2A, or two columns of the chip-shaped substrate 2 as shown in FIG. It may be divided for each group 11.

【0043】さらに、チップ状電子部品のチップ状基板
体2には、必要に応じて、表面側から底面側に貫通する
スルーホールや、表面あるいは底面に凹・凸部を設けて
もよい。このように、チップ状基板体2にスルーホール
や凹・凸部を設ける場合に、例えば、母材基板体6(チ
ップ状基板体2)がセラミックスであるときには、セラ
ミックスの焼成成形時に母材基板体6を成形すると共に
各チップ状基板体2の形成領域に上記スルーホールや凹
・凸部を同時に形成してもよい。また、母材基板体6が
樹脂により構成されている場合には、母材基板体6の型
成形時に同時に上記スルーホールや凹・凸部を形成して
もよい。また、成形後の母材基板体6における各チップ
状基板体2の形成領域に上記スルーホールや凹・凸部を
設けてもよい。上記のように、各チップ状基板体2毎に
分離する前に上記スルーホールや凹・凸部を設けること
が望ましいが、各チップ状基板体2毎に分離した後に、
各チップ状基板体2にスルーホールや凹・凸部を設けて
もよい。
Further, the chip-shaped substrate 2 of the chip-shaped electronic component may be provided with a through hole penetrating from the front side to the bottom side, or a concave / convex portion on the front side or the bottom side, as necessary. As described above, when the through holes and the concave / convex portions are provided in the chip-shaped substrate body 2, for example, when the base material substrate body 6 (chip-shaped substrate body 2) is ceramic, the base material substrate is formed at the time of firing and forming the ceramic. The through hole and the concave / convex portions may be simultaneously formed in the formation area of each chip-shaped substrate body 2 while the body 6 is formed. When the base material substrate 6 is made of a resin, the through holes and the concave / convex portions may be formed simultaneously with the molding of the base material substrate 6. Further, the through-holes and the concave / convex portions may be provided in the formation region of each chip-shaped substrate body 2 in the formed base material substrate body 6. As described above, it is desirable to provide the through holes and the concave / convex portions before separating each chip-shaped substrate body 2, but after separating each chip-shaped substrate body 2,
Each chip-shaped substrate 2 may be provided with a through hole or a concave / convex portion.

【0044】[0044]

【発明の効果】この発明によれば、チップ状基板体の行
又は列群の状態で、つまり、各チップ状基板体毎に分離
される前の状態で、チップ状基板体に側面導体パターン
を形成する構成であり、チップ状基板体の行又は列群は
チップ状基板体よりも大きいことから、非常に微細な各
チップ状基板体の側面に側面導体パターンを形成する場
合に比べて、チップ状基板体の行又は列群における各チ
ップ状基板体の側面形成領域に容易に、しかも、位置精
度良く側面導体パターンを形成することができる。
According to the present invention, the side conductor pattern is formed on the chip-shaped substrate in a state of rows or columns of the chip-shaped substrate, that is, before being separated for each chip-shaped substrate. Since the row or column group of the chip-shaped substrate body is larger than the chip-shaped substrate body, the chip-shaped substrate is formed as compared with the case where the side conductor pattern is formed on the side surface of each very fine chip-shaped substrate body. Side conductor patterns can be formed easily and with high positional accuracy on the side surface forming regions of each chip-shaped substrate in the rows or columns of the substrate.

【0045】このように、各チップ状基板体に側面導体
パターンを位置精度良く形成することができるので、側
面導体パターンの位置ずれに起因したチップ状電子部品
の歩留まり低下の問題を防止することができる。
As described above, since the side conductor pattern can be formed on each chip-shaped substrate body with high positional accuracy, it is possible to prevent a problem of a decrease in the yield of chip-shaped electronic components due to a displacement of the side conductor pattern. it can.

【0046】その上、各チップ状基板体毎に分離される
前の状態で、チップ状基板体に側面導体パターンが形成
されるので、複数のチップ状基板体に一括的に側面導体
パターンを形成することができることとなり、従来のよ
うに、個々のチップ状基板体毎に、側面導体パターンを
形成する場合に比べて、チップ状電子部品の生産性を格
段に向上させることができる。
In addition, since the side conductor pattern is formed on the chip substrate before being separated for each chip substrate, the side conductor pattern is collectively formed on a plurality of chip substrates. Thus, the productivity of the chip-shaped electronic component can be remarkably improved as compared with the conventional case where the side conductor pattern is formed for each chip-shaped substrate.

【0047】上記のように、チップ状電子部品の歩留ま
り低下防止の効果と、生産性向上効果とが相俟って、チ
ップ状電子部品の価格を抑制することが容易となり、安
価なチップ状電子部品を提供することが可能となる。
As described above, the effect of preventing the yield of chip-shaped electronic components from lowering and the effect of improving the productivity are combined, so that the cost of chip-shaped electronic components can be easily suppressed, and the cost of chip-shaped electronic components can be reduced. Parts can be provided.

【0048】また、前記のように、チップ状基板体の側
面に側面導体パターンを位置精度良く形成することがで
きるので、チップ状基板体を大型化することなく、複雑
な側面導体パターンを形成することが可能となり、これ
からますます要求される側面導体パターンの複雑化(回
路網の高密度化)に十分対応することができるチップ状
電子部品を、簡単、かつ、安価に製造することができ
る。
Further, as described above, since the side conductor pattern can be formed on the side surface of the chip-shaped substrate body with high positional accuracy, a complicated side conductor pattern can be formed without increasing the size of the chip-shaped substrate body. This makes it possible to easily and inexpensively manufacture a chip-shaped electronic component that can sufficiently cope with the increasingly required complexity of side conductor patterns (higher density of a circuit network).

【0049】さらに、母材基板体を複数積層する際に母
材基板体を接合材料を用いて一体化する構成とし、チッ
プ状基板体の積層体を各チップ状基板体毎に分離する際
には、上記接合材料の接合力を低下させてチップ状基板
体の積層体を各チップ状基板体毎に分離する構成のもの
にあっては、母材基板体の積層体をチップ状基板体の行
又は列群毎に切り分ける場合に、母材基板体の積層体が
崩れてしまうという問題を確実に防止することができ
る。また、チップ状基板体の積層体を各チップ状基板体
毎に容易に分離することができる。
Further, when a plurality of base material substrates are laminated, the base material substrates are integrated by using a bonding material, and when the stacked body of chip-shaped substrates is separated for each chip-shaped substrate, In a configuration in which the bonding strength of the bonding material is reduced to separate the stack of chip-shaped substrate bodies for each chip-shaped substrate body, the stacked body of the base material substrate body is In the case of separating each row or column group, the problem that the stacked body of the base material substrate collapses can be reliably prevented. Further, the stacked body of the chip-shaped substrate bodies can be easily separated for each chip-shaped substrate body.

【0050】チップ状電子部品がチップ状アンテナ素子
であるものにあっては、チップ状アンテナ素子は側面導
体パターンを位置精度良く形成することが要求される
が、その要求に十分に応えられるチップ状アンテナ素子
を得ることができる。
In the case where the chip-shaped electronic component is a chip-shaped antenna element, the chip-shaped antenna element is required to form the side conductor pattern with high positional accuracy, but the chip-shaped antenna element can sufficiently meet the demand. An antenna element can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係るチップ状電子部品の製造方法の一
実施形態例を示す説明図である。
FIG. 1 is an explanatory view showing one embodiment of a method for manufacturing a chip-shaped electronic component according to the present invention.

【図2】その他の実施形態例を示す説明図である。FIG. 2 is an explanatory diagram showing another embodiment.

【図3】チップ状アンテナ素子の一例を示すモデル図で
ある。
FIG. 3 is a model diagram showing an example of a chip antenna element.

【図4】従来の課題を示す説明図である。FIG. 4 is an explanatory diagram showing a conventional problem.

【符号の説明】 1 チップ状アンテナ素子 2 チップ状基板体 6 母材基板体 10 チップ状基板体の行群 11 チップ状基板体の列群 12 チップ状基板体の側面形成領域 13 チップ状基板体の積層体DESCRIPTION OF SYMBOLS 1 Chip-shaped antenna element 2 Chip-shaped substrate 6 Base material substrate 10 Row group of chip-shaped substrate 11 Column group of chip-shaped substrate 12 Side surface forming area of chip-shaped substrate 13 Chip-shaped substrate Laminate

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 チップ状基板体の側面には導電材料が予
め定められたパターンでもって形成されて側面導体パタ
ーンが構成されているチップ状電子部品の製造方法であ
って、複数の上記チップ状基板体を形成するための母材
基板体を用意し、まず、上記複数の母材基板体を積層
し、次に、上記母材基板体の積層体を予め定めたチップ
状基板体の行列配置の行又は列群毎に切り分け、その
後、上記チップ状基板体の行又は列群における各チップ
状基板体の側面形成領域にそれぞれ上記側面導体パター
ンを形成し、然る後に、上記チップ状基板体の行又は列
群をチップ状基板体の列又は行毎に切り分けてチップ状
基板体の積層体と成し、次に、そのチップ状基板体の積
層体を各チップ状基板体毎に分離することを特徴とする
チップ状電子部品の製造方法。
1. A method for manufacturing a chip-shaped electronic component in which a conductive material is formed on a side surface of a chip-shaped substrate body in a predetermined pattern to form a side-surface conductive pattern. A base material body for forming a substrate body is prepared, first, the plurality of base material substrate bodies are stacked, and then, the stacked body of the base material body is arranged in a predetermined matrix of chip-shaped substrate bodies. Then, the side surface conductor patterns are formed in the side surface forming regions of the respective chip-shaped substrate bodies in the row or column group of the chip-shaped substrate body, and thereafter, the chip-shaped substrate body is formed. Are divided into columns or rows of the chip-shaped substrate to form a stacked body of the chip-shaped substrate, and then the stacked body of the chip-shaped substrate is separated for each chip-shaped substrate. Manufacture of chip-shaped electronic components characterized by the following: Method.
【請求項2】 母材基板体を複数積層する際には、それ
ら複数の母材基板体を接合材料を用いて一体化する構成
とし、チップ状基板体の積層体を各チップ状基板体毎に
分離する際に、上記接合材料の接合力を低下させてチッ
プ状基板体の積層体を各チップ状基板体毎に分離するこ
とを特徴とする請求項1記載のチップ状電子部品の製造
方法。
2. When laminating a plurality of base material substrates, the plurality of base material substrates are integrated by using a bonding material, and the stacked body of chip-shaped substrates is separated for each chip-shaped substrate. 2. The method for manufacturing a chip-like electronic component according to claim 1, wherein, when separating the chip-like electronic parts, the bonding strength of the bonding material is reduced to separate the stack of chip-like substrate bodies into individual chip-like substrate bodies. .
【請求項3】 チップ状電子部品はチップ状アンテナ素
子であることを特徴とする請求項1又は請求項2記載の
チップ状電子部品の製造方法。
3. The method for manufacturing a chip-shaped electronic component according to claim 1, wherein the chip-shaped electronic component is a chip-shaped antenna element.
JP16796799A 1999-06-15 1999-06-15 Manufacturing method of chip-shaped electronic component Expired - Fee Related JP3632504B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16796799A JP3632504B2 (en) 1999-06-15 1999-06-15 Manufacturing method of chip-shaped electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16796799A JP3632504B2 (en) 1999-06-15 1999-06-15 Manufacturing method of chip-shaped electronic component

Publications (2)

Publication Number Publication Date
JP2000357909A true JP2000357909A (en) 2000-12-26
JP3632504B2 JP3632504B2 (en) 2005-03-23

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP16796799A Expired - Fee Related JP3632504B2 (en) 1999-06-15 1999-06-15 Manufacturing method of chip-shaped electronic component

Country Status (1)

Country Link
JP (1) JP3632504B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109428169A (en) * 2017-08-29 2019-03-05 三星电机株式会社 The manufacturing method of piece type antenna and the piece type antenna

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109428169A (en) * 2017-08-29 2019-03-05 三星电机株式会社 The manufacturing method of piece type antenna and the piece type antenna
CN109428169B (en) * 2017-08-29 2020-11-06 三星电机株式会社 Chip antenna and method for manufacturing the same
US11165156B2 (en) 2017-08-29 2021-11-02 Samsung Electro-Mechanics Co., Ltd. Chip antenna and manufacturing method thereof

Also Published As

Publication number Publication date
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