JP2000353801A - Semiconductor device with solid-state image sensing element and its manufacture - Google Patents

Semiconductor device with solid-state image sensing element and its manufacture

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Publication number
JP2000353801A
JP2000353801A JP11166843A JP16684399A JP2000353801A JP 2000353801 A JP2000353801 A JP 2000353801A JP 11166843 A JP11166843 A JP 11166843A JP 16684399 A JP16684399 A JP 16684399A JP 2000353801 A JP2000353801 A JP 2000353801A
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Japan
Prior art keywords
semiconductor substrate
insulating layer
region
isolation insulating
formed
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Application number
JP11166843A
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Japanese (ja)
Inventor
Keiichi Higashiya
Atsushi Maeda
敦 前田
恵市 東谷
Original Assignee
Mitsubishi Electric Corp
三菱電機株式会社
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Priority to JP11166843A priority Critical patent/JP2000353801A/en
Publication of JP2000353801A publication Critical patent/JP2000353801A/en
Withdrawn legal-status Critical Current

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Abstract

(57) Abstract: A semiconductor device having a solid-state image sensor capable of suppressing generation of dark current in a transfer switch section, and a method of manufacturing the same are provided. SOLUTION: An impurity concentration higher than an impurity concentration of the semiconductor substrate 2 is provided on a surface of the semiconductor substrate 2 below a gate electrode layer 8a of the transfer switch M1 and adjacent to an end E of the element isolation insulating layer 3. P + impurity region 1a is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a solid-state image sensor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a solid-state imaging device using an amplification type sensor has been proposed as one of the solid-state imaging devices. This element has a characteristic that an optical signal detected by the photoelectric conversion storage unit is amplified very near the photoelectric conversion storage unit.

FIG. 37 shows a CMOS image sensor as a solid-state image sensor.
FIG. 2 is a diagram illustrating a circuit configuration of a (Complementary Metal Oxide Semiconductor) type image sensor. Referring to FIG. 37, unit pixels or unit cells C are arranged in a matrix, and each cell C is connected to a vertical shift register and a horizontal shift register.

Each unit cell C includes a photodiode PD
, A transfer switch M1, a reset switch M2, an amplifier M3, and a selection switch M4. The photodiode PD plays a role of converting incident light into an electric signal. The transfer switch M1 has a role of transferring the converted electric signal to the amplifier M3, and its control is performed by a signal from the vertical shift register. The reset switch M2 plays a role of resetting signal charges, and the amplifier M3 plays a role of amplifying an electric signal.

Each of the transfer switch M1, the reset switch M2, the amplifier M3, and the selection switch M4 is
It consists of MOS transistors.

FIG. 38 is a plan view showing a specific conventional structure of a region R in FIG. FIGS. 39 and 40 are schematic sectional views taken along lines 201-201 and 202-202 of FIG.

Referring to FIGS. 38 to 40, the surface of p-type semiconductor substrate 102 has a LOCOS (Local Oxidation of
Element isolation insulating layer 103 formed by a silicon (Si) method.
And ap + impurity region 101 in contact with the lower surface and having an impurity concentration higher than that of p-type semiconductor substrate 102 is formed.

Referring mainly to FIG. 38, element isolation insulating layer 1
The photodiode PD, the transfer switch M1, and the reset switch M2 are arranged side by side on the surface of the semiconductor substrate 102 electrically separated from the semiconductor substrate 103 by the p + impurity region 101.

Referring mainly to FIGS. 38 and 40, photodiode PD is formed of a pn junction between a p-type region and an n-type impurity region 104 of semiconductor substrate 102.
Above the n-type impurity region 104, the p-type impurity region 1 is formed.
05 is formed. This p-type impurity region 105
The depletion layer at the pn junction between the p-type region and the n-type impurity region 104 of the semiconductor substrate 102 has a concentration such that it does not reach the surface of the semiconductor substrate 102. Since the p-type impurity region 105 prevents defects and the like existing near the surface of the semiconductor substrate 102 from being taken into the depletion layer,
Leakage current (hereinafter referred to as dark current) due to this can be suppressed.

The transfer switch M1 is connected to the n-type source region 10
4 and an n-type drain (FD) region 106a and a gate electrode layer 108a. n-type source region 104 and n
Formed on the surface of semiconductor substrate 102 at a predetermined distance from mold drain region 106a. The gate electrode layer 108a is formed on a region between the n-type source region 104 and the n-type drain region 106a with the gate insulating layer 107 interposed therebetween. Note that the n-type impurity region 104 of the photodiode PD and the n-type source region 104 of the transfer switch M1 are formed of the same impurity region.

Referring mainly to FIG. 38, reset switch M2 includes a pair of n-type source / drain regions 106a,
And a gate electrode layer 108b. A pair of n-type source / drain regions 106a are formed on the surface of semiconductor substrate 102 at a predetermined distance from each other. The gate electrode layer 108b includes a pair of source / drain regions 1
The gate insulating layer is formed on a region interposed between the gate insulating layers 06a. Note that the n-type drain region 106a of the transfer switch M1 and the n-type source / drain region 106a of the reset switch M2 are formed of the same region.

Referring to FIGS. 38 to 40, an interlayer insulating film 109 is formed so as to cover the entire surface, and desired openings 109a and 109b are formed in interlayer insulating film 109. A wiring layer 110 and the like are formed so as to be electrically connected to each of the gate electrode layers 108a and 108b through the openings 109a and 109b.

[0013]

In the above-described conventional image sensor, there is a problem that a dark current is generated due to a crystal defect or the like due to a stress at the time of forming the isolation insulating layer 103, and the characteristics of the sensor are deteriorated. Hereinafter, this will be described in detail.

The isolation insulating layer 103 is formed by the LOCOS method.
When the substrate 102 is formed by oxidation, the semiconductor substrate 10
2 is stressed during oxidation. Therefore, many crystal defects occur in the semiconductor substrate 102 near the isolation insulating layer 103.

In this state, as shown in FIG. 41, the source region 104 or the drain region 106a and the semiconductor substrate 10
A depletion layer 150 is generated from the pn junction with the second p-type region. When the depletion layer 150 extends below the gate electrode layer 108a to the region S at the end of the isolation insulating layer 103, crystal defects in the region S are taken into the depletion layer 150. As a result, a large number of electron-hole pairs are generated in the crystal defect portion, and the electrons flow into the transfer switch M1, resulting in a leak current (dark current).

When the charge generated in the photodiode PD is Q P and the capacitance in the FD is C FD , the output voltage V
out is Vout = Q P / C FD .

If the dark current component Q 1 exists, an error ΔVout = Q 1 / C FD corresponding thereto occurs. As a result, Vout (noise) when there is no light irradiation increases by an amount corresponding to △ Vout, so that the sensitivity as a solid-state image sensor,
That is, the S / N ratio decreases.

An object of the present invention is to provide a semiconductor device having a solid-state image sensor capable of preventing generation of dark current in a transfer transistor portion, and a method of manufacturing the same.

[0019]

According to the present invention, there is provided a semiconductor device having a solid-state imaging device, comprising: a photoelectric conversion element for converting light into an electric signal; an amplifying means for amplifying the electric signal;
A semiconductor device having a solid-state imaging device including a transfer insulated gate field effect transistor as a switch that transfers an electric signal converted by a photoelectric conversion element to an amplification unit, a semiconductor substrate, an isolation insulating layer, It has a gate electrode layer of an insulated gate field effect transistor for transfer and a high concentration impurity region. The semiconductor substrate is of the first conductivity type and has a main surface. The isolation insulating layer is formed on the main surface of the semiconductor substrate for electrically isolating the transfer insulated gate field effect transistor from other elements. The gate electrode layer of the transfer insulated gate field effect transistor is formed to extend on the main surface of the semiconductor substrate sandwiched between the opposing one side and the other side of the isolation insulating layer. . The high-concentration impurity region is of the first conductivity type and is formed on the main surface of the semiconductor substrate so as to extend from the end of the isolation insulating layer toward the formation region of the transfer insulated gate field effect transistor and to be located immediately below the gate electrode layer. And has an impurity concentration higher than that of the first conductivity type region of the semiconductor substrate.

In the semiconductor device having the solid-state image pickup device according to the present invention, the high-concentration impurity region is formed near the lower side of the gate electrode layer and adjacent to the end of the isolation insulating layer. Therefore, the extension of the depletion layer toward the end of the isolation insulating layer is suppressed by the high-concentration impurity region. Therefore, it becomes difficult for crystal defects and the like near the isolation insulating layer to be taken into the depletion layer, and it is possible to suppress the occurrence of dark current in the transfer insulated gate field effect transistor portion, thereby improving the characteristics of the image sensor. be able to.

In the above semiconductor device, preferably, the photoelectric conversion element has a photodiode, and the high-concentration impurity region is adjacent to the end of the isolation insulating layer so as to surround the periphery of the photodiode in the photodiode formation region. It is formed on the main surface of the semiconductor substrate.

Thus, it is possible to suppress the occurrence of dark current due to a crystal defect at the end of the isolation insulating layer in the photodiode formation region.

In the above-described semiconductor device, preferably, the high-concentration impurity region is formed to extend below the isolation insulating layer so as to be in contact with the lower surface of the isolation insulating layer.

The high-concentration impurity region achieves electrical isolation between the transfer insulated gate field effect transistor and other elements.

In the above-described semiconductor device, preferably, the gate electrode layer is formed so as to ride on both ends of one side and the other side of the isolation insulating layer.

Thus, element isolation of the transfer insulated gate field effect transistor can be performed by the isolation insulating layer.

Preferably, in the above semiconductor device, the gate electrode layer is formed so as to have a space between at least one end on one side and the other side of the isolation insulating layer.

Thus, the device isolation of the transfer insulated gate field effect transistor can be performed by the pn junction isolation.

In the above semiconductor device, preferably, the element isolation of the transfer insulated gate field effect transistor is p
It has a configuration performed by n-junction separation.

Thus, the device isolation of the transfer insulated gate field effect transistor can be performed by the pn junction isolation.

In the above semiconductor device, preferably, the transfer insulated gate field effect transistor is a second conductivity type source region formed on the main surface of the semiconductor substrate so as to sandwich a region located below the gate electrode layer. And a drain region. The photodiode has a first conductivity type region of the semiconductor substrate and a second conductivity type impurity region forming a pn junction. The source region and the second conductivity type impurity region are formed of the same region.

This makes it possible to arrange the photodiode and the transfer insulated gate field effect transistor side by side within a small plane occupation area.

A method of manufacturing a semiconductor device having a solid-state imaging device according to one aspect of the present invention includes a photoelectric conversion element for converting light into an electric signal, an amplifying means for amplifying the electric signal, and a photoelectric conversion element. A method for manufacturing a semiconductor device having a solid-state imaging device including a transfer insulated gate field effect transistor as a switch for transferring the electric signal converted in step (a) to the amplifying means, comprising the following steps.

First, a mask layer is formed on the main surface of the semiconductor substrate of the first conductivity type, and ions of the first conductivity type are obliquely implanted into the main surface of the semiconductor substrate using the mask layer as a mask. Then, heat treatment is performed while the mask layer is left, so that an isolation insulating layer is formed in a region exposed from the mask layer. The first conductivity type high concentration impurity region extending on the main surface of the semiconductor substrate toward the field effect transistor formation region side is formed to have an impurity concentration higher than the impurity concentration of the first conductivity type region of the semiconductor substrate. Then, the gate electrode layer of the transfer insulated gate field effect transistor is formed so as to extend on the main surface of the semiconductor substrate sandwiched between the opposing one side and the other side of the isolation insulating layer.

In the manufacturing method according to one aspect of the present invention, high-concentration impurity regions adjacent to the end of the isolation insulating layer can be formed by injecting ions obliquely into the main surface of the semiconductor substrate. . Therefore, the extension of the depletion layer toward the end of the isolation insulating layer is suppressed by the high concentration impurity region. Therefore, a crystal defect or the like at an end of the isolation insulating layer is less likely to be taken into the depletion layer, so that generation of dark current can be suppressed, and characteristics of the image sensor can be improved.

Preferably, in the manufacturing method according to one aspect of the present invention, ions are implanted at an angle of 30 ° or more and 60 ° or less with respect to a perpendicular to the main surface of the semiconductor substrate.

As a result, a high-concentration impurity region can be appropriately formed. A method for manufacturing a semiconductor device having a solid-state imaging device according to another aspect of the present invention includes a photoelectric conversion element for converting light into an electric signal, an amplification unit for amplifying the electric signal, and a photoelectric conversion element. A method for manufacturing a semiconductor device having a solid-state imaging device including a transfer insulated gate field effect transistor as a switch for transferring the electrical signal to the amplifying means, comprising the following steps.

First, an isolation insulating layer is selectively formed on the main surface of a semiconductor substrate. Then, ions of the first conductivity type are implanted using the mask layer which opens the main surface of the semiconductor substrate adjacent to the edge of the isolation insulating layer as a mask, so that the transfer insulating gate type field effect is applied from the edge of the isolation insulating layer. A first conductivity type high concentration impurity region extending on the main surface of the semiconductor substrate to the transistor formation region side is formed to have an impurity concentration higher than the impurity concentration of the first conductivity type region of the semiconductor substrate. An insulating gate type electric field effect for transfer extending on the main surface of the semiconductor substrate sandwiched between one side and the other side of the isolation insulating layer and directly above the high concentration impurity region. A gate electrode layer of the transistor is formed.

In the manufacturing method according to another aspect of the present invention, a high-concentration impurity region adjacent to the end of the isolation insulating layer can be formed by implanting ions using a mask. Therefore, the extension of the depletion layer toward the end of the isolation insulating layer is suppressed by the high concentration impurity region. Therefore, a crystal defect or the like at an end of the isolation insulating layer is less likely to be taken into the depletion layer, so that generation of dark current can be suppressed, and characteristics of the image sensor can be improved.

[0040]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a plan view schematically showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. FIG. 2 and FIG.
FIG. 2 is a schematic sectional view taken along lines 201-201 and 202-202 of FIG. 1.

Referring to FIGS. 1 to 3, p-type semiconductor substrate 2
The element isolation insulating layer 3 formed by the LOCOS method is formed on the surface of the device. Ap + impurity region 1a having an impurity concentration higher than that of semiconductor substrate 2 is formed in contact with the lower surface of element isolation insulating layer 3. The p impurity region 1a is formed in a region below the gate electrode layers 8a and 8b,
In the D region and the FD region, it is formed to extend from the end E of the element isolation insulating layer 3 to the transfer switch M1 forming region side on the surface of the semiconductor substrate 2. Therefore, the end portion Ep of the p + impurity region 1a and the element isolation insulating layer 3
Are separated from each other by a distance D.

Referring mainly to FIG. 1, a photodiode PD, a transfer switch M1, and a reset switch M2 are provided on a surface of a semiconductor substrate 2 electrically separated by an element isolation insulating layer 3 and ap + impurity region 1a. Are arranged side by side.

Referring mainly to FIGS. 1 and 3, the photodiode PD is formed by a pn junction between a p-type region and an n-type impurity region 4 of the semiconductor substrate 2. Above the n-type impurity region 4, a p-type impurity region 5 is formed. The p-type impurity region 5 has such a concentration that a depletion layer of a pn junction between the p-type region and the n-type impurity region 4 of the semiconductor substrate 2 does not reach the surface of the semiconductor substrate 2. Since the p-type impurity region 105 prevents defects or the like existing near the surface of the semiconductor substrate 2 from being taken into the depletion layer, it is possible to suppress dark current caused by the defects.

The transfer switch M1 has an n-type source region 4, an n-type drain (FD) region 6a, and a gate electrode layer 8a. N-type source region 4 and N-type drain region 6
a is formed on the surface of the semiconductor substrate 2 at a predetermined distance. The gate electrode layer 8a is formed on a region sandwiched between the n-type source region 4 and the n-type drain region 6a via the gate insulating layer 7. Note that the n-type impurity region 4 of the photodiode PD and the n-type source region 4 of the transfer switch M1 are formed of the same impurity region.

Referring mainly to FIG. 1, reset switch M
2 has a pair of n-type source / drain regions 6a and a gate electrode layer 8b. A pair of n-type source / drain regions 6a are formed on the surface of semiconductor substrate 2 at a predetermined distance from each other. Gate electrode layer 8b is formed on a region interposed between a pair of n-type source / drain regions 6a via a gate insulating layer (not shown). Note that the n-type drain region 6a of the transfer switch M1 and one of the pair of source / drain regions 6a of the reset switch M2 are formed of the same impurity region.

Referring to FIGS. 1 to 3, interlayer insulating film 9 is formed to cover the entire surface.
Are formed with desired openings 9a and 9b. The wiring layer 10 and the like are formed so as to be electrically connected to the gate electrode layers 8a and 8b through the openings 9a and 9b. Here, for convenience of explanation, illustration of a wiring layer connected to the gate electrode layer 8b is omitted.

Next, the impurity concentration distribution in this embodiment will be described. FIGS. 4 and 5 correspond to FIG.
FIG. 11 is a diagram showing impurity concentration distribution in the semiconductor substrate at a portion along line 211 and line 212-212.

[0049] Figure 2, with reference to FIGS. 4 and 5, the semiconductor substrate 2 has an impurity concentration of about 1 × 10 15 ~1 × 10 17 cm -3, p + impurity region 1a is 1 × 10 16 -1
It has an impurity concentration of about × 10 18 cm −3 . Also p
+ Distance D from end Ep of impurity region 1a to end E of element isolation insulating layer 3 is, for example, 0.2 to 0.3 μm. Here, the end Ep of the p + impurity region 1a is a portion where the impurity concentration of the p + impurity region 1a is substantially equal to the impurity concentration of the semiconductor substrate 2, as shown in FIG.

Next, the manufacturing method of the present embodiment will be described. 6 to 9 are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps. Referring to FIG. 6, an underlying oxide film 11 and a silicon nitride film 12 are sequentially laminated on the surface of semiconductor substrate 2.

Referring to FIG. 7, a photoresist pattern 13 is formed on silicon nitride film 12 by using a usual photolithography technique. By etching the silicon nitride film 12 using the resist pattern 13 as a mask,
The silicon nitride film 12 is patterned.

Referring to FIG. 8, with the resist pattern 13 left, a p-type impurity (ion) such as boron (B) is obliquely implanted. Angle of this ion implantation θ
Is 30 ° or more with respect to a perpendicular to the surface of the semiconductor substrate 2.
° or less. By oblique implantation, boron is implanted into the lower region of the silicon nitride film 12. Thereafter, the resist pattern 13 is removed and a thermal oxidation process is performed. Then, silicon nitride film 12 and underlying oxide film 11 are removed.

Referring to FIG. 9, an element isolation insulating layer 3 made of a silicon oxide film and ap + impurity region 1a are formed on the surface of semiconductor substrate 2 by the above-described thermal oxidation process. The p + impurity region 1a is formed so as to be in contact with the lower surface of the element isolation insulating layer 3 and to have an end Ep separated from the end E of the element isolation insulating layer 3 by a distance D.

Thereafter, the gate insulating layer 7, the gate electrode layer 8
a, 8b, n-type source region 4, n-type drain region 6a,
The p-type impurity region 5, the interlayer insulating film 9, the wiring layer 10, and the like are formed, and the semiconductor device of the present embodiment shown in FIGS. 1 to 3 is completed.

In the present embodiment, the p + impurity region 1a is formed below the gate electrode layer 8a by the end E of the element isolation insulating layer 3.
Extending to the formation area side of the transfer switch M1 from
It is possible to suppress generation of dark current due to stress at the time of forming the element isolation insulating layer 3. Hereinafter, this will be described.

FIG. 10 is a circuit diagram of the transfer switch M1 shown in FIG.
It is a top view which expands and shows a G part. Referring to FIG.
As described above, under the gate electrode layer 8a, p+Unfortunate
A pure region 1a is formed. Therefore, the gate electrode
In the lower region of the layer 8a, the source region of the transfer switch M1
Region 4 or end of drain region 6a and element isolation insulating layer
A distance D can be ensured between the end portion 3 and the end E. Ma
P+The impurity region 1a has a higher impurity concentration than the semiconductor substrate 2.
Is more depleted in the semiconductor substrate 2 than in the semiconductor substrate 2
The layer is difficult to extend. Therefore, the source region 4 or the drain
Region 6a and p +Extending from the pn junction with impurity region 1a
The depletion layer 50 is p+Element isolation by impurity region 1a
Reaching the end E of the insulating layer 3 is suppressed. Accordingly
To separate the elements due to stress at the time of forming the element isolation insulating layer 3.
Crystal defects and the like generated near the end of the insulating layer 3 cause this depletion.
Entrapment in the layer 50 is suppressed. Dark as a result
Current generation can be suppressed, improving sensor characteristics
It is possible to do.

Since p + impurity region 1a is also formed around PD region and FD region, generation of dark current due to stress at the time of forming element isolation insulating layer 3 is also suppressed in these regions. You can also.

Second Embodiment FIG. 11 is a plan view schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention. 12 and 13 are schematic cross-sectional views taken along lines 201-201 and 202-202 of FIG.

Referring to FIGS. 11 to 13, the present embodiment differs from the structure of the first embodiment in that a new p + impurity region 1c is provided and the shape of p + impurity region 1b is changed. What changed is different.

Referring mainly to FIGS. 11 and 12, p + impurity region 1c has an impurity concentration higher than that of semiconductor substrate 2 and is located below gate electrode layer 8a. It is formed. The p + impurity region 1c is formed so as to extend from the end E of the element isolation insulating layer 3 to the formation region side of the transfer switch M1 on the surface of the semiconductor substrate 2. For this reason, from the end E of the element isolation insulating layer 3, p +
The distance D to the end Ep of the impurity region 1c is, for example, 0.
2 to 0.3 μm.

Referring mainly to FIGS. 12 and 13, p + impurity region 1b has an impurity concentration higher than that of semiconductor substrate 2 and is formed so as to be in contact with the lower surface of element isolation insulating layer 3. Have been.

The remaining structure is almost the same as that of the first embodiment described above, and therefore, the same members are denoted by the same reference characters and description thereof will not be repeated.

Next, the impurity concentration distribution in this embodiment will be described. FIG. 14 and FIG.
It is a figure which shows the impurity concentration distribution in the semiconductor substrate of the part which follows the 11-211 line and the 212-212 line.

Referring to FIG. 12, FIG. 14 and FIG.
The semiconductor substrate 2 has an impurity concentration of about 1 × 10 15 to 1 × 10 17 cm −3 , and the p + impurity
It has an impurity concentration of about 17 to 1 × 10 19 cm −3 .

Note that p + impurity region 1 defining distance D
The end Ep of c is a portion where the impurity concentration of the p + impurity region 1c becomes substantially equal to the impurity concentration of the semiconductor substrate 2 as shown in FIG.

Next, the manufacturing method of the present embodiment will be described. 16 to 19 are schematic sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps. The manufacturing method of the present embodiment first performs the same steps as those of the first embodiment shown in FIGS. Thereafter, referring to FIG. 16, silicon nitride film 12 and resist pattern 13 are formed.
Is used as a mask, and a p-type impurity such as B
Is substantially perpendicular to the surface of the substrate. After this,
The resist pattern 13 is removed, and a thermal oxidation process is performed. Then, the silicon nitride film 12 and the underlying oxide film 1
1 is removed.

Referring to FIG. 17, an element isolation insulating layer 3 made of a silicon oxide film and ap + impurity region 1c are formed on the surface of semiconductor substrate 2 by the above-described thermal oxidation process.

Referring to FIG. 18, the resist pattern 14a is formed on the surface of the semiconductor substrate 2 by a normal photolithography technique.
Is formed. This resist pattern 14a is formed as shown in FIG.
As shown in FIG. 7, the transfer switch M1 is formed so as to open near the end E of the element isolation insulating layer 3 near the region where the gate electrode layer is formed. In addition, FIG.
Corresponds to the cross section along line 01.

Using this resist pattern 14a as a mask
For example, boron (B) or boron fluoride (BF)Two)
Such as 1 × 1013~ 1 × 1015
cm -2Ions are implanted with a moderate doping amount. This
The semiconductor substrate 2 adjacent to the end E of the element isolation insulating layer 3.
P on the surface of+Impurity region 1c is formed.

Referring to FIG. 19, thereafter, gate insulating layer 7 and gate electrode layer 8a are formed.

Further, n-type source region 4, n-type drain region 6a, p-type impurity region 5, interlayer insulating film 9, wiring layer 1
0 and the like are formed to complete the semiconductor device of the present embodiment shown in FIGS.

In this embodiment, the gate electrode layer 8
Under a, ap + impurity region 1c extends from the end E of the element isolation insulating layer 3 toward the formation region of the transfer switch M1 on the surface of the semiconductor substrate 2. Therefore, the first embodiment
Similarly to the case described above, the extension of the depletion layer toward the end E of the element isolation insulating layer 3 can be suppressed, whereby the occurrence of dark current can be suppressed.

In the present embodiment, p+Impurity region 1
c can be formed using the resist pattern 14a as a mask.
Therefore, it is necessary to change the shape of the resist pattern 14a.
And p +It is possible to arbitrarily set the shape of the impurity region 1c.
it can.

Third Embodiment FIG. 21 is a plan view schematically showing a configuration of a semiconductor device according to a third embodiment of the present invention. FIG. 22 is a schematic sectional view taken along the line 202-202 in FIG.

Referring to FIGS. 21 and 22, the structure of the present embodiment is different from the structure of the second embodiment in that the p + impurity region 1c has an element isolation insulating layer even in the PD region and the FD region. 3 in that it is formed on the surface of the semiconductor substrate 2 adjacent to the end E of the third substrate 3. Also, 201-201 of FIG.
The cross-sectional structure along the line is almost the same as the structure shown in FIG. 12 of the second embodiment, and the same is true of the impurity concentration distribution.

The remaining structure is almost the same as that of the second embodiment, and therefore, the same members are denoted by the same reference characters and description thereof will not be repeated.

Next, the manufacturing method of the present embodiment will be described. 23 and 24 are a schematic cross-sectional view and a plan view illustrating a method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 23A corresponds to a schematic sectional view taken along the line 201-201 in FIG. 24, and FIG.
It corresponds to a schematic sectional view along line 2-202.

The manufacturing method of this embodiment is the same as that of Embodiment 2
In the method of forming p + impurity region 1c, as compared with the method of the first embodiment.

In this embodiment, when forming p + impurity region 1c, first, a resist pattern 14b as shown in FIGS. 23 and 24 is formed. The resist pattern 14b is formed not only in the formation region of the gate electrode layer of the transfer switch M1, but also in the PD region and the FD region.
The element isolation insulating layer 3 is formed so as to open near the end E. Then, p + impurity region 1c is formed by ion-implanting a p-type impurity such as B or BF 2 using the resist pattern 14b as a mask.

The other manufacturing steps are almost the same as those in the second embodiment, and the description is omitted.

In the present embodiment, the p + impurity region 1c is formed below the gate electrode layer 8a of the transfer switch M1, so that generation of dark current can be suppressed as in the first and second embodiments. it can.

The p + impurity region 1c is also distributed on the surface of the semiconductor substrate 2 adjacent to the end E of the element isolation insulating layer 3 in the PD region and the FD region. There is also an effect of suppressing generation of current.

Fourth Embodiment FIG. 25 is a plan view schematically showing a configuration of a semiconductor device according to a fourth embodiment of the present invention. FIG. 26 is a sectional view of FIG.
It is a schematic sectional drawing which follows the 01-201 line.

Referring to FIGS. 25 and 26, the present embodiment differs from the configuration of the second embodiment in the shape of gate electrode layer 8a of transfer switch M1. One end of the gate electrode layer 8a in the longitudinal direction does not run over the end E of the element isolation insulating layer 3, and the end face is located immediately above the p + impurity region 1c. That is, the end face on one end side of the gate electrode layer 8 a is formed so as to have a space between the end face E of the element isolation insulating layer 3. With this configuration, the transfer switch M1 can be separated by a pn junction instead of being separated by the element isolation insulating layer 3. The cross section along the line 202-202 in FIG. 25 corresponds to the cross-sectional structure shown in FIG.

The remaining structure is substantially the same as the structure of the second embodiment described above. Therefore, the same members are denoted by the same reference characters and description thereof will not be repeated.

Next, the manufacturing method of the present embodiment will be described. FIG. 27 is a schematic sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention. The manufacturing method of the present embodiment differs from the manufacturing method of the second embodiment in the method of forming the gate electrode layer 8a of the transfer switch M1.

In the present embodiment, the gate electrode layer 8a
As shown in FIG. 27, it is formed by patterning such that one end does not run on element isolation insulating layer 3 and the end face of one end is located directly above p + impurity region 1c.

The other manufacturing steps are almost the same as those in the second embodiment, and therefore, the description thereof is omitted.

In the present embodiment, the p + impurity region 1c is formed below the gate electrode layer 8a of the transfer switch M1, so that the occurrence of dark current can be suppressed as in the first to third embodiments. it can.

Further, since the end face of the gate electrode layer 8a is spaced from the end E of the element isolation insulating layer 3, the element can be separated by a pn junction in this part.

Fifth Embodiment FIG. 28 is a plan view schematically showing a configuration of a semiconductor device according to a fifth embodiment of the present invention. Referring to FIG.
In the present embodiment, compared to the configuration of the fourth embodiment, p
+ The difference is that impurity region 1c is formed on the surface of semiconductor substrate 2 adjacent to end E of element isolation insulating layer 3 also in the PD region and the FD region. In addition, 201- in FIG.
The cross-sectional structure along the line 201 is almost the same as the configuration shown in FIG. 12, and the cross-sectional structure along the line 202-202 is almost the same as the configuration shown in FIG.

The remaining structure is almost the same as that of the above-described fourth embodiment, so that the same members are denoted by the same reference numerals and description thereof will be omitted.

Next, the manufacturing method of the present embodiment will be described. The manufacturing method of the present embodiment is different from the manufacturing method of the fourth embodiment in the method of forming p + impurity region 1c.

In the present embodiment, in forming p + impurity region 1c, first, a resist pattern 14b as shown in FIGS. 23 and 24 is formed. The resist pattern 14b is formed not only in the formation region of the gate electrode layer of the transfer switch M1, but also in the PD region and the FD region.
The element isolation insulating layer 3 is formed so as to open near the end E. Then, p + impurity region 1c is formed by ion-implanting a p-type impurity such as B or BF 2 using the resist pattern 14b as a mask.

The other manufacturing steps are almost the same as those in the fourth embodiment, and the description is omitted.

In the present embodiment, the p + impurity region 1c is formed under the gate electrode layer 8a of the transfer switch M1, so that the occurrence of dark current can be suppressed as in the first to fourth embodiments. it can.

Since the p + impurity region 1c is also distributed on the surface of the semiconductor substrate 2 adjacent to the end E of the element isolation insulating layer 3 in the PD region and the FD region, similar to the third embodiment, There is also an effect of suppressing generation of dark current in the region and the FD region.

Since the end face of the gate electrode layer 8a is spaced from the end E of the element isolation insulating layer 3, separation between elements by pn junction can be performed at this portion.

Sixth Embodiment FIG. 29 is a plan view schematically showing a configuration of a semiconductor device according to a sixth embodiment of the present invention. FIG. 30 is a schematic cross-sectional view along the line 201-201 in FIG.

Referring to FIGS. 29 and 30, in the present embodiment, the shape of gate electrode layer 8a of transfer switch M1 is different from that in the fourth embodiment. In the gate electrode layer 8a of the transfer switch M1, both ends in the longitudinal direction do not ride on the end E of the element isolation insulating layer 3, and each end face of each end is located on the p + impurity region 1c; It has an interval from the end E of the isolation insulating layer 3. With such a configuration, the element isolation of the transfer switch M1 is all pn.
It will be composed of junctions. 29-2 in FIG.
The cross-sectional structure along the line 02 is almost the same as the configuration shown in FIG.

The remaining structure is substantially the same as that of the above-described fourth embodiment. Therefore, the same members are denoted by the same reference numerals and description thereof will not be repeated.

Next, the manufacturing method of the present embodiment will be described. FIGS. 31 and 32 are schematic sectional views showing a method of manufacturing a semiconductor device in the sixth embodiment of the present invention in the order of steps. The manufacturing method according to the present embodiment goes through the steps shown in FIGS. 6 and 7 and then the steps shown in FIGS. 16 and 17. Thereafter, referring to FIG. 31, a resist pattern 14c is formed on semiconductor substrate 2. This resist pattern 14c is formed so as to open only near the end E of the element isolation insulating layer 3 near the region where the gate electrode of the transfer switch M1 is to be formed, as shown in FIG.
Using this resist pattern 14c as a mask, B or B
A p-type impurity such as F 2 is ion-implanted. Thus, the semiconductor substrate 2 adjacent to the end E of the element isolation insulating layer 3
P + impurity region 1c is formed on the surface of.

Referring to FIG. 32, gate electrode layer 8a of transfer switch M1 is formed on the surface of semiconductor substrate 2 with gate insulating layer 7 interposed. The gate electrode layer 8a is formed so that both end portions do not run over the end portion E of the element isolation insulating layer 3 and each end surface of the both end portions is a p + impurity region 1c.
It is formed by being patterned so as to be located above.

Thereafter, an n-type source region 4, an n-type drain region 6a, a p-type impurity region 5, an interlayer insulating film 9, a wiring layer 10 and the like are formed, and the present embodiment shown in FIGS. The semiconductor device is completed.

In the present embodiment, the p + impurity region 1c is formed below the gate electrode layer 8a of the transfer switch M1, so that the occurrence of dark current can be suppressed as in the first to fifth embodiments. it can.

Further, since each end face of both ends of the gate electrode layer 8 has a space with the end E of the element isolation insulating layer 3, the element isolation of the transfer switch M1 is entirely constituted by a pn junction. Become.

Seventh Embodiment FIG. 34 is a plan view schematically showing a configuration of a semiconductor device according to a seventh embodiment of the present invention.

Referring to FIG. 34, the present embodiment is different from the structure of the sixth embodiment in the shape of p + impurity region 1c. The p + impurity region 1c is
In the region D, it is also formed on the surface of the semiconductor substrate 2 adjacent to the end E of the element isolation insulating layer 3. The cross-sectional structure along the line 201-201 in FIG. 34 is substantially the same as the configuration shown in FIG. 30, and the cross-sectional structure along the line 202-202 is
This is almost the same as the configuration shown in FIG.

The remaining structure is almost the same as that of the sixth embodiment described above, and therefore the same members are denoted by the same reference characters and description thereof will not be repeated.

Next, the manufacturing method of the present embodiment will be described. 35 and 36 are a cross-sectional view and a plan view illustrating the method for manufacturing the semiconductor device in the seventh embodiment of the present invention. It should be noted that FIGS. 35 (a) and (b) correspond to 201- in FIG.
It is a schematic sectional drawing which follows the 201 line and the 202-202 line.

The manufacturing method of the present embodiment is similar to that of the sixth embodiment.
In the step of forming p + impurity region 1c as compared with the manufacturing process of

In the present embodiment, in forming p + impurity region 1c, first, a resist pattern 14d as shown in FIGS. 35 and 36 is formed. The resist pattern 14d is formed not only in the formation region of the gate electrode layer of the transfer switch M1 but also in the PD region and the FD region so as to open near the end E of the element isolation insulating layer 3. Using this resist pattern 14d as a mask, ap + impurity region 1c is formed by ion-implanting a p-type impurity such as B or BF 2 .

The manufacturing method according to the present embodiment other than the above is the same as the manufacturing method according to the above-described sixth embodiment, and a description thereof will be omitted.

In the present embodiment, the p + impurity region 1c is formed under the gate electrode layer 8a of the transfer switch M1, so that the occurrence of dark current can be suppressed as in the first to sixth embodiments. it can.

Since p + impurity region 1c is also distributed on the surface of semiconductor substrate 2 adjacent to end E of element isolation insulating layer 3 in the PD region and FD region, the same as in the third and fifth embodiments. , PD region and FD region.

Further, since each end face of both ends of the gate electrode layer 8a is spaced from the end E of the element isolation insulating layer 3,
All the element isolations of the transfer switch M1 are configured by pn junctions.

It should be noted that the embodiment disclosed this time is an example in all respects and is not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0118]

According to the semiconductor device having the solid-state imaging device of the present invention, the high-concentration impurity region is formed near the lower side of the gate electrode layer and adjacent to the end of the isolation insulating layer.
Therefore, the extension of the depletion layer toward the end of the isolation insulating layer is suppressed by the high-concentration impurity region. Therefore, it becomes difficult for crystal defects and the like near the isolation insulating layer to be taken into the depletion layer,
Generation of dark current in the transfer insulated gate field effect transistor portion can be suppressed, and the characteristics of the image sensor can be improved.

In the above semiconductor device, preferably, the photoelectric conversion element has a photodiode, and the high-concentration impurity region is adjacent to an end of the isolation insulating layer so as to surround the photodiode in the photodiode formation region. It is formed on the main surface of the semiconductor substrate. Thus, generation of dark current due to crystal defects at the end of the isolation insulating layer in the photodiode formation region can be suppressed.

In the above-described semiconductor device, preferably, the high concentration impurity region is formed to extend below the isolation insulating layer so as to be in contact with the lower surface of the isolation insulating layer. The high-concentration impurity region achieves electrical isolation between the transfer insulated gate field effect transistor and other elements.

In the above-described semiconductor device, preferably, the gate electrode layer is formed so as to ride on both ends of one side and the other side of the isolation insulating layer. Thus, element isolation of the transfer insulated gate field effect transistor can be performed by the isolation insulating layer.

In the above semiconductor device, preferably, the gate electrode layer is formed so as to have a space between at least one end on one side and the other side of the isolation insulating layer. Thereby, the element isolation of the transfer insulated gate field effect transistor can be configured by pn isolation.

In the above semiconductor device, preferably, the element isolation of the transfer insulated gate field effect transistor is p
It has a configuration performed by n-junction separation. Thus, element isolation of the transfer insulated gate field effect transistor can be performed by pn junction isolation.

In the above semiconductor device, preferably, the insulated gate field effect transistor for transfer has a source region of the second conductivity type formed on the main surface of the semiconductor substrate so as to sandwich a region located below the gate electrode layer. And a drain region. The photodiode has a first conductivity type region of the semiconductor substrate and a second conductivity type impurity region forming a pn junction. The source region and the second conductivity type impurity region are formed of the same region. This makes it possible to arrange the photodiode and the transfer insulated gate field effect transistor side by side within a small plane occupation area.

In the manufacturing method according to one aspect of the present invention, high-concentration impurity regions adjacent to the end of the isolation insulating layer can be formed by implanting ions by oblique implantation. Therefore, the extension of the depletion layer toward the end of the isolation insulating layer is suppressed by the high concentration impurity region. Therefore, it becomes difficult for crystal defects at the end of the isolation insulating layer to be taken into the depletion layer,
Generation of dark current can be suppressed, and the characteristics of the image sensor can be improved.

In the manufacturing method according to one aspect of the present invention, ions are preferably implanted at an angle of 30 ° or more and 60 ° or less with respect to a perpendicular to the main surface of the semiconductor substrate. Thereby, the high-concentration impurity region can be appropriately formed.

In the manufacturing method according to another aspect of the present invention, high-concentration impurity regions adjacent to the end of the isolation insulating layer can be formed by implanting ions using a mask. Therefore, the extension of the depletion layer toward the end of the isolation insulating layer is suppressed by the high concentration impurity region. Therefore, a crystal defect or the like at an end portion of the isolation insulating layer is less likely to be taken into the depletion layer, generation of dark current can be suppressed, and characteristics of the image sensor can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view taken along line 201-201 of FIG.

FIG. 3 is a schematic sectional view taken along the line 202-202 in FIG. 1;

FIG. 4 is a diagram showing an impurity concentration distribution in a semiconductor substrate along a line 211-211 in FIG. 2;

FIG. 5 is a diagram showing an impurity concentration distribution in the semiconductor substrate along the line 212-212 in FIG. 2;

FIG. 6 is a schematic sectional view showing a first step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a schematic sectional view showing a second step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view showing a third step of the method for manufacturing a semiconductor device in the first embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing a fourth step of the method for manufacturing a semiconductor device in the first embodiment of the present invention.

FIG. 10 is a diagram illustrating that dark current can be suppressed in the semiconductor device according to the first embodiment of the present invention;

FIG. 11 is a plan view schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention.

FIG. 12 is a schematic sectional view taken along the line 201-201 in FIG. 11;

FIG. 13 is a schematic sectional view taken along the line 202-202 in FIG. 11;

14 is a diagram showing an impurity concentration distribution in the semiconductor substrate along the line 211-211 in FIG. 12;

FIG. 15 is a diagram showing an impurity concentration distribution in the semiconductor substrate along line 212-212 in FIG. 12;

FIG. 16 is a schematic cross-sectional view showing a first step of the method for manufacturing a semiconductor device in the second embodiment of the present invention.

FIG. 17 is a schematic cross-sectional view showing a second step of the method for manufacturing a semiconductor device in the second embodiment of the present invention.

FIG. 18 is a schematic cross-sectional view showing a third step of the method for manufacturing a semiconductor device in the second embodiment of the present invention.

FIG. 19 is a schematic cross-sectional view showing a fourth step of the method for manufacturing a semiconductor device in the second embodiment of the present invention.

FIG. 20 is a plan view showing a state of a resist pattern used in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 21 is a plan view schematically showing a configuration of a semiconductor device according to a third embodiment of the present invention.

FIG. 22 is a schematic sectional view taken along the line 202-202 in FIG. 21;

FIG. 23 is a schematic sectional view showing the method for manufacturing the semiconductor device in the third embodiment of the present invention;

FIG. 24 is a plan view showing a state of a resist pattern used in the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 25 is a plan view schematically showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.

26 is a schematic sectional view taken along the line 201-201 in FIG.

FIG. 27 is a schematic sectional view showing the method for manufacturing the semiconductor device in the fourth embodiment of the present invention.

FIG. 28 is a plan view schematically showing a configuration of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 29 is a plan view schematically showing a configuration of a semiconductor device in a sixth embodiment of the present invention.

FIG. 30 is a schematic sectional view taken along the line 201-201 in FIG. 29.

FIG. 31 is a schematic cross-sectional view showing a first step of the method for manufacturing a semiconductor device in the sixth embodiment of the present invention.

FIG. 32 is a schematic sectional view showing a second step of the method for manufacturing the semiconductor device according to the sixth embodiment of the present invention;

FIG. 33 is a plan view showing a state of a resist pattern used in the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention.

FIG. 34 is a plan view schematically showing a configuration of a semiconductor device in a seventh embodiment of the present invention.

FIG. 35 is a schematic sectional view showing the method for manufacturing the semiconductor device in the seventh embodiment of the present invention.

FIG. 36 is a plan view showing a state of a resist pattern used in the method for manufacturing a semiconductor device according to the seventh embodiment of the present invention.

FIG. 37 is a diagram illustrating a circuit configuration of a CMOS image sensor.

FIG. 38 is a plan view schematically showing a configuration of a conventional semiconductor device.

FIG. 39 is a schematic sectional view taken along the line 201-201 in FIG. 38.

40 is a schematic sectional view taken along the line 202-202 in FIG. 38.

FIG. 41 is an enlarged plan view showing a gate electrode portion of the transfer switch M1 of FIG. 38;

[Explanation of symbols]

1a, 1b, 1cp + impurity region, 2 semiconductor substrate,
3 element isolation insulating layer, 7 gate insulating layer, 8a gate electrode layer, 4 source region, 6a drain region, M1
Transfer switch, PD photodiode, M3 amplifier.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA05 AB01 BA14 CA04 CA18 EA03 EA14 FA06 FA25 FA28 FA33 FA42 5F049 MA02 NA04 NA05 NB05 PA14 QA11 RA04 RA06 RA08 SE09

Claims (10)

    [Claims]
  1. A photoelectric conversion element for converting light into an electric signal; an amplifying means for amplifying the electric signal; and a switch for transferring the electric signal converted by the photoelectric conversion element to the amplifying means. A semiconductor device having a solid-state image sensor, comprising: a first conductive type semiconductor substrate having a main surface; and a transfer insulated gate field effect transistor. An isolation insulating layer formed on the main surface of the semiconductor substrate to electrically isolate the semiconductor substrate from the elements of the semiconductor substrate sandwiched between one side and the other side of the isolation insulating layer facing each other. A gate electrode layer of the transfer insulated gate field effect transistor formed to extend on the main surface; and a transfer insulated gate field effect transistor from an end of the isolation insulating layer. A first conductive layer formed on the main surface of the semiconductor substrate so as to extend to the side where the star is formed and located immediately below the gate electrode layer, and having an impurity concentration higher than that of the first conductivity type region of the semiconductor substrate; A semiconductor device having a solid-state imaging device, comprising: a conductive high-concentration impurity region.
  2. 2. The photoelectric conversion element includes a photodiode, and the high-concentration impurity region is adjacent to an end of the isolation insulating layer so as to surround a periphery of the photodiode in a region where the photodiode is formed. 2. The semiconductor device having the solid-state imaging device according to claim 1, wherein the semiconductor device is formed on a main surface of the semiconductor substrate.
  3. 3. The solid-state imaging device according to claim 1, wherein the high-concentration impurity region is formed to extend below the isolation insulating layer so as to contact a lower surface of the isolation insulating layer. Semiconductor device.
  4. 4. The solid-state imaging device according to claim 1, wherein said gate electrode layer is formed so as to ride on both ends of one side and the other side of said isolation insulating layer. A semiconductor device having:
  5. 5. The device according to claim 1, wherein the gate electrode layer is formed so as to have a space between at least one end of one side and the other side of the isolation insulating layer. A semiconductor device having the solid-state imaging device according to item 1.
  6. 6. The semiconductor device having a solid-state imaging device according to claim 5, wherein the device isolation of the insulated gate field effect transistor for transfer has a configuration in which pn junction isolation is performed.
  7. 7. The source and drain regions of the second conductivity type formed on the main surface of the semiconductor substrate so as to sandwich a region located below the gate electrode layer in the insulated gate field effect transistor for transfer. The photodiode has a first conductivity type region of the semiconductor substrate and a second conductivity type impurity region forming a pn junction, and the source region and the second conductivity type impurity region A semiconductor device having the solid-state imaging device according to claim 1, wherein the semiconductor device comprises the same region.
  8. 8. A photoelectric conversion element for converting light into an electric signal, amplification means for amplifying the electric signal, and a switch for transferring the electric signal converted by the photoelectric conversion element to the amplification means. A method for manufacturing a semiconductor device having a solid-state imaging device, comprising: a transfer insulated gate field-effect transistor as described above, wherein a mask layer is formed on a main surface of a semiconductor substrate of a first conductivity type; Implanting ions of the first conductivity type obliquely to the main surface of the semiconductor substrate using the mask as a mask, and performing a heat treatment while leaving the mask layer, to form an isolation insulating layer in a region exposed from the mask layer. Formed on the main surface of the semiconductor substrate from the end of the isolation insulating layer to the area where the transfer insulated gate field effect transistor is formed, while being in contact with the lower surface of the isolation insulating layer. Forming a high-concentration impurity region of the first conductivity type extending so as to have an impurity concentration higher than the impurity concentration of the first conductivity type region of the semiconductor substrate; Forming a gate electrode layer of the transfer insulated gate type field effect transistor so as to extend on the main surface of the semiconductor substrate sandwiched between the other side. A method for manufacturing a semiconductor device.
  9. 9. The method for manufacturing a semiconductor device having a solid-state imaging device according to claim 8, wherein said ions are implanted at an angle of 30 ° or more and 60 ° or less with respect to a perpendicular to a main surface of said semiconductor substrate.
  10. 10. A photoelectric conversion element for converting light into an electric signal, amplifying means for amplifying the electric signal,
    A method for manufacturing a semiconductor device having a solid-state imaging device, comprising: a transfer insulated gate field effect transistor as a switch for transferring the electric signal converted by the photoelectric conversion element to the amplifying means; Selectively forming an isolation insulating layer on the main surface of the semiconductor substrate, and implanting ions of the first conductivity type using a mask layer that opens the main surface of the semiconductor substrate adjacent to an end of the isolation insulating layer as a mask. A high-concentration impurity region of the first conductivity type extending on the main surface of the semiconductor substrate from the end of the isolation insulating layer to the formation region side of the transfer insulated gate field effect transistor, Forming the mold region to have an impurity concentration higher than the impurity concentration of the mold region; and forming the semiconductor layer sandwiched between one side and the other side of the isolation insulating layer facing each other. Forming a gate electrode layer of the transfer insulated gate field effect transistor so as to extend on the main surface of the substrate and directly above the high concentration impurity region. Device manufacturing method.
JP11166843A 1999-06-14 1999-06-14 Semiconductor device with solid-state image sensing element and its manufacture Withdrawn JP2000353801A (en)

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