JP2000340748A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor integrated circuit device, such as a standard cell or the like possessed of basic cell rows designed by an automatic arrangement/wiring program to be protected against a latch-up phenomenon without causing it to increase in area. SOLUTION: A semiconductor integrated circuit device is equipped with belt-like high-concentration diffused regions 8 and 9 located along the edge of a basic cell row, and the diffused regions 8 and 9 are connected to intra-cell high-concentration diffused regions 4 and 6 formed in the basic cells. The high- concentration diffused regions 4, 6, 8, and 9 are arranged in the basic cell row, so that semiconductor integrated circuit device can be designed where a latch-up phenomenon can be prevented from occurring between the basic cell rows, without deteriorating it in arrangement.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to the prevention of latch-up in a minimum unit basic cell automatically arranged and wired by an automatic arrangement and wiring program of a gate array system or a standard cell system. A stopper for strengthening is provided.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device design system called a gate array system or a standard cell system which is currently mainstream, it is important to prevent latch-up of a basic cell constituted by active transistors and the like. It is one of the issues.

Conventionally, in a semiconductor integrated circuit device designed by the automatic placement and routing method, as a measure for preventing latch-up of a basic cell row in which basic cells are arranged in a row, both ends of the basic cell row or adjacent to each other are provided. A method of arranging a latch-up preventing stopper cell between basic cell rows has been adopted.

[0004] For example, Japanese Patent Application Laid-Open No. H3-131066 discloses that stopper cells having the same structure as the basic cells are used as the stopper cells arranged at both ends of the basic cell row. The technique described in this publication aims to prevent latch-up occurring between an input / output cell arranged near both ends of a basic cell row and the basic cell row. That is, latch-up in the direction in which the basic cell columns are arranged is prevented.

However, in order to further increase the density of the semiconductor integrated circuit device, it is particularly important to arrange the basic cell rows and to make them finer in the orthogonal direction. Therefore, a technique for preventing the latch-up in the orthogonal direction is required. Is required.

Here, Japanese Patent Application Laid-Open No. 8-222640 discloses that a high-concentration diffusion layer region of the same conductivity type as a substrate is formed between a basic cell row and a basic cell row adjacent thereto. By connecting to the power supply conductor provided above,
A technique for preventing latch-up occurring between two adjacent basic cell columns is described. That is, the technique described in this publication prevents latch-up in the direction orthogonal to the arrangement of the basic cell rows.

[0007]

SUMMARY OF THE INVENTION However, Japanese Patent Application Laid-Open No. Hei 8-2
In the technique disclosed in Japanese Patent No. 22640, it is necessary to arrange a power conductor such as aluminum between two adjacent basic cell rows in order to prevent latch-up. However, a signal wiring is often arranged between two adjacent basic cell columns, and arranging a power supply conductor between the two lines always limits the degree of freedom of design in a semiconductor integrated circuit device. There is.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a stopper for preventing latch-up between two adjacent basic cell columns in a semiconductor integrated circuit device having a basic cell column arranged by an automatic placement and routing program. An object of the present invention is to provide a semiconductor integrated circuit which can be arranged without dropping and without increasing a chip area.

[0009]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a plurality of basic cell rows in which a plurality of basic cells are arranged in a row. A contact region for supplying power to each basic cell is provided in each basic cell as a high-concentration diffusion layer region in the cell, and the high-concentration diffusion layer region in each cell is formed at an edge of a corresponding basic cell row. It is characterized by being connected by a belt-like high concentration diffusion layer region arranged along.

According to the semiconductor integrated circuit device of the present invention, a high-concentration diffusion layer region in a cell connected to a power supply line for supplying power to each basic cell is provided in each basic cell, and each cell is Since the inner high-concentration diffusion layer regions are interconnected by a band-like high-concentration diffusion layer region extending along the edge of the basic cell, the band-like high-concentration diffusion layer region functions as a stopper for preventing latch-up, On the other hand, the high-concentration diffusion layer region in each cell can be used to supply power to the basic cell, so that the area occupied by the basic cell is not particularly increased.
The basic cell of the present semiconductor integrated circuit device is preferably a CMO
It is constituted by an SFET. The band-shaped high-concentration diffusion layer region is preferably arranged in the basic cell and designed by an automatic arrangement and wiring program for the basic cell.

Here, the high-concentration diffusion layer region in the present invention refers to a region having an impurity concentration higher than the surrounding impurity concentration. For example, an impurity concentration approximately equal to the impurity concentration of the source / drain region of the MOS transistor. Area.

In a preferred example of the semiconductor integrated circuit device according to the present invention, the band-shaped high-concentration diffusion layer regions are arranged at both edges of a basic cell row. In this case, one basic cell column is
Latch-up between two adjacent basic cell columns can be prevented.

The integrated circuit device of the present invention is preferably configured as a standard cell or a gate array.
This is because the basic cell row is particularly frequently used in these semiconductor integrated circuit devices.

It is also a preferred embodiment of the present invention that a power supply wiring is arranged above the contact region. In this case, it is possible to dispose the signal wiring on the upper portion of the band-shaped high concentration diffusion layer region and on the upper portion between two adjacent basic cell columns.

Here, it is preferable that at least the basic cell row is designed by a computer using an automatic placement and routing program. It is also a preferred embodiment of the present invention to arrange latch-up prevention cells for preventing latch-up at both ends of the basic cell row.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to the drawings based on embodiments of the present invention. FIG.
FIG. 2 is a plan view showing a basic cell (basic logic cell) which is a minimum unit of the semiconductor integrated circuit device of the present invention. Many basic cells having the same structure are arranged in rows in the left-right direction of the drawing to form a basic cell row. In addition, a plurality of basic cell rows are arranged at intervals in the vertical direction of the drawing. The upper portion between the basic cell rows is used, for example, as a passage space for signal wiring. The arrangement of such basic cells is determined by an automatic placement and routing program such as a gate array system or a standard cell system.

Each elementary cell has a P-type (MO) on one side of the column.
S) The transistor region P1 is used, and the other side is N-type (MO
S) Transistor region N1. The P-type transistor region P1 is an N-well region 1 formed in a P-type substrate.
Within. A strip-shaped high-concentration P-type diffusion layer region 8 is formed at the edge of the basic cell row in the N-well region 1 along the edge. Adjacent to the band-shaped high-concentration P-type diffusion layer region 8, the in-cell high-concentration N-type diffusion layer 4 is disposed inside. A high-potential power line 2 is disposed directly above the high-concentration N-type diffusion layer region 4 in the cell, and the high-potential power line 2 is connected to the high-concentration N-type diffusion layer region 4 in the cell by a contact 5A. In the N-well region, the source 2 of the P-type transistor is located immediately below the high-potential power supply line 2 adjacent to the high-concentration N-type diffusion layer 4.
1 extends towards the center of the elementary cell. The high potential power supply line 2 and the source 21 are connected via a contact 5B. The drain 22 of the P-type transistor is connected to the gate electrode 2
3 are arranged to face the source 21. The drain is connected to the drain of the N-type transistor via the contact 5C and the wiring 24. The in-cell high-concentration N-type diffusion layer region 4 arranged in the basic cell and the strip-like high-concentration N-type diffusion layer region 8 connected thereto strengthen the potential of the N-well 1 and prevent latch-up. Functions as a stopper.

The N-type transistor region N1 is located in the P-type substrate region, and a band-like high-concentration P-type diffusion layer region 19 is formed along the edge of the basic cell row. Inside the band-like high-concentration P-type diffusion layer region 19, the high-concentration P
The mold diffusion layer region 6 is arranged. A low-potential power supply (ground) line 3 is disposed immediately above the high-concentration P-type diffusion layer region 6 in the cell, and the low-potential power supply line 3 is connected to the high-concentration P-type diffusion layer region 6 in the cell by a contact 7A. I have. In the N-type transistor region N1, the source 25 of the N-type transistor extends from directly below the low-potential power supply line 3 adjacent to the intra-cell high-concentration P-type diffusion layer region 6 toward the center of the basic cell. Contact 7 between low potential power supply line 3 and source 25
It is connected via B. Drain 2 of N-type transistor
Reference numeral 6 is arranged to face the source 25 with the gate electrode 23 interposed therebetween. The drain 26 includes the contact 7C and the wiring 2
4 is connected to the drain 22 of the P-type transistor. In-cell high-concentration P-type diffusion layer region 6 arranged in the basic cell and band-like high-concentration P-type diffusion layer region 9 connected thereto
Strengthens the potential of the N-type transistor region N1, and
Functions as a latch-up prevention stopper.

In an automatic placement and routing program used in a gate array system or a standard system, etc., general automatic placement of basic logic cells is performed by regularly setting cell array areas where basic logic cells can be placed by setting parameters. A method of arranging and arranging the basic logical cells specified by the connection information in the arranged cell column area is adopted.

According to the present invention, a function as a stopper for preventing latch-up in a basic logic cell automatically arranged is provided.
Since the in-cell high-concentration diffusion layer region and the belt-like high-concentration diffusion layer region are provided, the automatic placement and routing can be realized by the conventional automatic placement and routing program without using a new technology.

FIG. 2 shows the vicinity of an end of a basic cell row in a semiconductor integrated circuit device according to a second embodiment of the present invention. Although the structure of each basic logic cell in the basic cell row is the same as that of the first embodiment, in this embodiment, the latch-up stopper cells 10 are arranged at both ends of the basic cell row. The strip-like high-concentration N-type diffusion layer region 18 arranged at the inner edge of the P-type transistor region P1 extends into the latch-up stopper cell 10, and extends in a direction orthogonal to the basic cell column. Further, the belt-like high-concentration P-type diffusion layer region 19 arranged at the inner edge of the N-type transistor region N1 extends and similarly enters the latch-up stopper cell 10, and extends in a direction orthogonal to the basic cell column. Each of the band-shaped high concentration diffusion layer regions 18 and 19 is provided with a latch-up stopper cell 10.
, The corresponding power supply lines 12 and 13 respectively,
They are connected via contacts 15 and 17.

The latch-up stopper cells 10 in the present embodiment function to prevent the latch-up trigger from entering the basic cell row from the left and right directions by being arranged at the left and right ends of the basic cell row. In particular, in the present embodiment, the configuration in which the band-like high-concentration diffusion layer regions 18 and 19 almost completely surround the inside of the basic cell row is employed, so that a greater latch-up prevention effect can be obtained.

In each of the above embodiments, since the upper and lower portions of the basic logic cell are covered with the diffusion layer without any gap, the entry of the latch-up trigger from above and below can be prevented. Since this stopper is provided in the basic cell row, the effect can be obtained only by automatically arranging the basic cells in the same manner as in the related art. Further, since the stopper is formed only of the diffusion layer not used for the wiring, the upper part of the area can be used as a signal wiring area, and a wiring area similar to the conventional one can be secured. Therefore, the prevention of latch-up can be enhanced without reducing the design efficiency and without increasing the chip area.

As described above, the present invention has been described based on the preferred embodiment. However, the semiconductor integrated circuit device of the present invention is not limited to the configuration of the above-described embodiment, but is limited to the above-described embodiment. Various modifications and changes from the configuration are also included in the scope of the present invention.

[0025]

As described above, according to the semiconductor integrated circuit device of the present invention, the design efficiency of the semiconductor integrated circuit device designed by the automatic placement and routing program is not reduced and the chip area is not increased. This has the effect of enhancing latch-up prevention.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor integrated circuit device according to a second embodiment of the present invention.

[Explanation of symbols]

 P1 P-type transistor region N1 N-type transistor region 1 N-well 2, 12 High-potential power supply line 3, 13 Low-potential power supply line 4 High-concentration N-type diffusion layer region in cell 5A, 5B, 5C, 15 Contact 6 High-concentration in cell P-type diffusion layer region 7A, 7B, 7C, 17 Contact 8, 18 High band-concentration N-type diffusion layer region 9, 19 High band-concentration P-type diffusion layer region 10 Latch-up stopper cell 21 Source of P-type transistor 22 P-type transistor 23 Gate electrode 24 Wiring 25 Source of N-type transistor 26 Drain of N-type transistor

Claims (7)

[Claims] In a semiconductor integrated circuit device having a plurality of basic cell rows in which a plurality of basic cells are arranged in a row, a contact area for supplying power to each basic cell is provided within each basic cell. A semiconductor integrated circuit device provided as a concentration diffusion layer region, wherein the high-concentration diffusion layer regions in each cell are connected by a band-like high-concentration diffusion layer region arranged along an edge of a basic cell row. . 2. The semiconductor integrated circuit device according to claim 1, wherein the in-cell high-concentration diffusion layer region and the band-like high-concentration diffusion layer region are arranged at both edges of a basic cell row. 3. The semiconductor integrated circuit device according to claim 1, configured as a standard cell or a gate array. 4. The semiconductor integrated circuit device according to claim 1, wherein a power supply wiring is arranged above said contact region. 5. The semiconductor integrated circuit device according to claim 1, wherein at least the basic cell row is designed by a computer using an automatic placement and routing program. 6. The semiconductor integrated circuit device according to claim 1, wherein said band-shaped high-concentration diffusion layer region is arranged in a basic cell. 7. A latch-up prevention cell is disposed at both ends of the basic cell row, and the latch-up prevention cell extends in a direction orthogonal to the basic cell row and has a high concentration inside the cell extending from the band-like high concentration diffusion layer region. 7. A diffusion layer region.
The semiconductor integrated circuit device according to any one of the above.