JP2000340615A - Semiconductor device, wiring material for the same, and their manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be manufactured in a highly reliable state at a low cost, a wiring material constituting part of the device, and methods for manufacturing the device and material. SOLUTION: A semiconductor device is manufactured by bonding external terminals (solder balls) to copper wiring after a semiconductor chip is bonded to a wiring material by a bump bonding method. The wiring material is composed of a polyimide film carrying wiring on one surface and an adhesive layer covering the wiring and the front end sections of bumps are exposed from the adhesive layer. In addition, the polyimide film has via holes for forming the external terminals. At bonding the semiconductor chip to the wiring material, the chip is hot-pressed to the material, and thereafter, a bonding tool is pressed against the polyimide film existing on the bonding spot and energy is given to the tool under a prescribed condition.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for various electronic devices, a wiring material constituting a part thereof, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor devices such as semiconductor packages are
It is manufactured by joining a semiconductor chip and a wiring material.
In the past, the wire bonding method using gold wire was mainly used as the electrical bonding method, but recently, the bump bonding method has been adopted to meet the demand for smaller and lighter electronic devices. It has become. In this bump bonding method, a projecting electrode called a bump is formed on an electrode pad of a semiconductor chip or an electrode portion of a wiring material for mounting the semiconductor chip, and both are electrically connected via the bump. Thus, the wiring in the semiconductor device can be shortened, and the semiconductor device can be easily downsized.

Therefore, a conventional example of manufacturing a semiconductor device by such a bump bonding method is shown in FIGS.
This will be described with reference to FIG. First, FIG. 4 shows an example of a configuration of a wiring material that has already been proposed, and the above-described bump is formed on the wiring material. That is, this wiring material is basically composed of an insulating polyimide film having a wiring formed of a copper foil on one surface thereof, and an adhesive layer covering the wiring. A bump is formed in a part of the wiring at a position corresponding to the electrode part of the semiconductor chip, and the tip is configured to protrude from the adhesive layer. On the other surface of the polyimide film, an opening for a bonding tool is provided at a bump formation position, and a via hole for forming an external terminal is provided. And
The surface of the bump protruding from the adhesive layer and the wiring exposed in the opening for the bonding tool and the via hole for forming the external terminal are plated as necessary.

Next, a method of manufacturing a wiring material having such a configuration will be described with reference to FIG. First, an etching resist layer is provided on the surface of a double-sided copper-clad substrate composed of three layers of a copper foil, a polyimide film and a copper foil, and a mask for forming a bump is brought into close contact with the surface of the etching resist layer, and is exposed and developed. Thereby, a resist pattern for forming a bump is formed (see FIG. 5A). Then, after the exposed copper foil portion is half-etched to form a bump, the resist layer remaining on the surface of the bump is removed (see FIG. 5B).

[0005] Next, an etching resist layer is provided again on the copper foil surface on which the bumps are formed, and a mask for forming a wiring pattern is brought into close contact with the mask and exposed and developed. Form a pattern.
Then, after the exposed copper foil portion is etched, the remaining etching resist is peeled off and removed to form a predetermined wiring pattern. Thereafter, an adhesive layer is formed on the entire surface on the wiring side, and curing is performed. As a forming method, a method of bonding an adhesive filmed in advance is usually used because a uniform film thickness can be easily obtained (see FIG. 5D).

Next, the entire surface of the adhesive layer thus formed is etched to reduce only the thickness of the adhesive layer and expose the tip of the bump (see FIG. 5E).
After that, an etching resist layer is formed again on both surfaces, and the opening of the bonding tool and the via hole for forming external terminals are formed on the surface of the etching resist layer opposite to the surface on which the wiring is laid. A desired etching resist pattern is formed by bringing a mask having a pattern into close contact, exposing and developing. Then, after etching the exposed copper foil portion, the remaining etching resist is removed and removed to form a copper mask pattern for etching the polyimide film (see FIG. 5F).

Next, by etching the polyimide film, a bonding tool opening for inserting a bonding tool when performing bump bonding, and an external terminal forming via for forming external terminals after bump bonding. Form a hole. Then, the wiring portions exposed inside are protected by a resist, the remaining copper mask is removed by etching, and then all the remaining etching resist layers are removed (FIG. 5 (g)).
reference). Finally, if necessary, gold plating is applied to the copper surface and the bump surface in the via holes for forming external terminals to complete the wiring material (see FIGS. 5 (h) and 4).

Next, steps from bump bonding of the wiring material manufactured as described above to a semiconductor chip and forming a semiconductor device will be described with reference to FIG. First, the bump of the wiring material is aligned with the electrode portion of the semiconductor chip, and the two are overlapped. Then, by heating and pressing on a heating stage, both are adhered by an adhesive (see FIG. 6A).

Next, with the semiconductor chip placed on the heating stage, the bonding tool is inserted into the opening for the bonding tool, and a predetermined load and ultrasonic waves are applied from the back side of the bump to the semiconductor chip. The electrodes of the chip and the bumps are joined (see FIG. 6B). Thereafter, external terminals (solder bumps) are formed in the via holes for forming external terminals of the polyimide film (see FIG. 6C). The semiconductor device obtained in this way is very advantageous when mounted on a printed wiring board at a high density because the plane area of the wiring material can be made almost the same as the plane area of the semiconductor chip. .

[0010]

The problem to be solved by the present invention is shown in FIG.
When manufacturing a conventional semiconductor device as shown in
As described above, a bonding tool opening was formed in the polyimide film, and a bonding tool was inserted into the opening to bond the bump of the wiring material to the electrode portion of the semiconductor chip. The reason for providing the tool opening is that under the conventional joining conditions, if you try to join with a polyimide film interposed,
This is because sufficient energy was not applied to the bumps, and complete joining was not possible. In addition, when the temperature, the load, the ultrasonic output, and the time are appropriately adjusted and the bondable energy is applied to the bump, the semiconductor chip may be broken.

For this reason, in the conventional semiconductor device shown in FIG. 6C, the wiring is exposed in the opening for the bonding tool even after completion, and is exposed to the surrounding environment. Was. Therefore, such a configuration
It was not always sufficient in terms of insulation reliability and the like. In the opening, not only the wiring portion but also a part of the adhesive layer is exposed. for that reason,
As shown in FIG. 5 (g), in the step of etching the polyimide film, it is necessary to select a special adhesive that does not dissolve in the polyimide film etchant, which is a factor in the production of wiring materials. It was a shackle when reducing costs.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device capable of reducing manufacturing costs and obtaining high reliability and a part thereof. And a method of manufacturing the same.

[0013]

In order to achieve the above-mentioned object, a method of manufacturing a semiconductor device according to the present invention is characterized in that when a semiconductor chip and a wiring material are bump-bonded, an insulating material is provided on the back surface of the bonding portion on the wiring material side. With the film interposed,
A predetermined load and energy required for bonding are applied to the bump bonding section from the insulating film side. In this case, the energy is ultrasonic energy, the joining temperature is 250 to 310 ° C., and the load is 100 to 220 gf.
When the conditions for the / bump and the ultrasonic output are set to 0.8 to 2.5 W, suitable bonding is performed. Further, it is more effective to set the thickness of the insulating film to 12 to 75 μm.

Further, in order to achieve the above object, a wiring material for a semiconductor device according to the present invention provides an insulating film having a wiring provided with bumps at positions corresponding to electrodes of a semiconductor chip to be connected. And an adhesive layer adhered to the surface of the insulating film to cover the wiring so as to expose the tip of the bump, and the insulating film is located at the position of the bump. Are not removed, and via holes for forming external terminals are provided at positions other than the bump positions.
In that case, it is preferable that the insulating film is provided with an opening for exposing the adhesive at a position near the bump position and at a position where the wiring is not exposed. . Further, it is preferable that plating is applied to the exposed tip portion of the bump and the wiring portion exposed in the via hole.

According to another aspect of the present invention, there is provided a wiring material for a semiconductor device, wherein the wiring material is laid on a surface of the insulating film, and the surface of the insulating film is covered with the wiring to cover the wiring. An opening is provided at a position corresponding to the electrode of the semiconductor chip to be attached and connected and an adhesive layer exposing the wiring is mainly constituted, and the insulating film is located at the position of the opening. The via holes for forming the external terminals are not removed and are provided at positions other than the positions of the openings. In that case, it is preferable that the wiring portion exposed in the opening and the wiring portion exposed in the via hole be plated.

In each of the above wiring materials for semiconductor devices, the thickness of the insulating film is 12 to 75 μm.
It is preferred that Further, when the semiconductor wiring material and the semiconductor chip are joined by a bump bonding method, a highly reliable and low-cost semiconductor device can be obtained.

In order to achieve the above object, a method of manufacturing a wiring material for a semiconductor device according to the present invention comprises the steps of: providing an etching resist layer on one surface of an insulating film having metal foils provided on both sides; A step of forming a resist pattern for forming a bump by exposing and developing a mask for forming a bump in close contact with the surface thereof, forming a bump by half-etching the exposed metal foil portion, After providing an etching resist layer again on the surface of the formed metal foil, closely contacting a mask having a wiring pattern on the surface thereof, exposing and developing to form an etching pattern for forming a wiring, Forming a wiring portion by etching a portion to remove and remove the remaining portion of the etching resist layer; and a surface on the side where the wiring portion is formed. Forming an adhesive layer and curing; exposing the bump tip by etching the entire surface of the adhesive layer to reduce the thickness of the adhesive layer; and After providing an etching resist layer on the other side, a mask for forming via holes for forming external terminals on the surface is closely contacted, exposed and developed to form a resist pattern for via holes for forming external terminals, Forming a metal mask pattern for etching an insulating film by etching the exposed portion of the metal foil and removing and removing an etching resist layer remaining on the surface thereof; and A step of forming a via hole for forming a terminal and a step of removing a remaining metal mask by etching are included. In this case, after the step of removing the remaining metal mask by etching, it is preferable to add a step of plating the exposed tip portion of the bump and the wiring portion exposed in the via hole.

Further, another method of manufacturing a wiring material for a semiconductor device according to the present invention, which can achieve the above object, comprises providing an etching resist layer on one surface of an insulating film provided with a metal foil on both surfaces. Forming a resist pattern for forming a wiring by exposing and developing a mask for forming a wiring on the surface thereof, and etching the exposed portion of the metal foil to form a remaining portion of the etching resist layer. Peeling and removing to form a wiring portion;
A step of forming an adhesive layer on the surface on the side where the wiring portion is formed and curing, and after providing an etching resist layer on the surface of the adhesive layer, bringing a mask for forming an opening into close contact with the surface. Exposing and developing to form a resist pattern for forming an opening at a position corresponding to the electrode portion of the semiconductor chip, and etching the exposed portion of the adhesive layer to leave the etching resist layer A step of forming an opening in the adhesive layer by peeling and removing a portion, and a mask for forming via holes for forming external terminals on the surface after providing an etching resist layer on the other side of the insulating film Contacting, exposing and developing to form a resist pattern for via holes for forming external terminals, and etching the exposed portions of the metal foil to remain on the surface thereof A step of forming a metal mask pattern for insulating film etching by peeling and removing the etching resist layer; a step of forming via holes for forming external terminals by etching the insulating film; and etching the remaining metal mask by etching. And a removing step. In this case, after the step of removing the remaining metal mask by etching, a step of plating the wiring portion exposed in the opening and the wiring portion exposed in the via hole is added. It is suitable.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a method for manufacturing a semiconductor device by bonding a semiconductor chip and a wiring material by a bump bonding method, wherein a bump formed on one of the semiconductor chip and the wiring material and a bump formed on the other are used. A predetermined load and energy are applied from the wiring material side to the joint portion formed with the electrode portion from the wiring material side with the insulating film interposed therebetween. Thereby, it is possible to obtain a suitably bonded semiconductor device. The reason why this has become possible has not been elucidated in detail, but mainly because the bump itself has been miniaturized to reduce the size of the semiconductor device, and the area for applying the bonding energy has been reduced. Even if a large amount of energy is applied to the joint via the insulating film,
This is probably because the semiconductor chip is no longer damaged.

Then, when the conditions were changed and examined, it was found that bump bonding can be suitably performed only when the temperature is in the range of 250 to 250.
It was found that the temperature was 310 ° C., the load was 100 to 220 gf / bump, and the ultrasonic output was 0.8 to 2.5 W. Of course, bonding is possible even beyond this condition range, but when the thickness of the insulating film is reduced, there is a possibility that the semiconductor chip may be damaged,
Also, if the value falls below the above range, when the thickness of the insulating film becomes large, there is a possibility that a bonding failure may occur. Further, the thickness of the insulating film capable of performing bump bonding most reliably under the above conditions is 12 to 75 μm.
It turned out to be. If the thickness is smaller than this range, the semiconductor chip may be damaged. If the thickness is larger than this range, the possibility of causing a bonding failure increases.

Tables 1 to 3 below show some of the experimental results when a polyimide film having a thickness of 30 μm was used as the insulating film. From these results, it can be understood that excellent bonding results can be obtained when the above conditions are satisfied. In each table,
◎ indicates that all bumps are completely joined,
○ indicates a state where it can be determined that there is actually no problem even if it is not perfect, × indicates a state where there is a problem in use or bonding is incomplete, and Δ indicates that the semiconductor chip has been damaged. Is shown.

Table 1 shows that the wiring material having the structure shown in FIG. 1A was used, the temperature was 250 ° C., the bonding time was 50 msec, the load was 60 to 260 gf / bump, and the ultrasonic output was 0.1 to 3.0.
This shows the result of joining the semiconductor chip and the wiring material under the condition of 0 W, then peeling them off and observing the joined state. [Table 1] Output load (gf / bump) (W) 60 100 140 180 220 220 260 0.1 × × × × × ◆ 0.5 × × × ○ ○ ◆ 0.8 × ○ ○ ○ ◎ ◎ ◆ 1 2.5 × ◎ ◎ ◎ ◆ 2.5 ○ ◎ ◎ ◎ ◎ ◆ 2.8 ○ ◆ ◆ ◆ ◆ ◆ 3.0 ◆ ◆ ◆ ◆ ◆ ◆ ◆

Table 2 shows the results obtained under the same conditions as in Table 1 except that the temperature was set at 320 ° C., and the bonding state was confirmed. [Table 2] Output load (gf / bump) (W) 60 100 140 180 220 220 260 0.1 × × × × × ◆ 0.5 × × ○ ○ ◎ ◎ ◆ 0.8 × ◎ ◎ ◎ ◎ ◆ 1 2.5 × ◎ ◎ ◎ ◆ 2.5 ○ ◎ ◎ ◎ ◎ ◆ 2.8 ○ ◆ ◆ ◆ ◆ ◆ 3.0 ◆ ◆ ◆ ◆ ◆ ◆ ◆

Table 3 shows the results obtained under the same conditions as in Table 1 except that the temperature was 220 ° C., and the bonding state was confirmed. [Table 3] Output load (gf / bump) (W) 60 100 140 180 220 220 260 0.1 × × × × × ◆ 0.5 × × × × × ◆ 0.8 × × × × × × ◆ ◆ 1 2.5 × × × × ○ ◆ 2.5 × × ○ ○ ○ ◆ 2.8 × ◆ ◆ ◆ ◆ ◆ 3.0 ◆ ◆ ◆ ◆ ◆ ◆ ◆

The structure of the wiring material according to the present invention is as follows:
Two modes are adopted depending on whether the bump is provided on the wiring material side or the semiconductor chip side. Therefore,
First, an embodiment in which bumps are provided on the wiring material side is shown in FIG.
Will be described. The wiring material of this embodiment is mainly composed of a polyimide film having wiring on one surface and an adhesive layer covering the wiring portion, and a part of the wiring portion includes a semiconductor chip. A bump is provided at a position corresponding to the electrode part, and its tip protrudes from the adhesive layer. In addition, although via holes for forming external terminals are formed in the polyimide film, openings for bonding tools are not formed as in the conventional example shown in FIG. The wiring exposed on the bottom surface of the via hole and the exposed portions of the bumps are plated.

FIG. 1B shows an embodiment in which bumps are provided on the semiconductor chip side. The wiring material of this embodiment is mainly similar to the embodiment shown in FIG.
It consists of a polyimide film with wiring on one side and an adhesive layer that covers the wiring part,
No bump is provided in the wiring portion. Instead, an opening is provided in the adhesive layer at a position corresponding to the bump provided in the semiconductor chip, and the wiring portion exposed there is provided. Are electrode portions for bonding to the bumps. Also in this embodiment, the polyimide film has via holes for forming external terminals, but does not have openings for bonding tools. The wiring exposed at the bottom of the via hole and the wiring exposed at the opening of the adhesive are plated. However, it is not always necessary to apply this plating, and this is the same in the case of the embodiment shown in FIG.

Further, in any of the above two embodiments, when bump bonding is performed, stress is generated by crushing the bump and the adhesive, which may damage the semiconductor chip. An aspect capable of reducing such damage is shown in FIG. That is, the embodiment shown in FIG. 1C is a modification of the embodiment shown in FIG.
In the polyimide film, besides via holes for forming external terminals, near the contact position of the bonding tool,
That is, the opening is formed near the bump.
Therefore, the adhesive crushed during the bump bonding can escape into the opening, thereby reducing stress. Such an opening can be formed simultaneously with the formation of the via hole for forming the external terminal.
It can be formed also in the embodiment shown in FIG.

As described above, in the case of the wiring material of the present invention, in order to apply a load and an ultrasonic wave by the bonding tool, it is necessary to provide the opening for the bonding tool in the insulating film as in the related art. Absent. Further, thereby, the wiring portion near the junction is not exposed to the surrounding environment, so that a highly reliable semiconductor device can be obtained. Further, by adopting the embodiment shown in FIGS. 1A and 1B, it is possible to use an adhesive which does not have resistance to an etching solution for an insulating film. As the material of the insulating film that can be used in the present invention, there are various materials such as polyethylene, polyacrylamide, and polybiphenyl, in addition to the above-mentioned polyimide.

The wiring material of the present invention having such a structure is basically manufactured by the same method as the conventional wiring material, except that a bonding tool is used when etching the insulating film. This is to ensure that the part to be contacted is left. Therefore, next, a brief description will be given of a method of manufacturing the wiring material of the embodiment shown in FIG.

First, FIG. 2A shows FIG.
The same state as (e) is shown. Therefore, the steps up to this point are exactly the same as those of the above-described conventional example.
After that, an etching resist layer is formed again on both sides, and a mask having a pattern of via holes for forming external terminals is brought into close contact with the surface of the etching resist layer on the side opposite to the wiring side, and is exposed and developed. Then, the copper foil portion is etched, the etching resist remaining on the surface is peeled and removed, and a copper mask pattern for etching the polyimide film is formed (FIG. 2).
(B)).

Next, the exposed polyimide film is treated with an etching solution for polyimide to form via holes for forming external terminals. After that, the wiring exposed at the bottom of the via hole for external terminal formation is protected with resist,
The remaining copper mask is removed by etching (FIG. 2C).
reference). Then, by removing the etching resist on the surface on the bump formation side and the resist on the bottom of the via hole for external terminal formation, and finally plating the copper surface and the bump surface on the bottom surface of the via hole for external terminal formation by gold plating,
The wiring material is completed (see FIG. 2D).

Next, steps from bump bonding of the wiring material manufactured as described above to a semiconductor chip to forming a semiconductor device will be described with reference to FIG. First, FIG.
As shown in (a), the semiconductor chip and the wiring material are overlapped, and the electrode portion of the semiconductor chip and the bump are aligned. Next, the semiconductor chip is placed on a heating stage with the semiconductor chip facing down, and is heated at a predetermined temperature, so that the semiconductor chip and the wiring material can be bonded with an adhesive. Thereafter, the bonding tool is pressed against the polyimide film so that a predetermined load can be obtained from above the bump position, and a predetermined output ultrasonic wave is applied (FIG. 3).
(B)). Thereby, the electrode portion of the semiconductor chip and the bump are securely joined.

Finally, external terminals (solder bumps) are formed in the via holes for forming external terminals of the polyimide film, thereby completing the manufacture of the semiconductor device (see FIG. 3C). Accordingly, the semiconductor device manufactured in this manner has extremely high insulation reliability because the wiring is not exposed unlike the conventional example. In addition, since an inexpensive adhesive can be used without using a special adhesive, it is very advantageous in terms of cost.

[0034]

Next, the production of the above-mentioned wiring material and the production of a semiconductor device using the wiring material will be described in detail with reference to six examples and two comparative examples. Each of these was an actual attempt to manufacture, and each wiring material was manufactured using a double-sided Nippon Steel Chemical Co., Ltd. consisting of three layers of copper foil, polyimide film, and copper foil. A copper clad laminate material (product name: ESPANEX) was used. For forming the adhesive layer, a thermoplastic polyimide adhesive film (thickness: 30 μm) manufactured by Nippon Steel Corporation was used. This thermoplastic polyimide adhesive is of a type that dissolves in a polyimide etching solution. Further, as a semiconductor chip to be joined to the wiring material, a silicon chip having an electrode portion made of aluminum having a thickness of 1 μm, a size of 13 × 7.5 mm, and a thickness of 450 μm was used. Further, the bonding between the wiring material and the semiconductor chip was performed by a single point bonding method in which bumps were bonded one by one using a wire bonder FB-118A (trade name) manufactured by Kaijo.

Example 1 (1) Production of Wiring Material In this example, a double-sided copper-clad laminate material having a copper foil thickness of 35 μm and a polyimide film thickness of 50 μm was used. Therefore, first, an intermediate product at the stage shown in FIG. 2A was manufactured by initially adopting the same processing steps as those in the related art. At this stage, the thickness of the copper wiring is 18 μm, 69 copper dumps having a diameter of 40 μm are formed thereon, and the copper wiring is further covered with an adhesive layer.

Next, a dry film type etching resist is laminated on the copper foil on the other side on which no bump is formed, exposed and developed, and then heated to a liquid temperature of 45 ° C. using an aqueous cupric chloride solution. Etch the copper foil to a diameter of 40
A copper mask pattern for polyimide etching was formed in which 74 0 μm openings were arranged at 750 μm intervals. Then, using a 5% aqueous solution of sodium hydroxide, the remaining resist was removed and removed at a liquid temperature of 50 ° C. This stage is the stage shown in FIG.

Then, the polyimide film side was immersed and etched in a non-hydrazine-based alkali type polyimide etching solution at a liquid temperature of 80 ° C. to form a via hole having a diameter of about 340 μm. Thereafter, the copper wiring exposed in the via hole was protected with a resist, and the remaining copper mask was removed by etching. This stage is the stage shown in FIG. By removing the resist protecting the inside of the via hole and applying 1 μm thick gold plating to the surface of the copper wiring and the surface of the bump exposed therefrom, the state shown in FIG. Wiring material was obtained.

Then, when the adhesive surface and the via hole of the wiring material manufactured in the above process were observed using a microscope of 40 times magnification, no portion where the adhesive layer was etched was found, and Also, the via hole formation state was very good.

(2) Fabrication of Semiconductor Device First, as shown in FIG. 3A, the positions of the electrode portions of the semiconductor chip and the bumps of the wiring material are aligned, and the temperature is reduced to 3 °.
The temperature and temperature were adjusted to 00 ° C., the load was set to 10 kgf / cm ² , and thermocompression bonding was performed for 30 seconds to bond the two. Next, as shown in FIG. 3B, the semiconductor chip was placed on the stage heated to 280 ° C.,
gf / bump, 50 msec under the condition of 1.5 W ultrasonic output
During c, a bonding tool was pressed from above the polyimide film to perform bump bonding.

Then, a solder ball having a diameter of 400 μm is mounted in a via hole for forming an external terminal provided in the polyimide film, and is heated and joined to a copper wiring to form an external terminal as shown in FIG. Terminals were formed.
Therefore, 100 semiconductor devices manufactured in such a process were 100% inspected. As a result, it was confirmed that a good bonding state was observed for all of them and that no disconnection or short-circuit failure occurred.

Example 2 (1) Production of Wiring Material In this example, a double-sided copper-clad laminate material having a copper foil thickness of 35 μm and a polyimide film thickness of 75 μm was used. A wiring material was manufactured in the same manner as in Example 1 described above. Then, when the adhesive surface and the via hole of the manufactured wiring material were observed using a microscope of 40 times magnification, no portion where the adhesive layer was etched was observed, and a good via hole was formed. did it.

(2) Manufacture of Semiconductor Device The bonding conditions of the electrode portion of the semiconductor chip and the bump of the wiring material were as follows except that the temperature was 300 ° C., the load was 220 gf / bump, the ultrasonic output was 2.5 W, and the time was 50 msec. In the same manner as in Example 1, 100 semiconductor devices were manufactured. Then, when all the manufactured semiconductor devices were inspected, a good bonding state was confirmed in all the devices,
It was also confirmed that no disconnection or short-circuit failure occurred.

Example 3 (1) Production of Wiring Material In this example, a double-sided copper-clad laminated material having a thickness of each copper foil of 35 μm and a thickness of a polyimide film of 25 μm was used. A wiring material was manufactured in the same manner as in Example 1 described above. Then, when the adhesive surface and the via hole of the manufactured wiring material were observed using a microscope of 40 times magnification, no portion where the adhesive layer was etched was observed, and a good via hole was formed. did it.

(2) Manufacture of Semiconductor Device The bonding conditions of the electrode portion of the semiconductor chip and the bump of the wiring material were as follows except that the temperature was 300 ° C., the load was 100 gf / bump, the output of ultrasonic wave was 1.0 W, and the time was 50 msec. In the same manner as in Example 1, 100 semiconductor devices were manufactured. Then, when all the manufactured semiconductor devices were inspected, a good bonding state was confirmed in all the devices,
It was also confirmed that no disconnection or short-circuit failure occurred.

Example 4 (1) Production of Wiring Material In this example, a double-sided copper-clad laminated material having a copper film thickness of 35 μm and a polyimide film thickness of 12 μm was used. A wiring material was manufactured in the same manner as in Example 1 described above. Then, when the adhesive surface and the via hole of the manufactured wiring material were observed using a microscope of 40 times magnification, no portion where the adhesive layer was etched was observed, and a good via hole was formed. did it.

(2) Fabrication of Semiconductor Device The bonding conditions of the electrode portion of the semiconductor chip and the bump of the wiring material were as follows except that the temperature was 280 ° C., the load was 100 gf / bump, the ultrasonic output was 0.8 W, and the time was 50 msec. In the same manner as in Example 1, 100 semiconductor devices were manufactured. Then, when all the manufactured semiconductor devices were inspected, a good bonding state was confirmed in all the devices,
It was also confirmed that no disconnection or short-circuit failure occurred.

Fifth Embodiment (1) Production of Wiring Material This embodiment is an example in which a wiring material of the type shown in FIG. 1B is produced. Therefore, the steps were slightly different from those of the above-described embodiments, and were performed in the steps already described. However, various processing conditions were performed in accordance with the above-described first embodiment. When the surface of the adhesive and the via hole of the wiring material manufactured in this manner were observed using a microscope with a magnification of 40 times, no portion where the adhesive layer was etched was observed at all. Via holes were formed.

(2) Manufacture of Semiconductor Device In the case of this embodiment, a silicon chip provided with gold bumps on the surface of an aluminum electrode was employed as a semiconductor chip. 100 conductor devices were manufactured according to the case of (1). When all of them were inspected, it was confirmed that in all of them, a good joining state was confirmed, and that no disconnection or short-circuit failure occurred.

Embodiment 6 (1) Production of Wiring Material This embodiment is an embodiment in which a wiring material of the type shown in FIG. In addition to the external terminal forming via hole, the opening provided in the polyimide film had a diameter of 50 μm. In addition, the manufacturing process was performed in the steps already described, and various processing conditions were performed according to the above-described first embodiment. Then, the adhesive surface of the wiring material thus manufactured and the via hole are connected to each other by 4
Observation using a microscope of 0 magnification revealed that no portions where the adhesive layer was etched were observed and good via holes could be formed.

(2) Manufacture of Semiconductor Device In the case of this embodiment, 100 conductor devices were manufactured according to the case of the first embodiment. Then, when a 100% inspection was performed, it was confirmed that a good bonding state was confirmed in all the products, and that no disconnection or short-circuit failure occurred.

Comparative Example 1 (1) Production of Wiring Material This comparative example uses a double-sided copper-clad laminate material in which each copper foil has a thickness of 35 μm and a polyimide film has a thickness of 10 μm. A wiring material was manufactured in the same manner as in Example 1 described above. Then, when the adhesive surface and the via hole of the manufactured wiring material were observed using a microscope of 40 times, no portion where the adhesive layer was etched was observed.
In addition, good via holes could be formed.

(2) Fabrication of Semiconductor Device Next, the bonding conditions between the electrode portion of the semiconductor chip and the bump of the wiring material were as follows: temperature 280 ° C., load 100 gf / bump, ultrasonic output 1.0 W, time 50 msec. Manufactured 100 semiconductor devices in the same manner as in Example 1 described above. When all the manufactured semiconductor devices were inspected, it was found that a conduction failure occurred in some of them. Then, when examined in detail using a microscope, it was confirmed that the semiconductor chip had cracks.

[Comparative Example 2] (1) Production of Wiring Material In this comparative example, a double-sided copper-clad laminate material having a copper foil thickness of 35 μm and a polyimide film thickness of 100 μm was used. A wiring material was manufactured in the same manner as in Example 1 described above. When the adhesive surface and the via hole of the manufactured wiring material were observed using a microscope with a magnification of 40 times, no portion where the adhesive layer was etched was observed, and a good via hole could be formed. Was.

(2) Manufacture of Semiconductor Devices Then, 100 semiconductor devices were manufactured in the same manner as in Example 2 described above under the conditions for joining the electrode portions of the semiconductor chip and the bumps of the wiring material. When all the manufactured semiconductor devices were inspected, it was found that some of them were broken. Therefore, upon detailed examination, it was confirmed that the cause was defective bonding between the electrode portion of the semiconductor chip and the bump of the wiring material.

[0055]

As described above, according to the present invention, when the bonding tool is applied to the wiring material side by the bump bonding method and the semiconductor chip and the wiring material are bonded, the insulation is provided between the bonding tool and the bonding portion. Insulation reliability of the resulting semiconductor device is significantly higher than before because of the presence of the conductive film, and there is no need to use special adhesives when manufacturing wiring materials. Thus, an inexpensive wiring material can be obtained, and as a result, the manufacturing cost of the semiconductor device can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of a wiring material for a semiconductor device according to the present invention, wherein FIG. 1A shows a first embodiment,
FIG. 1B shows a second embodiment, and FIG. 1C shows a modification of the first embodiment.

FIGS. 2A to 2D are views for explaining a method of manufacturing the wiring material for a semiconductor device shown in FIG. 1A;
It is sectional drawing shown in order of process.

3 (a) to 3 (c) are steps for explaining a method of manufacturing a semiconductor device by bonding the semiconductor device wiring material and the semiconductor chip shown in FIG. 1 (a). It is sectional drawing shown in order.

FIG. 4 is a cross-sectional view showing a conventional wiring material for a semiconductor device.

5 (a) to 5 (h) are views for explaining a method of manufacturing the conventional wiring material for a semiconductor device shown in FIG. 4;
It is sectional drawing shown in order of process.

6 (a) to 6 (c) are shown in the order of steps to explain a method of manufacturing a semiconductor device by bonding the semiconductor device wiring material and the semiconductor chip shown in FIG. 4; It is sectional drawing.

Claims (14)

[Claims] When a semiconductor chip and a wiring material are bump-bonded, a predetermined load is applied to the bump bonding portion from the insulating film side with an insulating film interposed between the back surface of the bonding portion on the wiring material side. A method for manufacturing a semiconductor device, wherein energy required for the semiconductor device is applied. 2. The method according to claim 1, wherein the energy is ultrasonic energy, the bonding temperature is 250 to 310.degree.
2. The method for manufacturing a semiconductor device according to claim 1, wherein 220 gf / bump and an ultrasonic output are set to 0.8 to 2.5 W. 3. The thickness of the insulating film is 12 to 75.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness is set to μm. 4. An insulating film having a wiring provided with a bump provided at a position corresponding to an electrode of a semiconductor chip to be connected, and an insulating film for covering the wiring so as to expose a tip of the bump. And an adhesive layer adhered to the surface of the insulating film. The insulating film is not removed at the position of the bump, and the external terminal forming via is provided at a position other than the position of the bump. A wiring material for a semiconductor device, comprising a hole. 5. An opening for exposing an adhesive is provided in the insulating film at a position near the bump position where the wiring is not exposed. The wiring material for a semiconductor device according to claim 4. 6. The wiring material for a semiconductor device according to claim 4, wherein a plating is applied to an exposed front end portion of the bump and a wiring portion exposed in the via hole. 7. An insulating film having a wiring laid on a surface thereof, and an opening at a position corresponding to an electrode of a semiconductor chip to be connected which is attached to a surface of the insulating film to cover the wiring. And the adhesive layer exposing the wiring, the insulating film is not removed at the position of the opening, and the external terminal forming via is provided at a position other than the position of the opening. A wiring material for a semiconductor device, comprising a hole. 8. The semiconductor device according to claim 7, wherein the wiring portion exposed in the opening and the wiring portion exposed in the via hole are plated. Wiring material. 9. The insulating film has a thickness of 12-7.
The wiring material for a semiconductor device according to claim 4, wherein the thickness is 5 μm. 10. A semiconductor device, wherein the wiring material according to claim 4 and a semiconductor chip are bump-bonded. 11. A resist pattern for forming a bump by forming an etching resist layer on one surface of an insulating film having a metal foil provided on both sides, and then exposing and developing the surface by closely contacting a mask for forming a bump. Forming a bump by half-etching the exposed portion of the metal foil, and providing a wiring pattern on the surface after providing an etching resist layer again on the surface of the metal foil on which the bump is formed. A step of forming an etching pattern for wiring formation by exposing and developing the mask in close contact, and etching the exposed metal foil portion to peel and remove the remaining portion of the etching resist layer to remove the wiring portion; Forming, forming an adhesive layer on the surface on the side where the wiring portion is formed and curing, and etching the entire surface of the adhesive layer to perform the bonding. Exposing the tip of the bump by reducing the thickness of the layer, and providing an etching resist layer on the other side of the insulating film, and then forming a via hole for forming an external terminal on the surface thereof. Forming a resist pattern for an external terminal forming via hole by exposing and developing, and etching and exposing the exposed portion of the metal foil to remove and remove an etching resist layer remaining on the surface. Forming a metal mask pattern for etching an insulating film, forming a via hole for forming an external terminal by etching the insulating film, and removing the remaining metal mask by etching. A method of manufacturing a wiring material for a semiconductor device. 12. The method according to claim 1, further comprising, after the step of removing the remaining metal mask by etching, a step of plating the exposed tip portion of the bump and the wiring portion exposed in the via hole. The method of manufacturing a wiring material for a semiconductor device according to claim 11. 13. A resist pattern for forming a wiring pattern by providing an etching resist layer on one surface of an insulating film having metal foils on both sides and then exposing and developing a mask for forming a wiring on the surface. Forming a wiring portion by etching the exposed portion of the metal foil and peeling and removing the remaining portion of the etching resist layer; and forming a wiring portion on the surface on the side where the wiring portion is formed. A step of forming an adhesive layer and curing, and after providing an etching resist layer on the surface of the adhesive layer, a mask for forming an opening is brought into close contact with the surface and exposed and developed to form an electrode portion of the semiconductor chip. A step of forming a resist pattern for forming an opening at a corresponding position, etching the exposed portion of the adhesive layer, and peeling and removing the remaining portion of the etching resist layer Step of forming an opening in the adhesive layer, and after providing an etching resist layer on the other side of the insulating film, closely contacting a mask for forming via holes for forming external terminals on the surface thereof, and exposing and developing the mask. Forming a resist pattern for a via hole for forming an external terminal by etching the exposed portion of the metal foil to remove and remove an etching resist layer remaining on the surface of the exposed portion of the metal foil. Forming a metal mask pattern, etching the insulating film to form via holes for forming external terminals, and removing the remaining metal mask by etching. A method for manufacturing a wiring material for a semiconductor device. 14. After the step of removing the remaining metal mask by etching, a wiring portion exposed in the opening and a wiring portion exposed in the via hole are formed.
14. A plating step is provided.
3. The method for producing a wiring material for a semiconductor device according to claim 1.