JP2000332738A - Data transfer unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely detect wrong synchronization due to a phase change in a frame with a synchronization bit added thereto. SOLUTION: This data transfer unit consists of a frame transmitter 1 that stores data outputted from a data generator 27, inserts a phase change detection pattern to the stored data at a rate of once per m-frames (m is a natural number), applies coding processing to the data to which the phase change detection pattern is inserted for each frame, adds a synchronization bit to each frame and provide the output of the resulting frame and of a frame receiver 2, that detects the synchronization bit from the frame outputted from the frame transmitter 1, extracts data from the frame outputted from the frame transmitter 1 when the synchronization bit is detected, provides an output of the extracted data, detects phase change detection pattern from the frame outputted from the frame transmitter 1 at a rate of one per m-frames and stops extraction of the data, on the basis of the detected phase change detection pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device for transferring data to which a synchronization bit is added for each frame, and more particularly to a data transfer device capable of detecting erroneous synchronization due to a change in the phase of a frame.

[0002]

2. Description of the Related Art Conventionally, when transmitting serial data at high speed, data transfer is performed using an optical transmission line such as an optical fiber. In a data transfer apparatus in which such data transfer is performed, in general, a specific pattern is defined as a synchronization bit in order to prevent erroneous synchronization, and data for transfer is scrambled by a specific polynomial. The configuration is such that the same pattern as the synchronization bit does not appear on the data for transfer.

However, in a data transfer apparatus in which scramble processing is performed on transfer data,
There is a problem that it takes time for the scramble process and a problem that the scale of the system becomes large. For this reason, recent data transfer apparatuses are required to prevent erroneous synchronization without performing scrambling processing.
No. 191306. According to this,
Transmit the data with the synchronization bit added for each frame,
Detect the synchronization bit in the receiving device that receives the frame,
This is configured to prevent erroneous synchronization.

FIG. 8 is a diagram showing a configuration example of a receiving device used in a conventional data transfer device.

As shown in FIG. 8, this configuration example detects a synchronization bit included in a received frame 51, and outputs a synchronization establishment signal 48 when the synchronization bit is detected, and a synchronization detection unit 32. When the synchronization establishment signal 48 output from the frame 32 is input, the arithmetic processing of the data included in the frame 51 is started, and the frame data arithmetic unit 31 for outputting the result of the arithmetic processing as the arithmetic result 53;
When the synchronization establishment signal 48 output from is input, the monitoring of the synchronization bits included in the frame 51 is started, and when the alternation of the monitored synchronization bits and the 0, 1 pattern are normal, the synchronization detection unit 32 and the frame data And a synchronization monitoring unit 33 that outputs a synchronization monitoring signal 52 to the calculation unit 31. When the synchronization monitoring signal 52 is input, the frame data calculation unit 31 The arithmetic processing is performed, and the detection of the synchronization bit included in the frame 51 is stopped in the synchronization detection unit 32 when the synchronization monitoring signal 52 is input.

The frame 51 has a synchronization bit added to data for each frame.

[0007] The operation of the receiving apparatus configured as described above will be described below.

When the synchronization detecting section 32 detects a synchronization bit included in the received frame 51, a synchronization establishing signal 48 is output to the frame data calculating section 31 and the synchronization monitoring section 33. The detection of the synchronization bit included in is stopped.

In the synchronization monitoring unit 33, the synchronization detection unit 3
When the synchronization establishment signal 48 output from the frame 2 is input, monitoring of the synchronization bits included in the frame 51 is started, and when the alternation of the monitored synchronization bits and the 0, 1 pattern are normal, the synchronization detection unit 32 And frame data operation unit 31
, A synchronization monitoring signal 52 is output.

[0010] In the frame data calculation section 31, when the synchronization establishment signal 48 output from the synchronization detection section 32 is input, the calculation processing of the data included in the frame 51 is started, and the data is output from the synchronization monitoring section 33. While the synchronization monitoring signal 52 is input, the arithmetic processing of the data included in the frame 51 is performed, and the result of the arithmetic processing is calculated as the arithmetic result 5.
It is output as 3.

Further, the synchronization monitor 33
As a result of monitoring the synchronization bit included in the frame 1, the frame 5
If the alternation of the synchronization bits included in 1 and the 0, 1 pattern are not normal, the output of the synchronization monitoring signal 52 to the synchronization detection unit 32 and the frame data calculation unit 31 is stopped.

When the output of the synchronization monitoring signal 52 from the synchronization monitoring unit 33 stops, the output of the synchronization establishment signal 48 stops in the synchronization detection unit 32, and the detection of the synchronization bit included in the frame 51 is restarted. In the frame data calculation unit 31, the calculation processing of the data included in the frame 51 is stopped.

Hereinafter, the synchronization monitor 33 shown in FIG. 8 will be described in detail.

FIG. 9 is a block diagram showing an example of the configuration of the synchronization monitor 33 shown in FIG. As shown in FIG. 9, the present configuration example is based on the synchronization bit position storage unit 44 that stores the synchronization bit position information included in the synchronization establishment information 48, and the synchronization bit position information stored in the synchronization bit position storage unit 44. , A synchronization bit extraction unit 40 for extracting and outputting synchronization bits included in a frame 51, and a synchronization bit extraction unit 4
The alternation monitoring unit 41 monitors alternation of the synchronization bits output from 0, and outputs an alternation OK signal when the alternation of the monitored synchronization bits is different from the alternation of the synchronization bits one frame before.
Each time the synchronization bit output from the synchronization bit extraction unit 40 is input, the internal 1-bit counter counts up, and the count value of the 1-bit counter and the output from the synchronization bit extraction unit 40 are output. And a pattern monitoring unit 42 that outputs a pattern monitoring OK signal when both values match, and an alternation monitoring unit 4.
AND gate 43 that outputs a monitoring OK signal 55 when both the alternating OK signal output from 1 and the pattern monitoring OK signal output from the pattern monitoring unit 42 are input.
And the monitoring OK signal 55 output from the AND gate 43
A rear protection control unit 45 that performs rear protection control based on
A forward protection control unit that performs forward protection control based on the monitoring OK signal 55 output from the gate 43 and outputs a forward protection signal in the forward protection state;
6, an OR gate 47 for forcibly outputting the synchronization monitoring signal 52 when the forward protection signal is output, and an output of the synchronization monitoring signal 52 when the rear protection signal is output from the rear protection control unit 45. And an AND gate 54 for stopping.

The alternation monitoring section 41 internally stores a synchronization bit storage section (not shown) for holding and storing the synchronization bits output from the synchronization bit extracting section 40, and stores the synchronization bits in the synchronization bit storage section. And a comparator (not shown) that outputs an alternation OK signal when the alternation of the synchronization bit and the alternation of the synchronization bit output from the synchronization bit extracting unit 40 after one frame are different. I have.

The pattern monitor 42 includes a 1-bit counter (not shown) for counting from an initial value based on an initial value signal included in the synchronization establishment signal 48, and a synchronization bit included in the frame 51. And a comparator (not shown) for comparing the count value of the 1-bit counter with the count value and outputting a pattern monitoring OK signal when both are the same.

The synchronization establishing signal 48 provides an initial value signal for setting an initial value of a 1-bit counter provided in the pattern monitoring unit 42 and synchronization bit position information to the synchronization bit extracting unit 40. Bit position information.

The operation of the synchronization monitoring unit configured as described above will be described below.

When the synchronization establishment signal 48 is input, the synchronization bit position information contained in the synchronization establishment signal 48 is fetched and stored in the synchronization bit position storage section 44. The synchronization bit position storage unit 44 stores the synchronization bit position information included in the synchronization establishment signal 48 while the synchronization establishment signal 48 is being input.

Next, the synchronization bit extracting section 40 extracts synchronization bits included in the frame 51 based on the contents of the synchronization bit position information stored in the synchronization bit position storage section 44, and thereafter, extracts the synchronization bits from the frame 51. The extracted synchronization bit is used as an alternation monitoring unit 41 and a pattern monitoring unit 42.
Is output to

In the pattern monitoring section 42, a synchronization bit extracting section 4 is provided in a 1-bit counter provided therein.
The initial value of the synchronization bit output from 0 is the synchronization establishment signal 4
8, the count value is incremented each time a synchronization bit is input from the synchronization bit extracting unit 40. Further, the 1 The count value of the counter is compared with the value of the synchronization bit output from the synchronization bit extracting unit 40, and if they match, a pattern monitoring OK signal is output.

In the alternation monitoring section 41, the synchronization bit output from the synchronization bit extracting section 40 is stored in a storage section provided therein, and the storage section is provided in a comparator provided therein. Is compared with the alternation of the synchronization bits output from the synchronization bit extracting unit 40 after one frame, and if both are different, an alternation OK signal is output.

Next, when the alternation OK signal output from the alternation monitoring section 41 and the pattern monitoring OK signal output from the pattern monitoring section 42 are both input to the AND gate 43, a monitoring OK signal 55 is output. You.

Here, in the rear protection control section 45,
When the monitoring OK signal 55 is output from the AND gate 43 in the asynchronous state, the state is shifted to the rearward protection state, and the rearward protection control is performed to output the rearward protection signal.

In the backward protection state, during the number of frames exceeding the number of backward protection stages, the monitoring O
When the K signal 55 is output, the rear protection control unit 45 transitions to the synchronous state, stops the rear protection control operation, and stops outputting the rear protection signal.

When the output of the monitoring OK signal 55 from the AND gate 43 is stopped in the rear protection state, the rear protection controller 45 shifts to the asynchronous state and stops the rear protection control operation to stop the rear protection. Signal output stops.

In the forward protection control unit 46, when the output of the monitoring OK signal 55 from the AND gate 43 is stopped in the synchronous state, the forward protection state is changed.
Forward protection control is performed, and a forward protection signal is output.

In the forward protection state, during a frame exceeding the number of forward protection stages, the monitoring OK is output from the AND gate 43.
When the output of the signal 55 is stopped, in the front protection control unit 46, the state is shifted to an asynchronous state, the front protection control operation is stopped, and the output of the front protection signal is stopped.

When the monitor OK signal 55 is output from the AND gate 43 in the forward protection state, the forward protection control section 46 shifts to the synchronous state, stops the forward protection control operation, and outputs the forward protection signal. Output stops.

As a result, in the rear protection state, the rear protection signal is output from the rear protection control unit 45 and the front protection signal is not output from the front protection control unit 46.
The operation of the R gate 47 and the AND gate 54 stops the output of the synchronization monitoring signal 52.

In the front protection state, the rear protection signal is not output from the rear protection control unit 45 and the front protection signal is output from the front protection control unit 46, so that the OR gate 47 and the AND gate 54 operate. The synchronization monitoring signal 52 is forcibly output.

FIG. 10 is a diagram for explaining the operation of monitoring the synchronization bit by the synchronization monitoring unit shown in FIG. In FIG. 10, when a repetitive pattern of 1, 0, 0 is input as a synchronization bit, the pattern monitoring unit 42
, The monitoring result of the alternation monitoring unit 41, and the result of the comprehensive determination (synchronous monitoring) determined based on the monitoring results of the pattern monitoring unit 42 and the alternation monitoring unit 41, respectively. The 1-bit counter shown in FIG. 10 is a count value of a 1-bit counter provided in the pattern monitoring unit 42.

As shown in FIG. 10, after the repetition pattern of 1, 0, 0 is input as the synchronization bit, the alternation monitoring section 41 monitors the alternation of the synchronization bit. NG appears only in. In this case, if the synchronization monitoring signal 52 is protected in two stages, no erroneous synchronization is detected, and the frame data operation unit 31 remains erroneously synchronized.
(See FIG. 8), the frame data calculation is performed,
Incorrect data is output. However, as a result of monitoring the 0 and 1 patterns of the synchronization bit by the pattern monitoring unit 42, NG continues for three consecutive stages.
Until four steps of protection are applied to 2, a false synchronization is reliably detected.

[0034]

In a conventional data transfer device having a receiving device configured as described above,
The alternation monitoring of the synchronization bit added to the frame and the monitoring of the 0 and 1 patterns are simultaneously performed in the receiving device, so that even when the synchronization bit has a specific repetition pattern, erroneous synchronization is detected. It is configured.

However, when a phase change occurs in the frame, the synchronization bit extracted by the synchronization bit extraction unit may be judged to be normal by both the alternation monitoring unit and the pattern monitoring unit. For this reason, there is a problem that erroneous synchronization is not detected.

The present invention has been made in view of the above-described problems of the prior art, and is intended to be applied to the case where the detection of false synchronization by alternate monitoring of synchronization bits and monitoring of 0, 1 patterns is not effective. It is an object of the present invention to provide a data transfer device capable of reliably detecting erroneous synchronization due to a phase change of the data.

[0037]

In order to achieve the above object, the present invention provides a data generating device for generating and outputting data, and storing data output from the data generating device.
A frame transmitting apparatus that encodes the stored data for each frame and further transmits a frame by adding a synchronization bit; and detects a synchronization bit added to the frame transmitted from the frame transmission apparatus, and detects the synchronization bit. A synchronization monitoring unit that establishes synchronization and outputs a frame phase when is detected, and extracts data from a frame transmitted from the frame transmission device when the frame phase output from the synchronization monitoring unit is input. And a frame receiving device having a data extracting unit for outputting the data. The frame transmitting device stores the data output from the data generating device, and outputs m to the stored data. (M is a natural number) A phase change detection pattern is inserted once per frame, and data with the phase change detection pattern inserted is output. A phase change detection pattern insertion unit; and a frame generation unit that encodes data output from the phase change detection pattern insertion unit for each frame, and further adds a synchronization bit to transmit the frame. The monitoring unit detects a phase change detection pattern included in the frame transmitted from the frame generation unit at a rate of once in m frames, and detects erroneous synchronization based on the detected phase change detection pattern phase. The output of the phase is stopped.

Further, the phase change detection pattern insertion section includes:
A frame number counter that counts up for each frame and outputs the count value as a frame number;
A data storage unit that stores the input data for each frame and outputs the stored data based on the frame number, a pattern generation unit that generates and outputs a phase change detection pattern based on the frame number, A data selection unit that outputs one of a phase change detection pattern output from the pattern generation unit and data output from the data storage unit based on the frame number.

Further, the synchronization monitoring section detects the synchronization bit, establishes synchronization when the synchronization bit is detected, and outputs a frame phase, and outputs a frame phase to the frame transmitted from the frame generation section. The phase change detection pattern included is detected once every m frames, the phase of the detected phase change detection pattern is compared with the phase of the frame phase, and the phase change detection is detected when the two do not match. A pattern detection unit that outputs the phase of the pattern, and a pattern phase storage unit that stores the phase of the phase change detection pattern output from the pattern detection unit, wherein the pattern detection unit includes:
After receiving data of m frames, the phase stored in the pattern phase storage section is read out, and when a phase change detection pattern having a phase that matches the phase appears in the frame, a resynchronization command is issued to the synchronization detection section. And the synchronization detection unit stops outputting the frame phase when the resynchronization command is received.

Further, the pattern generator outputs an input data rejection signal to the data generator when the capacity for storing the data output from the data generator is insufficient. I do.

Further, the pattern generation section inserts a phase change detection pattern into all bits of a data portion of a frame output from the frame generation section. Further, the pattern generation unit inserts a phase change detection pattern into some bits of a data portion of a frame output from the frame generation unit.

(Operation) In the present invention configured as described above, the phase change detection pattern is inserted into the data portion of the frame once every m frames in the frame transmitting apparatus. The phase change detection pattern included in the frame is detected once per frame, and erroneous synchronization due to the phase change of the frame is detected based on the detected phase change detection pattern.

Therefore, even when monitoring the 0 and 1 patterns of the synchronization bit and the alternation, it is possible to reliably detect erroneous synchronization due to a change in the phase of the frame.

[0044]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the data transfer device of the present invention.

In this embodiment, as shown in FIG. 1, a data generating device 27 for generating and outputting data,
And stores the data 7 output from the
, A phase change detection pattern is inserted once every m (m is a natural number) frames, the data into which the phase change detection pattern has been inserted is encoded for each frame, and then a synchronization bit is generated for each frame. A frame transmitting device 1 that outputs the frame as an additional frame 9 and outputs an input data rejection signal 26 to a data generating device 27 when the free space for storing the data 7 is reduced.
And a synchronization bit is detected from the frame 9 output from the frame transmission device 1, and when the synchronization bit is detected, data 1 is detected from the frame 9 output from the frame transmission device 1.
0 is extracted and output, and a phase change detection pattern is detected from a frame 9 output from the frame transmission device 1 at a rate of once every m frames, and data 10 is extracted based on the detected phase change detection pattern. And a frame receiving device 2 to be stopped.

The frame transmitting apparatus 1 stores the data 7 output from the data generating apparatus 27, inserts a phase change detection pattern into the stored data 7 once every m frames, and outputs the data 8 Is output, and when the free space for storing the data 7 becomes smaller, the input data rejection signal 2
6, a phase change detection pattern insertion unit 3 that outputs 6 and encodes data 8 output from the phase change detection pattern insertion unit 3 for each frame, and adds a synchronization bit to the encoded data 8 And a frame generating unit 4 for outputting the frame as a frame 9.

When the frame receiving apparatus 2 is in an asynchronous state, it detects a synchronization bit included in the frame 9 and establishes synchronization.
And the phase change detection pattern included in the frame 9 is detected once every m frames, the phase change of the frame 9 is detected based on the detected phase change detection pattern, and the phase change of the frame 9 is detected. There is a synchronization monitoring unit 6 that stops outputting the frame phase 11 when it is detected, and a data extraction unit 5 that extracts data included in the frame 9 and outputs it as data 10 while the frame phase 11 is being input. are doing.

Hereinafter, the operation of the data transfer apparatus configured as described above will be described.

When the data 7 is output from the data generating device 27, the data 7 is stored in the phase change detection pattern insertion unit 3, and the phase change detection is performed on the stored data 7 once every m frames. The pattern is inserted and output as data 8. Note that the phase change detection pattern insertion unit 3 outputs an input data rejection signal 26 to the data generation device 27 when the free space for storing the data 7 is reduced. This is because the phase change detection pattern insertion unit 3 inserts the phase change detection pattern once every m frames, and the input data amount increases by one frame with respect to the output data amount. That's why.

Next, in the frame generating section 4, the data 8 is coded for each frame, and a synchronization bit is added to the coded data 8, whereby a frame 9 is generated and 2 is output.

Here, when the frame receiving apparatus 2 is in an asynchronous state with respect to the frame transmitting apparatus 1, the synchronization monitoring unit 6
, A synchronization bit included in the frame 9 is detected.

When the synchronization monitoring unit 6 detects a synchronization bit, the state of the frame reception device 2 with respect to the frame transmission device 1 changes to a synchronization state, and the synchronization monitoring unit 6 sends a frame phase to the data extraction unit 5. 11 is output.

Next, while the frame phase 11 is being input from the synchronization monitoring unit 6, data is extracted from the frame 9 in the data extraction unit 5, and the extracted data is output as data 10.

The synchronization monitoring unit 6 sends the frame phase 11
Is output, the synchronization monitoring unit 6 sets the phase change detection pattern included in frame 9 to 1 in m frames.
When the phase change of the frame 9 is detected based on the phase of the detected phase change detection pattern, the output of the frame phase 11 from the synchronization monitoring unit 6 stops. When the output of the frame phase 11 from the synchronization monitoring unit 6 stops, the data extraction unit 5 stops extracting data.

Hereinafter, the phase change detection pattern insertion unit 3 shown in FIG. 1 will be described in detail. FIG. 2 is a block diagram showing a configuration example of the phase change detection pattern insertion unit 3 shown in FIG.

In this configuration example, as shown in FIG. 2, a frame number counter 14 that counts up for each frame and outputs the count value as a frame number 18 and a data 7 output from the data generation device The data 7 is stored for each frame, and the data 7 stored based on the frame number 18 output from the frame number counter 14 is output as the data 16, and the data is generated when the free space for storing the data 7 is reduced. Device 2
7, a phase change detection pattern 1 based on the frame number 18 output from the frame number counter 14,
7, a pattern generation unit 13 for generating and outputting a frame number 7, a phase change detection pattern 17 output from the pattern generation unit 13 based on the frame number 18 output from the frame number counter 14, and data output from the data storage unit 12. 16
And a data selection unit 15 for outputting any one of them as data 8.

The range of the count value in the frame number counter 14 is in the range of 0 to (m-1).
When the count value reaches (m-1), the count value is returned to 0, and the count is restarted from 0.

The operation of the phase change detection pattern insertion unit configured as described above will be described below.

In the frame number counter 14, the count value is incremented each time data 7 is input for one frame, and the count value is used as the frame number 18 as the data storage unit 12, the pattern generation unit 13, and the data selection unit 15. Is output to The range of the count value is a range from 0 to (m-1), and the count value is (m
When -1) is reached, the value is returned to 0, and the count-up is performed again.

Next, when the data 7 is input to the data storage unit 12, the input data 7 is stored for each frame, and the frame number 18 output from the frame number counter 14 is changed from 1 to (m− If it is in the range of 1), the stored data 7 is output to the data selection unit 15 as the data 16, and if the frame number 18 is 0, the output of the data 16 is stopped. As described above, in the data storage unit 12, the input data amount per m frames is increased by one frame as compared with the output data amount. For this reason, the free space for storing the data 7 is reduced. In this case, the input data rejection signal 26 is output to the data generation device 27, and the output of the data 7 in the data generation device 27 is stopped.

In the pattern generation unit 13, the frame number 18 output from the frame number counter 14 is output.
Is 0, a phase change detection pattern 17 is generated and output to the data selection unit 15, and the frame number 18
Is in the range of 1 to (m-1), the output of the phase change detection pattern 17 stops.

Next, when the frame number 18 is 0 in the data selection unit 15, the phase change detection pattern 17 output from the pattern generation unit 13 is output as data 8, and the frame number 18 is changed from 1 to (m− In the range of 1), the data 16 output from the data storage unit 12 is output as data 8.

Hereinafter, the operation of the phase change detection pattern insertion unit shown in FIG. 2 will be described in more detail with reference to a flowchart.

FIG. 3 is a flowchart for explaining the operation of the phase change detection pattern insertion unit shown in FIG.

First, in the frame number counter 14, the count value is set to 0 and output as the frame number 18 (step A1).

Next, the data 7 is stored in the data storage section 12 (step A2). In the data storage unit 12, the data 7 is thereafter stored for each frame.

Next, the frame number counter 14 determines whether or not the frame number 18 is 0 (step A3). If the frame number 18 is determined to be 0, the pattern generation unit 13 causes the phase change detection pattern 17 to be determined. Is generated, the generated phase change detection pattern 17 is output to the data selection unit 15 (step A4), and if it is determined that the frame number 18 is not 0, the data storage unit 12 stores the stored data 7 Is output to the data selector 15 as data 16 (step A5).

In the data selecting section 15, step A
In step 3, when the frame number 18 output from the frame number counter 14 is determined to be 0, the phase change detection pattern 17 output from the pattern
When it is determined in step A3 that the frame number 18 is not 0, the data 16 output from the data storage unit 12 is output as data 8 (step A6).

Next, in the frame number counter 14, the count value is counted up, and the counted value is output as the frame number 18 (step A7).

Next, the frame number counter 14 determines whether or not the frame number 18 is m (step A8). If the frame number 18 is determined to be m, the count value is returned to 0 and returned to 0. The counted value is output as the frame number 18 (step A9).
It returns to the process in step A2.

On the other hand, if it is determined in step A8 that the frame number 18 is not m, the process returns to step A2.

Hereinafter, the synchronization monitoring section 6 shown in FIG. 1 will be described in detail.

FIG. 4 is a block diagram showing an example of the configuration of the synchronization monitoring section 6 shown in FIG.

In this configuration example, as shown in FIG. 4, when the frame receiving apparatus 2 is in an asynchronous state with respect to the frame transmitting apparatus 1, the synchronization bit included in the frame 9 is detected. 11, and thereafter, stops the detection of the synchronization bit, and monitors the synchronization bit included in the frame 9 when the frame reception device 2 is in synchronization with the frame transmission device 1. When the frame receiving apparatus 2 is in synchronization with the frame transmitting apparatus 1, the phase change detection pattern included in the frame 9 is detected once every m frames, and the phase of the detected phase change detection pattern is The phase of the phase change detection pattern is compared with the phase of the frame phase 11 output from the synchronization detection unit 19, and when the two do not match, the phase of the phase change detection pattern is detected. 3 and then a pattern detection unit 20 that stops detection of the phase change detection pattern included in the frame 9 and a pattern phase storage unit 21 that stores the phase 23 output from the pattern detection unit 20 as the phase 24. In the pattern detection unit 20, m
After the frame, the phase 24 stored in the pattern phase storage unit 21 is read out, the phase change detection pattern included in the frame 9 is detected again, and the phase of the detected phase change detection pattern and the pattern phase storage are stored. The phase 24 read from the unit 21 is compared, and when they match, a resynchronization command 25 is output to the synchronization detection unit 19,
As a result, the output of the frame phase 11 from the synchronization detector 19 stops.

Note that the frame phase 11 defines the phase of the synchronization bit included in the frame 9 and has a phase when the phase of the synchronization bit is correct.

Hereinafter, the operation of the synchronization monitoring unit configured as described above will be described.

In the synchronization detecting section 19, when the frame receiving apparatus 2 is in an asynchronous state with respect to the frame transmitting apparatus 1, the synchronization bit included in the frame 9 is detected. The state of the apparatus 2 with respect to the frame transmitting apparatus 1 changes from the asynchronous state to the synchronous state, whereby the frame phase 11 defining the phase of the synchronous bit is output, and thereafter, the detection of the synchronous bit included in the frame 9 stops.

Note that, even after the detection of the synchronization bit is stopped, the synchronization detection unit 19 determines whether the synchronization bit included in the frame 9 appears normally in the phase of the synchronization bit of the frame phase 11. The 0, 1 pattern monitoring and the alternation monitoring of the included synchronization bits are performed. Such monitoring is called a synchronization bit monitoring operation. Here, when the synchronization bit included in the frame 9 is not normal, the state of the frame receiving apparatus 2 with respect to the frame transmitting apparatus 1 is changed from the synchronous state to the asynchronous state, and the frame phase 11
Is stopped, and then detection of the synchronization bit included in the frame 9 is started.

When the frame receiving device 2 is in synchronization with the frame transmitting device 1, the pattern detecting section 20 detects the phase change detecting pattern included in the frame 9, and the phase change detecting pattern is detected. When detected,
Phase of detected phase change detection pattern and frame phase 1
One phase is compared. Here, when the pattern detection unit 20 determines that the phases of the two do not match,
The detected phase of the phase change detection pattern is output to the pattern phase storage unit 21 as the phase 23, and the operation of detecting the phase change detection pattern stops.

Next, in the pattern phase storage section 21, the phase 23 output from the pattern detection section 20 is stored as a phase 24.

After m frames, the pattern detector 20 reads the phase 24 stored in the pattern phase storage 21 and determines whether a phase change detection pattern having the same phase as the phase 24 appears in the frame 9. Monitoring is performed. If a phase change detection pattern having the same phase as the phase 24 appears in the frame 9, the pattern detection unit 20 determines that a phase change has occurred in the frame 9, and outputs a resynchronization command 25 to the synchronization detection unit 19. Is done.

When the resynchronization command 25 is output from the pattern detection section 20, the state of the frame reception apparatus 2 with respect to the frame transmission apparatus 1 changes from the synchronous state to the asynchronous state in the synchronization detection section 19, and the output of the frame phase 11 Stops, and the detection of the synchronization bit included in the frame 9 is restarted.

Hereinafter, the operation of the synchronization monitoring unit shown in FIG. 4 will be described in more detail with reference to a flowchart.

FIG. 5 is a flowchart for explaining the operation of the synchronization monitor shown in FIG.

First, the state of the frame receiving apparatus 2 is set to an asynchronous state with respect to the frame transmitting apparatus 1 (step S1), and the output of the frame phase 11 is stopped in the synchronization detecting section 19 (step S2). The pattern detection unit 20 stops detecting the phase change detection pattern included in the frame 9 (step S3).

Then, the synchronization detector 19 starts detecting the synchronization bit included in the frame 9 (step S4), and thereafter, determines whether or not synchronization has been established (step S5).

When the synchronization is established at step S5, the frame phase 11 is output from the synchronization detector 19 (step S6), and the detection of the synchronization bits included in the frame 9 is stopped (step S7). Monitoring of the synchronization bits included in the frame 9 is started (step S8), and detection of the phase change detection pattern included in the frame 9 is started in the pattern detection unit 20 (step S8).
9).

On the other hand, in step S5, the frame 9
If no synchronization bit is detected in step S
Returning to the process in 4, the detection of the synchronization bit included in the frame 9 is performed again.

Next, the pattern detection section 20 determines whether or not a phase change detection pattern included in the frame 9 has been detected (step S10). If the phase change detection pattern has been detected, the detected phase change detection pattern is detected. Is compared with the phase of the frame phase 11 (step S
11).

On the other hand, if the phase change detection pattern included in frame 9 is not detected in step S10,
Returning to the processing in step S9, the detection of the phase change detection pattern included in the frame 9 is performed again.

Next, the pattern detection unit 20 determines the comparison result between the phase of the phase change detection pattern and the phase of the frame phase 11 (step S12), and when it is determined that the two do not match, it is detected. The phase of the phase change detection pattern is output to the pattern phase storage unit 21 as the phase 23 (Step S13).

Next, in the pattern phase storage section 21, the phase 23 output from the pattern detection section 20 is stored as a phase 24 (step S14).

On the other hand, if it is determined in step S12 that the phase of the phase change detection pattern detected by the pattern detection section 20 matches the phase of the frame phase 11,
Returning to the processing in step S9, the detection of the phase change detection pattern included in the frame 9 is performed again.

Thereafter, the detection of the phase change detection pattern included in the frame 9 is stopped by the pattern detection section 20 until the m-th frame (step S15).

At this point, the synchronization detector 19 monitors the synchronization bits included in the frame 9 up to the m-th frame, and determines whether the monitored synchronization bits are normal (step S16). When it is determined that the included synchronization bit is not normal, the process returns to step S1.

On the other hand, if it is determined in step S16 that the synchronization bit included in frame 9 is normal,
After m frames, the pattern detection unit 20 reads the phase 24 stored in the pattern phase storage unit 21 and monitors whether a phase change detection pattern having the same phase as the phase 24 appears in the frame 9. (Step S1
7).

In the pattern detecting section 20, step S
As a result of monitoring the frame 9 at 17, it is determined whether or not a phase change detection pattern having the same phase as the phase 24 is detected in the frame 9 (step S18).
When it is determined that a phase change detection pattern having the same phase as the phase 24 has been detected in the frame 9, it is determined that a phase change has occurred in the frame 9, and the pattern detection unit 20 issues a resynchronization command to the synchronization detection unit 19. 25 is output (step S19), and thereafter, the process returns to step S1.

On the other hand, if it is determined in step S18 that a phase change detection pattern having the same phase as the phase 24 is not detected in the frame 9, it is determined that no frame phase change has occurred in the frame 9, and the process returns to step S18.
9, the phase change detection pattern is detected.

FIG. 6 is a time chart for explaining the operation of monitoring the synchronization bit by the synchronization monitoring section shown in FIG.

As shown in FIG. 6, a frame 9 has a data portion for each frame, a synchronization bit S is added at the beginning of the frame, and a phase change detection pattern is included in the data portion once every m frames. It is inserted and has a different phase from the phase of the frame phase 11 in which the correct synchronization bit phase is set, that is, a phase change occurs.

In this case, in the pattern detecting section 20,
The phase change detection pattern B1 is detected as the phase change detection pattern included in the frame 9.

When the phase change detection pattern B1 is detected by the pattern detection section 20, the phase information from the synchronization bit S immediately before the phase change detection pattern B1 to the first bit of the phase change detection pattern B1 is used as the phase 23. Phase storage unit 2
1 is output.

Thereafter, in the pattern phase storage unit 21,
Phase change detection pattern B output from pattern detection section 20
The phase 23 including the phase change detection pattern B3 is stored as the phase 24 including the phase change detection pattern B3. After m frames, the phase 24 including the phase change detection pattern B3 is read out to the pattern detection unit 20.

After m frames, the pattern detection section 20 detects the phase change detection pattern included in the frame 9 and detects a phase having the same phase as the phase change detection pattern B3 read from the pattern phase storage section 21. Monitoring for the frame 9 is performed for the appearance of the change detection pattern.

Here, if the phase change detection pattern detected from frame 9 is phase change detection pattern B2 having the same phase as phase change detection pattern B3, frame 9
And a resynchronization command 25 is output to the synchronization detection unit 19.

In the data transfer device configured as described above, the phase change detection pattern is inserted using all the bits of the data portion in frame 9. It is also possible to insert a phase change detection pattern into the bits of the section.
By inserting the phase change detection pattern into some bits of the data portion in the frame 9, the number of bits of the phase change detection pattern is reduced, so that the effect of improving data transfer efficiency can be obtained. .

For example, one of the data parts in the frame 9
When the number of bits per frame is n (n is a natural number), it is possible to insert a phase change detection pattern of p (p is a natural number) bits smaller than n bits.

FIG. 7 is a time chart for explaining a synchronous bit monitoring operation of the synchronous monitoring section (see FIG. 4) when a phase change detection pattern is inserted into some bits of the data section in frame 9. It is.

As shown in FIG. 7, in frame 9, a phase change detection pattern is inserted into some bits of the data portion once every m frames. Note that the subsequent operation of monitoring the synchronization bit is the same as the case where the phase change detection pattern is inserted into all the bits of the data portion in the frame 9, and a detailed description thereof will be omitted.

[0111]

As described above, in the present invention,
In the frame transmission device, a phase change detection pattern is inserted into the data portion of the frame once every m frames,
The frame receiving apparatus is configured such that a phase change detection pattern included in a frame is detected once every m frames, and erroneous synchronization due to a phase change of the frame is detected based on the detected phase change detection pattern. Therefore, even when monitoring the 0 and 1 patterns of the synchronization bit and the alternation, it is possible to reliably detect erroneous synchronization due to a change in the phase of the frame.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a data transfer device of the present invention.

FIG. 2 is a block diagram illustrating a phase change detection pattern insertion unit illustrated in FIG. 1;

FIG. 3 is a flowchart illustrating an operation of a phase change detection pattern insertion unit illustrated in FIG. 2;

FIG. 4 is a block diagram illustrating a synchronization monitoring unit illustrated in FIG. 1;

FIG. 5 is a flowchart illustrating an operation of a synchronization monitoring unit illustrated in FIG. 4;

FIG. 6 is a time chart for explaining a synchronization bit monitoring operation of the synchronization monitoring unit shown in FIG. 4;

7 is a time chart for explaining a monitoring operation of the synchronization bit of the synchronization monitoring unit shown in FIG. 4 when a phase change detection pattern is inserted into some bits of a data part in a frame.

FIG. 8 is a block diagram illustrating a configuration example of a receiving device in a conventional data transfer device.

FIG. 9 is a block diagram illustrating a configuration example of a synchronization monitoring unit illustrated in FIG. 8;

FIG. 10 is a diagram for explaining a synchronization bit monitoring operation in the synchronization monitoring unit shown in FIG. 9;

[Explanation of symbols]

 Reference Signs List 1 frame transmission device 2 frame reception device 3 phase change detection pattern insertion unit 4 frame generation unit 5 data extraction unit 6 synchronization monitoring unit 7, 8, 10 data 9 frames 11 frame phase 12 data storage unit 13 pattern generation unit 14 frame number counter Reference Signs List 15 data selection unit 16 data 17 phase change detection pattern 18 frame number 19 synchronization detection unit 20 pattern detection unit 21 pattern phase storage unit 23, 24 phase 25 resynchronization command 26 input data rejection signal 27 data generation device B1, B2, B3 Phase change detection pattern

Claims (6)

[Claims] 1. A data generating device for generating and outputting data, storing data output from the data generating device, encoding the stored data for each frame, and adding a synchronization bit to the frame to generate a frame. And a synchronization monitoring unit that detects a synchronization bit added to the frame transmitted from the frame transmission device, establishes synchronization when the synchronization bit is detected, and outputs a frame phase. A frame receiving device including a data extracting unit that extracts and outputs data from a frame transmitted from the frame transmitting device when a frame phase output from the synchronization monitoring unit is input. In the transfer device, the frame transmission device stores data output from the data generation device, and stores m (m (Natural number) A phase change detection pattern insertion unit that inserts a phase change detection pattern once in a frame and outputs data into which the phase change detection pattern is inserted, and outputs the data output from the phase change detection pattern insertion unit to a frame. And a frame generation unit for transmitting a frame by further adding a synchronization bit, wherein the synchronization monitoring unit sets a phase change detection pattern included in the frame transmitted from the frame generation unit to m. A data transfer device that detects once per frame, detects erroneous synchronization based on the phase of the detected phase change detection pattern, and stops outputting the frame phase. 2. The data transfer device according to claim 1, wherein the phase change detection pattern insertion unit counts up for each frame, and outputs a count value as a frame number. A data storage unit that stores data for each frame and outputs data stored based on the frame number; a pattern generation unit that generates and outputs a phase change detection pattern based on the frame number; A data selection unit that outputs one of a phase change detection pattern output from the pattern generation unit and data output from the data storage unit based on the data. 3. The data transfer device according to claim 1, wherein the synchronization monitoring unit detects the synchronization bit, establishes synchronization when detecting the synchronization bit, and outputs a frame phase. A synchronization detection unit, performs detection of a phase change detection pattern included in a frame transmitted from the frame generation unit once every m frames, and calculates a phase of the detected phase change detection pattern and a phase of the frame phase. A pattern detection unit that outputs the phase of the phase change detection pattern detected when the two do not match, and a pattern phase storage unit that stores the phase of the phase change detection pattern output from the pattern detection unit. After receiving the m-frame data, the pattern detection unit reads the phase stored in the pattern phase storage unit, and determines a phase change having a phase that matches the phase. When an output pattern appears in the frame, a resynchronization command is output to the synchronization detection unit, and the synchronization detection unit stops outputting a frame phase when the resynchronization command is received. Data transfer device. 4. The data transfer device according to claim 1, wherein the pattern generation unit is configured to execute the processing when the capacity for storing the data output from the data generation device is insufficient. A data transfer device for outputting an input data rejection signal to a data generation device. 5. The data transfer device according to claim 1, wherein the pattern generation unit detects a phase change for all bits of a data portion of a frame output from the frame generation unit. A data transfer device characterized by inserting a pattern. 6. The data transfer device according to claim 1, wherein the pattern generation unit performs a phase shift on some bits of a data portion of a frame output from the frame generation unit. A data transfer device, wherein a change detection pattern is inserted.