JP2000330800A - Unit and method for output control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a drawing process for an intermediate code at high speed, to shorten the process time accompanying drawing switching delay, and to efficiently perform the drawing process for the intermediate code by performing an interruption process by a CPU in parallel to a drawing process by a dedicated drawing circuit which performs drawing by using the intermediate code in advance. SOLUTION: An image forming circuit 105 by the intermediate code initiates an interruption and a CPU 101 executes an interruption processing routine. The CPU 101 saves registers in a stack and places itself in a hold state. The image forming circuit 105 resets the hold state of the CPU 101, holds its drawing, completes drawing by the CPU 101, and performs the drawing when the drawing is released from being held. The CPU 101 performs the drawing when the holding is reset from the image forming circuit 105, releases the image forming circuit 105 from being held, and reloads the registers to exit from the interruption routine.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output control apparatus having a plurality of drawing means for performing a drawing process based on an intermediate code generated by analyzing input output information and an output control method.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram for explaining the configuration of a printing apparatus to which this type of output control apparatus can be applied. A host 100 for creating print data and a printing apparatus 112 are connected via a predetermined interface. It corresponds when communication is possible. It is assumed that the printing device 112 includes the print control device 111 and the engine 110.

In the printing apparatus 112, 101 is a CPU.
Thus, the entire circuit is controlled based on the control program stored in the ROM 102. Note that the ROM 102 stores a print control program. 103 is a font ROM
In (FONTROM), outline or bitmap printer font data and the like are stored.

A RAM 104 stores print data from the host 100 and variables for executing a program.
Reference numeral 105 denotes an image forming circuit which converts image data for printing into C
It is formed on the image memory 106 according to a command from the PU 101.

Reference numeral 107 denotes a video circuit, and an image memory 106
The image data is read from the printer 110 and transferred to the engine 110 that actually prints the image. A host interface (host I / F) 108 receives print data from the host 100. A bus 109 connects the entire circuit blocks.

In the printing apparatus thus configured, print data is generated by the host 100, and the host I / F 10
8 and temporarily stored in the RAM 104 by the CPU 101. Subsequently, interpreted by the CPU 101,
The image data is converted into actual image data by the image forming circuit 105 and stored in the image memory 106. The image data created in the image memory 106 is read by the video circuit 107, transferred to the printing device 110, and forms an image on a printing medium such as paper.

The image memory 106 is provided with a bus selector so that the CPU 101 can access the image memory 106 while there is no access from the image forming circuit 105, and the CPU 101 can also form image data. I have.

In normal printing, the image forming circuit 105 forms image data on the image memory 106.
Depending on the print data designated from 0, the image forming circuit 105 cannot create the data or the circuit can draw, but the drawing circuit itself becomes complicated and the cost of the entire apparatus may increase.

At this time, the CPU 101 operates the image forming circuit 1
In some cases, the image memory 106 is accessed in place of the image data 05 to create image data for direct printing. CPU
While the image 101 is forming an image in the image memory 106, the image forming circuit 105 stops drawing and the CPU 101
Will end drawing.

The image forming circuit 105 holds information for forming image data in the form of an intermediate code called a display list.

FIG. 7 shows the image forming circuit 105 shown in FIG.
FIG. 5 is a diagram conceptually illustrating the correspondence between the intermediate code held in the.

In the figure, reference numeral 214 denotes a print medium such as paper, and three drawing objects are shown in this figure. 216,
218 is a character, and 220 is image data.
One intermediate code is prepared for each image.

Reference numerals 215, 217, and 219 denote addresses serving as drawing references, which are characters 216, 218, and image data 2
20 respectively.

The intermediate code includes a drawing start position 212, 2
13 and an object address 211 which is the head of the image to be drawn, and a flag 210. The flag 210 indicating the control of the entire intermediate code is used to stop the drawing or the CPU 10.
1 shows the transition of drawing to 1. Note that the object address 211 holds the address of the RAM 104 in which the data of the image to be drawn in the image memory 106 is stored.

The drawing start positions 212 and 213 indicate the coordinates in the image memory 106 at which the drawing is started. This is the position of addresses 215, 217, 219, etc.

FIG. 8 is a view for explaining the contents of the flag 210 shown in FIG.

In the figure, the content of the flag 210 is “0”.
If the value is "0", the intermediate code is interpreted as it is, indicating that the drawing is to be executed. If the value is "10", the CPU 101 does not immediately draw the drawing content including this flag but instead draws the content. After the drawing is completed, the subsequent drawing is performed. If the drawing is “11”, it indicates that the processing of the intermediate code is finished after the drawing by the designated intermediate code. However, the content of the flag “01” is not defined here.

When the content of the flag 210 is "10", the CPU 101 performs drawing. At this time, data for a program that has been executed up to that time is generated based on an interrupt generated by the image forming circuit 105. Is saved in a stack or the like, and a subroutine for image formation is executed. When the drawing operation by the CPU 101 ends, the CP
U101 extracts the data saved on the stack as before and continues the processing before the interruption.

Further, while the CPU 101 is performing the drawing, the image forming circuit 105 interrupts the drawing operation which has been performed so far, receives the information of the end of the drawing of the CPU itself from the CPU 101, and continues the drawing data if necessary. And a circuit for performing the operation.

FIG. 9 shows the image forming circuit 105 shown in FIG.
FIG. 2 is a block diagram illustrating a configuration of a main part of FIG.

In the figure, reference numeral 304 denotes an intermediate code buffer which holds an intermediate code to be executed. A flag detection circuit 305 decodes flag information output from the intermediate code buffer 304, generates an interrupt signal for the CPU 101, and sets and resets the FF3.
09 is set, and the execution of the intermediate code is suspended until the CPU 101 finishes drawing.

Reference numeral 310 denotes an address decoder.
When 1 finishes drawing, a predetermined value is written to a specific bit of a specific address, thereby clearing the set reset FF 309 which stops the intermediate code and restarting the drawing of the image forming circuit 105. Have. 31
Reference numeral 1 denotes a gate, which is a CPU data and address decoder 310.
Is output to the reset input R of the set / reset FF 309.

FIG. 10 is a transition diagram for explaining a drawing processing state in the output control device shown in FIG. 6, in which each column corresponds to the movement of each circuit and the time elapses according to the downward arrow in the figure. Is shown.

In the figure, the movement of the CPU 101, the processing of the intermediate code, the drawing processing on the image memory 106 by the image forming circuit, and the rightmost set reset FF are shown from the left column.
309 is shown.

At first, the drawing starts from the intermediate code 400-1, and while the flag 401-1 is "00", ie, the drawing codes C1 to C3, the image data 402-1 to 40-40.
2-3 are created by the image forming circuit 105.

When the rendering code C4 is reached, the content of the flag 401-4 of the intermediate code 400-4 is "10", which indicates that the rendering is performed by the CPU 101. The flag detection circuit 305 generates an interrupt signal to the CPU 101, sets the set / reset FF 309, and enters the hold state 410.

Subsequently, the CPU 101 starts from timing T2.
Is performed by the CPU, and when the processing is completed, at timing T3, in the drawing restart processing 415 for restarting the drawing that has been holding the image forming circuit 105, the processing to the address decoder 310 in the control circuit of the image forming circuit is performed. The access is performed and the held drawing process is restarted, and the image forming circuit 105 executes the drawing process of the drawing data 402-4. The CPU 101 executes the return process 413 from the interrupt at the timing T4, and continues executing the instruction before the interrupt.

[0028]

However, if the processing of drawing by the CPU is performed from the interrupt processing to the CPU as in the prior art, the processing of the registers to be saved by the CPU and the register saving access accompanying the processing often occur. Therefore, since the time required for drawing is originally reduced, there is a problem that the more the CPU draws, the more efficient drawing becomes impossible.

The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to provide a case where drawing by an exclusive drawing circuit for performing drawing using an intermediate code and a CPU is performed by interrupt processing. By performing the processing related to the interrupt handling in advance in parallel with the drawing processing by the dedicated drawing circuit, the intermediate code can be drawn at a high speed despite the processing by the CPU using an interrupt. An object of the present invention is to provide an output control device and an output control method capable of efficiently rendering intermediate codes by reducing the accompanying processing time.

[0030]

According to a first aspect of the present invention, a plurality of drawing means (an image forming apparatus shown in FIG. 2) for performing a drawing process based on an intermediate code generated by analyzing input output information. An output control device having at least one of a first designation information for designating a drawing unit on which the generated intermediate code is to be drawn and a plurality of drawing units when analyzing the output information. Setting means (CPU 101 shown in FIG. 2) for setting, in the intermediate code, second designation information for designating start of drawing preparation to another drawing means to start a subsequent drawing process after drawing by the drawing means.
).

According to a second aspect of the present invention, any one of the plurality of drawing means (the image forming circuit 105 shown in FIG. 2) is set in the generated intermediate code.
, An interrupt request to another drawing means is generated in parallel with the drawing processing for the intermediate code.

According to a third aspect of the present invention, one of the drawing means (the image forming circuit 105 shown in FIG. 2) is configured to execute the intermediate code based on the first designation information set in the generated intermediate code. This indicates to the other drawing means the drawing processing destination for.

According to a fourth aspect of the present invention, the other drawing means (CPU 101 shown in FIG. 2) executes a predetermined standby process based on the interrupt request and makes a transition to a wait state.

According to a fifth aspect of the present invention, the other drawing means (CPU 101 shown in FIG. 2) executes a predetermined standby process based on the interrupt request and performs a drawing process when the state shifts to a wait state. The end information of a specific drawing among the plurality of drawing units immediately before the start is set in the intermediate code.

In a sixth aspect according to the present invention, the other drawing means returns to a state immediately before a wait state based on the end information after drawing based on the designated intermediate code.

According to a seventh aspect of the present invention, the other drawing means is a CPU (CPU 101 shown in FIG. 2).

In an eighth aspect according to the present invention, any of the drawing means is a drawing-only circuit (image forming circuit 105 shown in FIG. 2).

According to a ninth aspect of the present invention, a dedicated drawing circuit (image forming circuit 105 shown in FIG. 2) and a CPU (FIG. 2) perform a drawing process based on an intermediate code generated by analyzing input output information. And an output control method in the output control device performed by the CPU 101), which prepares an interrupt process for analyzing the intermediate code and starting a drawing process preparation for the CPU in parallel with a drawing process by the dedicated drawing circuit. Process (Steps (9) to (1) shown in FIG. 5)
1)), a drawing step (step (6) shown in FIG. 5) for analyzing the intermediate code and performing drawing processing after the preparation step is completed, and after the drawing step is completed, the dedicated drawing circuit and the CPU (Steps (6), (7), and FIG. 5) shown in FIG.
(8)).

According to a tenth aspect of the present invention, the preparation step (steps (9) to (10) shown in FIG. 5) includes the C
A predetermined interrupt process for the PU is executed, and after the drawing process by the dedicated drawing circuit is completed, the PU is transited to the hold state.

According to an eleventh aspect of the present invention, in the predetermined interrupt processing, state information before drawing by the CPU is started is saved in a memory, and a CPU cycle is shifted to a wait state.

[0041]

FIG. 1 is a block diagram for explaining the arrangement of an image output apparatus to which an output control apparatus according to an embodiment of the present invention can be applied. Is attached.

In the figure, reference numeral 106A denotes an image memory unit.
As will be described in detail later, the apparatus includes a selector, a memory controller, and an image memory.

FIG. 2 is a block diagram illustrating the configuration of an output control device according to an embodiment of the present invention. The same components as those in FIG. 6 are denoted by the same reference numerals.

In the figure, reference numeral 101 denotes a CPU which executes a control program stored in a ROM 102 shown in FIG. 1 to control access to an image memory unit 106A and to access each device connected to an internal bus. Is controlled overall.

Reference numeral 105 denotes an image forming circuit, and reference numeral 106A denotes an image memory unit. Reference numeral 3 denotes a selector for switching access between the CPU 101 and the image forming circuit 105. A memory controller 4 controls access of the image memory 5 from the CPU 101 or the image forming circuit 105 by the selector 3. That is, the CP
It can be accessed from both the U101 and the image forming circuit 105.

The image memory 5 has an image forming circuit 10
The drawing data created in step 5 is created, and the image data is sent to the printing device (engine) 110 by the video circuit 107 shown in FIG. Also, an interrupt signal S1 and a wait request signal S2 are sent from the image forming circuit 105 to the CPU.
The image forming circuit 105 shown in FIG.
Of the CPU 101 is controlled by an interrupt or a wait.

FIG. 3 shows the image forming circuit 105 shown in FIG.
10 is a control circuit block diagram for explaining the internal configuration, and the same components as those in FIG. 9 are denoted by the same reference numerals.

In the figure, reference numerals 300 and 302 denote address registers which hold the addresses accessed by the CPU 101 detected by the comparators 301 and 303, respectively. The comparators 301 and 303 detect that the CPU has accessed the address set by the address registers 300 and 302 and transmit the detected signal to the circuit by a signal.

Reference numeral 304 denotes an intermediate code buffer which holds the contents of the intermediate code being executed, and the held contents of the intermediate code flag are sent to flag detection circuits 305 and 306 to determine whether a predetermined flag is set. Is detected.

The flag detection circuit 305 outputs an interrupt request signal to the CPU 101 to cause the CPU 101 to start preparation for drawing. Reference numeral 307 denotes an AND gate, which sets a rendering execution preparation flag for the CPU 101, and sets an output FF 308 for a CPU wait request signal when the comparator 301 detects an access to an address set by the CPU 101.

The flag detection circuit 306 detects the set state of the drawing execution flag for the CPU 101, resets the wait request FF 308 to the CPU when detecting that the drawing execution flag is set, and starts the drawing by the CPU 101. Reset F which temporarily suspends the drawing of the image forming circuit 105 by the intermediate code
Set F309.

FIG. 4 is a transition diagram for explaining the drawing processing state in the output control device according to the present invention, and the same components as those in FIG. 10 are denoted by the same reference numerals. The leftmost is
This shows the state of the CPU weight P308.

First, drawing starts from the intermediate code 400-1, and while the flag 401-1 is "00", that is, the drawing data C1 to C2, the image data 402-1.
402-2 are created by the image forming circuit 105.

Then, the intermediate code 40 of the drawing code C3
The contents of the flag 401-3 of 0-3 are "01". When this is detected by the flag detection circuit 305 shown in FIG.
01 interrupts the processing performed so far, and
At 11, an interrupt process 404 is executed. During this time, the image forming circuit 105 performs drawing on the image memory 5 like drawing data 402-3. Then, when the interrupt processing is completed, the CPU 101 preliminarily inserts an access instruction before the drawing program so as to access the address AD1 set in the address register 300.

Then, at the time when the interrupt processing is completed, that is, at the timing T12, by executing this code, the comparator 301 asserts a signal and the FF30
8 is set, and the CPU 101 enters the wait state at timing T13. Timing T14 is FF308
Indicates the time that is set. With this, CPU1
01 is prepared in a state of stopping immediately before drawing, and when the drawing process of the image data 402-3 by the image forming circuit 105 is completed and the intermediate code 400-4 of the drawing code C4 is read, the flag 401-4 is reset. Since the content is “10”, drawing by the CPU 101 is started. That is,
The output of the flag detection circuit 306 shown in FIG. 3 is asserted, the FF 309 is set, the drawing of the image forming circuit 105 enters the hold state 410, the FF 308 is reset, and the wait of the CPU 101 is released. Is executed.

A code for accessing the address AD2 set in the address register 302 is set in advance between the drawing execution program by the CPU 101 and the return processing from the interruption, and this code is executed at timing T15. Then, the output of the comparator 303 is asserted, and the intermediate code-based image forming circuit 105
Is released, and the drawing data 402-
The drawing process is executed as shown in FIG. Also, during this time, the process of returning from the interrupt of the CPU 101 at the timing T16 is performed in parallel, and the CPU 101 can return to the process before the interrupt was input normally.

Hereinafter, the alternative drawing processing operation specified by the CPU 101 in the intermediate code will be described with reference to the flowchart shown in FIG.

FIG. 5 is a flowchart showing an example of a data processing procedure in the output control device according to the present invention.
The flowchart on the left corresponds to the operation procedure of the drawing circuit,
The flowchart on the right side corresponds to the interrupt operation procedure of the CPU. Note that (1) to (17) indicate each step.

The image forming circuit 105 performs step (9).
Then, the intermediate code is read, and it is checked whether or not the flag is "10" in step (10). If it is determined that the flag is "10", the CPU 101 determines in step (11)
Issue an interrupt to. The CPU 101 controls the image forming circuit 10
In response to the interrupt request signal from the CPU 5, the CPU 101 executes an interrupt processing routine.

The CPU 101 firstly performs step (1)
Then, the register is saved to the stack, and step (2) is performed.
In step (3), the address AD1 is accessed, and in step (4), the device itself is put into a hold state.

Next, in step (5), the image forming circuit 1
Wait for hold release from 05.

On the other hand, the image forming circuit 105 determines whether or not the flag is “10” in step (12).
If it is ES, the CPU 101 releases the hold of the CPU 101 in step (13), holds its own drawing in step (14), and determines in step (15) whether the FF 308 as the hold FF has been cleared. That is, the drawing by the CPU 101 in step (6) is completed, and in step (7), the process waits until the hold is released. When the hold is released, the process proceeds to step (16).

On the other hand, in step (12), the flag is set to "1".
If it is determined that the flag is not "0", the drawing is executed in step (16). In step (17), it is determined whether or not the flag is "11", which is the end. If it is determined that the flag is not "11", Returning to step (9), the next intermediate code is processed, and if it is determined to be "11", the operation is terminated.

On the other hand, the CPU 101 determines in step (5)
In step (13), if the hold is released from the image forming circuit 105, the drawing is performed in step (6), and the address AD2 is accessed in step (7). In step (8), the image forming circuit 105 is released from the hold state, and in step (8), the operation of restoring the registers and the like is performed, and the process exits from the interrupt routine and returns to the normal operation.

According to the above embodiment, an interrupt is issued to the CPU before drawing by the CPU, and when the preparation for drawing is completed, means for holding by the CPU is prepared, and the CPU is set in the wait state. When the image forming circuit finishes drawing, the CPU is released from the wait state so that drawing by the CPU can be started immediately, thereby improving drawing efficiency by the CPU.

Although the output control device has been described by taking an image output device such as a printer as an example, it goes without saying that the output control device can also be applied to drawing processing of a display device or the like.

[0067]

As described above, the first embodiment according to the present invention is described.
According to the eleventh aspect, when drawing by the dedicated drawing circuit for drawing using the intermediate code and the CPU is performed by interrupt processing, processing related to interrupt handling is performed in parallel with drawing processing by the dedicated drawing circuit in advance. In this way, the intermediate code can be drawn at a high speed, despite the interrupt processing by the CPU, the processing time associated with the drawing switching delay can be reduced, and the intermediate code can be drawn efficiently. To play.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image output device to which an output control device according to an embodiment of the present invention can be applied.

FIG. 2 is a block diagram illustrating a configuration of an output control device according to an embodiment of the present invention.

FIG. 3 is a control circuit block diagram illustrating a configuration in an image forming circuit illustrated in FIG. 2;

FIG. 4 is a transition diagram illustrating a drawing processing state in the output control device according to the present invention.

FIG. 5 is a flowchart illustrating an example of a data processing procedure in the output control device according to the present invention.

FIG. 6 is a block diagram illustrating a configuration of a printing apparatus to which this type of output control device can be applied.

FIG. 7 is a diagram conceptually illustrating a correspondence between an intermediate code held in the image forming circuit shown in FIG. 6 and an output image thereof.

FIG. 8 is a diagram for explaining the contents of a flag shown in FIG. 7;

FIG. 9 is a block diagram illustrating a configuration of a main part of the image forming circuit illustrated in FIG. 6;

FIG. 10 is a transition diagram illustrating a drawing processing state in the output control device illustrated in FIG. 6;

[Explanation of symbols]

 3 Selector 4 Memory Controller 5 Image Memory 100 Host 101 CPU 102 ROM 103 RAM 105 Image Forming Circuit 106A Image Memory Unit 107 Video Circuit 301, 303 Comparator 300, 302 Address Register 304 Intermediate Code Buffer 305, 306 Flag Detection Circuit 307, 311 AND Gate 308, 309 Set reset FF

Claims (11)

[Claims] 1. An output control device having a plurality of drawing means for performing a drawing process based on an intermediate code generated by analyzing input output information, the intermediate code being generated when the output information is analyzed. After the first designation information for designating the drawing means to be drawn or drawing by any one of the plurality of drawing means, the start of drawing preparation to another drawing means to start the subsequent drawing processing is designated. An output control device provided with setting means for setting the second designation information to be set in the intermediate code. 2. A drawing unit of a plurality of drawing units, based on second designation information set in the generated intermediate code, executes another drawing unit in parallel with the drawing process for the intermediate code. 2. The output control device according to claim 1, wherein an interrupt request is issued to the output control device. 3. The image processing apparatus according to claim 1, wherein one of the drawing units instructs another drawing unit a drawing processing destination for the intermediate code based on first designation information set in the generated intermediate code. Item 2. The output control device according to Item 1. 4. The output control device according to claim 2, wherein the other drawing unit executes a predetermined standby process based on the interrupt request and transitions to a wait state. 5. When a predetermined standby process is executed based on the interrupt request and a transition is made to a wait state, the other drawing unit terminates a specific drawing of the plurality of drawing units immediately before the start of the drawing process. 3. The output control device according to claim 2, wherein the information is set in an intermediate code. 6. The output control device according to claim 5, wherein the other drawing unit returns to a state immediately before a wait state based on the end information after drawing based on the designated intermediate code. . 7. The output control device according to claim 1, wherein the other drawing unit is a CPU. 8. The output control device according to claim 1, wherein said one of the drawing means is a dedicated circuit for drawing. 9. A dedicated drawing circuit and a CPU for performing a drawing process based on an intermediate code generated by analyzing input output information.
An output control method in the output control device, comprising: performing an interrupt process for analyzing the intermediate code and starting preparation for a drawing process for the CPU in parallel with a drawing process performed by the dedicated drawing circuit; After the preparation step, a drawing step of analyzing the intermediate code to perform a drawing process; After the drawing step, a return step of returning the dedicated drawing circuit and the CPU to a state before the start of the preparation step;
An output control method comprising: 10. The output control according to claim 9, wherein in the preparing step, a predetermined interrupt process is performed on the CPU, and after the drawing process by the dedicated drawing circuit is completed, a transition is made to a hold state. Method. 11. The output control method according to claim 10, wherein in the predetermined interrupt processing, state information before drawing by the CPU is started is saved in a memory, and a CPU cycle is shifted to a wait state. .