JP2000323816A - Manufacture of printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a printed wiring board capable of reliably forming wiring layers on resin insulating layers. SOLUTION: The method of manufacturing a printed wiring board comprises the following steps: forming electroless Cu plated layers 17 and 18 on roughened resin insulating layers 13 and 14, the layers 17 and 18 satisfying the inequality R30<=0.061 exp(0.18X) with respect to the narrowest conductor gap X of wiring layers, R30 being the 10 point average roughness for a distance between 30 μm; forming plated resist layers 23 and 24 on the layers 17 and 18; and forming electrolytically Cu plated layers 27 and 28 on the exposed layers 17 and 18, thereafter stripping the layers 23 and 24, and forming wiring layers 3 and 4 by etching. As a result, the contact strength between the layers 23 and 24 and the layers 17 and 18 is increased, thereby suppressing the floating and/or flaking of the layers 23 and 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a printed wiring board having a resin insulating layer, and more particularly to a method of manufacturing a printed wiring board capable of forming a wiring layer reliably.

[0002]

2. Description of the Related Art Conventionally, when manufacturing a printed wiring board made of resin, a wiring layer is formed on a resin insulating layer as follows, for example. That is, as shown in a partially enlarged view of FIG. 12A, a laminated substrate 101 having a resin insulating layer 102 on the surface is prepared, and the entire surface is subjected to electroless plating to form an electroless plated layer 103. .

[0003] Next, as shown in FIG. 12 (b), a photosensitive dry film 104 is attached on the entire surface of the electroless plating layer 103. Further, as shown in FIG.
This is exposed and developed to form a plating resist layer 105 having a predetermined pattern. Next, as shown in FIG. 13A, electrolytic plating is performed, and electrolytic plating is thickened on the electroless plating layer 103 exposed from the plating resist layer 105 to form an electrolytic plating layer 106. Thereafter, the plating resist layer 105 is peeled off, quick etching is performed, and unnecessary portions of the electroless plating layer 103 and the like are removed by etching. Then, as shown in FIG.
2, a wiring layer 107 is formed.

[0004]

However, from the dry film 104, the plating resist layer 1 having a predetermined pattern is formed.
At the time of forming the layer 05 (see FIGS. 12B and 12C), for example, when a developing solution is sprayed during development, a part of the plating resist layer 105 may peel off or float from the electroless plating layer 103. May be done. In particular, the conductor gap D
A (see FIG. 13B) when forming the wiring layer 107 having a small conductor pattern, that is, the plating resist layer 1
When the width RA (see FIG. 12C) of the pattern 05 becomes narrow, the plating resist layer 105 is easily peeled off or floated from the electroless plating layer 103 at that portion. If the plating resist layer 105 peels or floats, an electrolytic plating layer is formed also on the electroless plating layer 103 at the peeled portion, which causes a short circuit.

As a result of the study, the present inventor has found that the adhesion strength between the plating resist layer 105 and the electroless plating layer 103 is affected by the surface roughness of the electroless plating layer 103. That is, it has been found that when the surface roughness of the electroless plating layer 103 is large, the plating resist layer 105 is easily peeled off or floated from the electroless plating layer 103.

Usually, the wiring layer 107 is formed on the resin insulating layer 102.
In order to increase the adhesion strength between the resin insulating layer 102 and the wiring layer 107 (electroless plating layer 103) by the anchor effect, the resin insulating layer 102 is formed before forming the electroless plating layer 103. Is roughened (see FIG. 12A). When the electroless plating layer 103 is formed on the resin insulating layer 102 thus roughened, the surface 103A of the electroless plating layer 103 also becomes rough like the surface 102A of the resin insulating layer 102. Therefore, it was considered that the plating resist layer 105 was easily peeled off from the electroless plating layer 103.

It has also been found that the smaller the conductor gap DA of the wiring layer 107 is, the smaller the surface roughness of the electroless plating layer 103 is, the more the peeling or floating of the plating resist layer 105 is likely to occur. That is, the plating resist layer 105
It has also been found that the ease of peeling is related to the size of the conductor gap DA of the wiring layer 107 and the surface roughness of the electroless plating layer 103.

The present invention has been made in view of such knowledge, and suppresses the plating resist layer from peeling off or floating from the electroless plating layer, and reliably forms a wiring layer on the resin insulating layer. It is an object of the present invention to provide a method for manufacturing a printed wiring board which can be used.

[0009]

Means for Solving the Problems, Functions and Effects The means for solving the problem is that the narrowest conductor gap is X (μ) on the resin insulating layer.
m) is a method for manufacturing a printed wiring board provided with a wiring layer having a conductor pattern, wherein the surface of the resin insulating layer having a roughened surface has a 10-point average roughness R of 30 μm on the surface.
₃₀ (μm) is within the range of 15 ≦ X ≦ 25, and the formula R ₃₀ ≦
An electroless plating layer forming step of forming an electroless plating layer satisfying 0.061 exp (0.18X); a resist layer forming step of forming a plating resist layer having a predetermined pattern on the electroless plating layer; On the electroless plating layer exposed from the layer, after forming an electrolytic plating layer, peeling the plating resist layer, etching the electroless plating layer exposed after peeling, forming a wiring layer to form a wiring layer And a process for producing a printed wiring board.

This printed wiring board includes a wiring layer having a conductor pattern in which the narrowest conductor gap X (μm) is in the range of 15 μm to 25 μm. According to the present invention, the surface of the resin insulating layer is roughened in order to increase the adhesive strength between the wiring layer and the adhesive strength between the resin insulating layers when the resin insulating layer is further laminated. I have. Then, in the electroless plating layer forming step, a 10-point average roughness R ₃₀ of 30 μm on the surface of the roughened resin insulating layer is set to R ₃₀ ≦ 0.06.
An electroless plating layer is formed by, for example, thickening so as to satisfy 1 exp (0.18X).

[0011] With this form of the surface roughness R ₃₀ of small non-electrolytic plating layer, a resist layer forming step, when forming the plating resist layer in an electroless plating layer, and an electroless plating layer and the plating resist layer Can increase the adhesion strength. Therefore, even if the surface of the resin insulating layer is larger roughened, the surface roughness R ₃₀ of the electroless plating layer is made smaller to satisfy the above equation, the plating resist layer is peeled off from the electroless plating layer , Suppresses floating,
A yield of 80% or more can be secured.

[0012] Therefore, when performing electroplating in the wiring layer forming step, the plating resist layer is prevented from peeling or floating, so that a short circuit is unlikely to occur, and the plating resist layer is exposed on the electroless plating layer exposed from the plating resist layer. Only the electrolytic plating layer can be formed. Further, since the resin insulating layer is roughened, the adhesion strength between the resin insulating layer and the wiring layer (electroless plating layer) is high. Therefore, the wiring layer can be reliably formed on the resin insulating layer.

Note that, in this specification, 10 points flat between 30 μm
Average roughness R₃₀Is defined by JIS at 30 μm intervals
Surface roughness measured according to the method of measuring surface roughness Rz
Say. Each point is measured under an electron microscope or an optical microscope.
To enlarge the cut surface of the electroless plating layer or the like. Also,
After manufacturing the lint wiring board, the surface roughness R of the electroless plating layer ₃₀
Is measured, a via is formed in the resin insulation layer.
The electroless medium formed on the side of this via.
Surface roughness R of stick layer₃₀Can be conveniently measured
You.

Here, the resin insulating layer may be appropriately selected in consideration of the adhesion to the wiring layer (electroless plating layer), the coefficient of thermal expansion, and the like. For example, epoxy resin, polyimide resin, BT resin, Resin such as PPE resin, composite material of these resins with organic fiber such as glass fiber (glass woven fabric or glass non-woven fabric) or polyamide fiber, or three-dimensional mesh-like fluororesin base material such as continuous porous PTFE And a resin-resin composite material impregnated with a resin such as an epoxy resin.

The surface of the resin insulating layer may be roughened in consideration of the adhesion strength with the wiring layer and the like, and the surface roughness can be appropriately selected. The surface of the resin insulating layer may be, for example, chemically roughened with chromic acid or potassium permanganate, or may be physically roughened by polishing or the like. As a method for forming the plating resist layer, for example, a photosensitive dry film may be attached and formed by exposing and developing a predetermined pattern.
Alternatively, a resist layer may be applied over the entire surface, and may be formed by exposing and developing into a predetermined pattern.

The printed wiring board may be any one provided with a resin insulating layer and a wiring layer. For example, the printed wiring board may be provided on one or both sides of a core substrate or without a core substrate.
An example in which a plurality of insulating layers and wiring layers are sequentially stacked is given. Further, a connection pad for mounting an electronic component such as an integrated circuit chip on the main surface of the printed wiring board or connecting to another substrate, or a pin as an input / output terminal may be provided.

Further, the present invention provides a method for manufacturing a printed wiring board comprising a wiring layer having a conductor pattern having a narrowest conductor gap of X (μm) on a resin insulating layer, wherein the resin has a roughened surface. On the insulating layer, the average roughness R ₃₀ (μm) of 10 points between 30 μm on the surface is in the range of 15 ≦ X ≦ 32,
An electroless plating layer forming step of forming an electroless plating layer satisfying R ₃₀ ≦ 0.15exp (0.12X); a resist layer forming step of forming a plating resist layer of a predetermined pattern on the electroless plating layer; After forming an electrolytic plating layer on the electroless plating layer exposed from the plating resist layer, the plating resist layer is peeled off, and the electroless plating layer exposed after peeling is etched to form a wiring layer. And a wiring layer forming step.

According to the present invention, in the step of forming the electroless plating layer, the narrowest conductor gap X (μm) among the wiring layers is formed on the roughened resin insulating layer by a distance of 30 μm on the surface. 1
0 point average roughness R ₃₀ (μm) is R ₃₀ ≦ 0.15exp
An electroless plating layer is formed so as to satisfy (0.12X). That is, a smaller value of the surface roughness R ₃₀ of the electroless plating layer.

Therefore, when the plating resist layer is formed on the electroless plating layer in the resist layer forming step, the adhesion strength between the electroless plating layer and the plating resist layer can be further increased. Separation and floating of the layer can be further suppressed, and a yield of 90% or more can be secured. Therefore, in the subsequent wiring layer forming step, a short circuit is less likely to occur, and the electrolytic plating layer can be formed only on the electroless plating layer exposed from the plating resist layer, so that the wiring layer can be formed more reliably. Can be.

Further, the present invention provides a method for manufacturing a printed wiring board comprising a wiring layer having a conductor pattern having a narrowest conductor gap of X (μm) on a resin insulating layer, wherein the resin has a roughened surface. On the insulating layer, the average roughness R ₃₀ (μm) of 10 points between 30 μm on the surface is in the range of 15 ≦ X ≦ 32,
An electroless plating layer forming step of forming an electroless plating layer satisfying R ₃₀ ≦ 2.0exp (0.071X); a resist layer forming step of forming a plating resist layer having a predetermined pattern on the electroless plating layer; After forming an electrolytic plating layer on the electroless plating layer exposed from the plating resist layer, the plating resist layer is peeled off, and the electroless plating layer exposed after peeling is etched to form a wiring layer. And a wiring layer forming step.

According to the present invention, in the step of forming the electroless plating layer, the narrowest conductor gap X (μm) of the wiring layer is formed on the roughened resin insulating layer by a distance of 30 μm on the surface. 1
0 point average roughness R ₃₀ (μm) is R ₃₀ ≦ 2.0exp
(0.071X), an electroless plating layer is formed. That is, a smaller value of the surface roughness R ₃₀ of the electroless plating layer.

For this reason, in forming the plating resist layer on the electroless plating layer in the resist layer forming step, the adhesion strength between the electroless plating layer and the plating resist layer can be further increased. Peeling and lifting of the layer can be further suppressed, and a yield of almost 100% can be secured. Therefore, in the subsequent wiring layer forming step, a short circuit is less likely to occur, and the electrolytic plating layer can be formed only on the electroless plating layer exposed from the plating resist layer, so that the wiring layer can be formed more reliably. Can be.

Further, in the above-mentioned method for manufacturing a printed wiring board, the surface of the resin insulating layer preferably has a 10-point average roughness R ₃₀ of ₃₀ μm satisfying the above expression and R ₃₀ ≧ 0.5 μm. It is preferable to adopt a method for manufacturing a printed wiring board.

The 10-point average roughness R ₃₀ of 30 μm on the surface of the resin insulating layer is expressed by the above formula: R ₃₀ ≦ 0.061 exp (0.18
X), R ₃₀ ≦ 0.15exp (0.12X), or
R ₃₀ ≦ 2.0exp (0.071X) is satisfied, and
When R ₃₀ ≧ 0.5 μm is satisfied, when the electroless plating layer is thinned, specifically when the electroless plating layer is thinned to 1 μm or less, the surface roughness of the electroless plating layer is also smaller than the surface roughness of the resin insulating layer. Almost unchanged. That is, when the surface roughness of the resin insulating layer satisfies R ₃₀ ≦ 0.061 exp (0.18 ×), the 10-point average roughness R ₃₀ of 30 μm on the surface of the electroless plating layer also satisfies this equation. When the surface roughness of the resin insulating layer satisfies R ₃₀ ≦ 0.15 exp (0.12 ×), the surface roughness R ₃₀ of the electroless plating layer also satisfies this equation. Further, the surface roughness of the resin insulating layer is R ₃₀ ≦ 2.0 exp.
(0.071X) when satisfying the surface roughness R ₃₀ of the electroless plating layer also satisfies this equation.

Therefore, since the adhesion strength between the plating resist layer and the electroless plating layer is increased, it is possible to prevent the plating resist layer from peeling off or floating from the electroless plating layer, and furthermore, to prevent the electroless plating layer from floating. It is sufficient to make the thinner, so that the time and cost can be reduced.
Moreover, the surface roughness R ₃₀ of the resin insulation layer is 0.5μm or more, the adhesion strength between the resin insulating layer and a wiring layer (electroless plating layer) can be ensured.

It should be noted that the surface roughness of the resin insulating layer is determined by the formula R ₃₀
≦ 0.061 exp (0.18X), the formula R ₃₀ ≦
0.15 exp (0.12X), furthermore, the formula R ₃₀ ≦
If 2.0exp (0.071X) is satisfied,
The effect of suppressing the plating resist layer from peeling off or floating from the electroless plating layer is further enhanced. For this reason, the yield at the time of manufacturing a printed wiring board can be further improved.

[0027]

Embodiment 1 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1A shows a plan view of the printed wiring board 1 manufactured in the present embodiment as viewed from the main surface 1A side, and FIG. 1B shows a partially enlarged view of a broken line portion in FIG. 1A. .

The printed wiring board 1 has a main surface 1A and a back surface (not shown) as shown in FIG.
It has a substantially square plate shape of 2.5 × 42.5 mm. On the main surface 1A side, an IC mounting area 2 for mounting an integrated circuit chip is formed. The wiring layer 3 is formed on the main surface 1A side. As shown in FIG. 1B, a part of the wiring layer 3 is formed in a comb shape with a certain conductor gap X in the vertical direction in the figure. The conductor width DH of the wiring layer 3 in this portion is 20 μm, and the conductor gap X is 20 μm.

In the printed wiring board 1, the conductor gap X in the portion of the wiring layer 3 shown in FIG.
It is the narrowest (20 μm). For this reason, in manufacturing the printed wiring board 1, as described later, when forming an electroless Cu plating layer on the resin insulating layer, the plating resist layer corresponding to this portion is most peeled off from the electroless Cu plating layer. And easy to float.

Next, a method of manufacturing the printed wiring board 1 will be described with reference to FIGS. First, the laminated substrate 11 is prepared. FIG. 2A shows the laminated substrate 11.
FIG. 2 shows a partially enlarged cross-sectional view of a portion corresponding to the AA cross section of FIG. 1B (the same applies to FIGS. 2 to 4). The substrate to be laminated 11 is formed by a known method.
Resin insulating layers 13 and 14 made of epoxy resin are laminated on both surfaces of a core substrate 12 made of T resin. Surfaces 13A, 13B of these resin insulating layers 13, 14
(The main surface 11A and the back surface 11B of the laminated substrate 11) are previously roughened by potassium permanganate, and the 10-point average roughness R _{30 for 30} μm is set to about 1.3 μm.

Next, in the electroless plating layer forming step,
As shown in FIG. 2B, electroless Cu plating (plating solution build copper manufactured by Okuno Pharmaceutical Co., Ltd.) is applied to the entire surface of the substrate 11 to be laminated.
And a 0.7 μm-thick electroless Cu plating layer 17, 1
8 is formed. At this time, the electroless Cu plating layers 17, 1
The thickness of 8, relatively thin, 1μm or less strongly influenced by the surface roughness R ₃₀ of the resin insulating layers 13 and 14 thereunder. Therefore, the surface 1 of the electroless Cu plating layers 17 and 18
7A, 30 [mu] m between the ten point average roughness R ₃₀ of 18A is about approximately equal to the surface roughness R ₃₀ of the resin insulating layers 13 and 14 1.3
μm.

[0032] In this way the surface roughness R ₃₀ of the resin insulating layers 13 and 14, keep the equivalent desired surface roughness R ₃₀ of electroless Cu plating layers 17 and 18, an electroless Cu plating layer 1
Even if the layers 7 and 18 are thin, the electroless Cu plating layers 17 and 1
Surface 17A of 8, because the desired roughness R ₃₀ can be obtained in 18A, it is possible to reduce the time and cost. Moreover, since the resin insulating layers 13 and 14 are roughened in advance, the resin insulating layers 13 and 14 and the electroless Cu plating layer 1 are not roughened.
The adhesion strength with 7, 18 is sufficiently high.

Next, in the resist layer forming step, FIG.
As shown in (a), these electroless Cu plating layers 17,
18 is a photosensitive dry film (Nichigo Morton NIT) made of an acrylic resin (water-soluble acrylic).
225) 21 and 22 are respectively adhered to the entire surface.

Next, as shown in FIG. 3B, the attached dry films 21 and 22 are exposed using a mask (not shown) having a predetermined pattern, and then developed to form a wiring layer 3 and the like. Corresponding plating resist layer 2 of predetermined pattern
3, 24 are formed. At that time, especially the developer (Na ₂ CO ₃
(1.1 wt%), the plating resist layers 23 and 24, particularly the part where the width RB of the pattern is the narrowest (part shown in FIG. 3B), are easily peeled off by the pressure. In particular, as in the present embodiment, when the narrowest conductor gap X (20 μm) of the wiring layer is narrow, the plating resist layers 23 and 24 are likely to peel off or float.

However, in this embodiment, since the surface roughness R ₃₀ of the electroless Cu plating layers 17 and 18 is reduced to about 1.3 μm, the electroless Cu plating layers 17 and 18 and the plating resist layer 23 are formed. , 24 are sufficiently high. Therefore, in this step, the plating resist layers 23, 2
4 hardly peels off or floats from the electroless Cu plating layers 17, 18.

Next, in the wiring layer forming step, FIG.
As shown in (a), the electroless Cu plating is applied to the electroless Cu plating layer 1 exposed from the plating resist layers 23 and 24.
7 and 18, a 15 μm-thick electrolytic Cu plating layer 27,
28 are formed. At this time, the plating resist layers 23, 24
Has no peeling or floating, and has no electroless Cu plating layers 17 and 1
8, no short circuit occurs, and only the exposed electroless Cu plating layers 17 and 18
The u plating layers 27 and 28 can be formed.

Thereafter, the plating resist layers 23 and 24 are peeled off, and the exposed electroless Cu is removed by quick etching.
The plating layers 17 and 18 are removed, and wiring layers 3 and 4 are formed as shown in FIG. At this time, since the etching solution is sprayed on the entire surface, the exposed electroless Cu plating layers 17 and 18 are removed, and the electrolytic Cu plating layer 2 is removed.
A part of the surface of 7, 28 is also removed. However, since the electrolytic Cu plating layers 27 and 28 (thickness 15 μm) are formed sufficiently thicker than the electroless Cu plating layers 17 and 18 (thickness 0.7 μm), the wiring layers 3 and 4 are etched. It will not be removed. In this manner, the wiring layers 3 and 4 are formed on the resin insulating layers 13 and 14 of the substrate 11 to be laminated, and the printed wiring board 1 is completed.

In this embodiment, the surfaces 13A and 14A of the resin insulating layers 13 and 14 of the laminated substrate 11 are roughened with potassium permanganate. However, depending on the material of the resin insulating layer, for example, chromic acid may be used. It may be roughened by, for example, roughening.
The surfaces 13A and 14A may be polished and roughened. The surface roughness R ₃₀ of the resin insulating layers 13 and 14 is about 1.3 μm. However, if it is desired to further enhance the anchor effect between the resin insulating layers 13 and 14 and the wiring layer 3, the surface roughness R ₃₀ may be increased. it is also possible to further increase the R ₃₀ is. in this case,
In the electroless plating layer forming step, the surface 17A of the electroless plating layers 17, 18 is formed by thickening the electroless plating.
18A has a desired surface roughness, for example, R ₃₀ = 1.3 μm.

In the present embodiment, in the wiring layer forming step, after the plating resist layers 23 and 24 are peeled off, the wiring layers 3 and 4 are formed by spraying an etching solution in the same state. However, after the plating resist layers 23 and 24 are peeled off, the surfaces of the electrolytic Cu plating layers 27 and 28
Etching may be performed after forming a protective film such as i-plate or Sn-plate. In this case, since the surfaces of the electrolytic Cu plating layers 27 and 28 are protected from the etching solution by the protective film, the surfaces of the wiring layers 3 and 4 are not etched.

With respect to the wiring layer 3 of the printed wiring board 1, the narrowest conductor gap X is variously changed,
30 μm of the surfaces 17A, 18A of the u-plated layers 17, 18
And between 10-point average roughness R _30, the relationship between the yield after the resist layer forming step, examined as described below, and the results are shown in the graphs of FIGS. 5-8.

First, the wiring layer 3 has the narrowest conductor gap X.
The following investigation was conducted on the printed wiring board 1 having a conductor pattern having a thickness of 20 μm. That is, the surface 13A of the resin insulating layers 13 and 14, by appropriately changing the 14A 30 [mu] m between the ten point average roughness R ₃₀ of the surface 17A of the electroless Cu plating layers 17 and 18, between 18A 30 [mu] m of 1
For multiple samples the 0-point average roughness R ₃₀ variously varied to investigate the yield after the resist layer forming step. Then, based on these investigations, the electroless Cu plating layer 17,
Relation between 18 surface roughness R ₃₀ and yield after plating resist layers 23 and 24 formed of, summarized in the graph of FIG. The horizontal axis of the graph shown in FIG.
The 10-point average roughness R ₃₀ (μm) between 30 μm of the surfaces 17A and 18A of the surfaces 7 and 18 is shown.
The yield (%) after formation of 3, 24 is shown (the same applies to FIGS. 6 to 8).

In the sample in which the plating resist layers 23 and 24 were not peeled off or floated from the electroless plated layers 17 and 18 in the resist layer forming step, a short circuit was caused in the wiring layer forming step. The wiring layers 3 and 4 could be reliably formed without any occurrence. In contrast, any of the samples in which the plating resist layers 23 and 24 were peeled off or floated from the electroless plating layers 17 and 18 caused a short circuit.

As can be seen from this graph, the wiring layer 3
When the narrowest conductor gap is X = 20 μm, electroless Cu
Surface roughness R of plating 17, 18₃₀But B in the figure₁₀₀Indicated by
As shown in FIG.
%become. On the other hand, the surface roughness of the electroless Cu plating 17, 18
Sa R₃₀Is 0.97μm or more, the yield gradually increases
Begins to drop. In particular, the table of electroless Cu plating 17, 18
Surface roughness R₃₀Exceeds about 2 μm, the yield suddenly decreases.
Down. From this graph, it can be seen that after the resist layer forming step,
Cu plating to increase yield of 80% or more
Surface roughness R of layers 17 and 18₃₀And B in the figure₈₀As shown
And R₃₀It can be seen that it is sufficient to set the thickness to 1.96 μm or less.
To increase the yield to 90% or more, B₉₀so
As shown, R₃₀= 1.67 μm or less.
To make the yield almost 100%, B₁₀₀
As shown by R_{Three 0}= 0.97 μm or less
I understand.

Next, regarding the wiring layer 3 of the printed wiring board 1, the narrowest conductor gap X is set to 20 μm to 15 μm.
The printed wiring board changed to the above was also investigated in the same manner as the above investigation. That is, by appropriately changing the surface roughness R ₃₀ of the resin insulating layers 13 and 14, a resist layer forming step is performed for a number of samples in which the surface roughness R ₃₀ of the electroless Cu plating layers 17 and 18 is variously changed. Later the yield was investigated. Then, based on these studies, the relationship between the surface roughness R ₃₀ and yield after plating resist layer formed of an electroless Cu plating layers 17 and 18, are summarized in the graph of FIG.

As can be seen from this graph, when the narrowest conductor gap among the wiring layers is X = 15 μm, the surface roughness R ₃₀ of the electroless Cu plating layers 17 and 18 is about 0.9 μm or less, and the resist layer The yield after the forming process is increased. On the other hand, the surface roughness R ₃₀ of electroless Cu plating layer 17 is about 1.5μm or more, the yield after the plating resist layer formation, little.

The narrowest conductor gap is X = 20 μm
Compared to the above investigation, the electroless Cu plating layers 17 and 18
Surface roughness R₃₀If the value is not set to a small value, the yield
No. Also, the surface roughness of the electroless Cu plating layers 17 and 18
Sa R₃₀Exceeds about 0.9 μm, the yield is large.
Is decreasing. From this graph, it can be seen that the resist layer
To increase the yield after the formation process to 80% or more,
Surface roughness R of Cu plating layers 17 and 18₃₀And A in the figure₈₀
As shown by R₃₀= 0.90 μm or less
I understand. To increase the yield to 90% or more,
A in₉₀As shown by R₃₀= 0.76μm or less
To make the yield almost 100%,
A in₁₀₀As shown by R_{Three 0}= 0.50 μm or less
It turns out that we should do it.

Next, regarding the wiring layer 3 of the printed wiring board 1, the narrowest conductor gap X is set to 20 μm to 25 μm.
The following investigations were also conducted on the printed wiring board changed to the above in the same manner as the above investigations. That is, the resin insulating layer 13,
The yield after the resist layer forming step was investigated for a number of samples in which the surface roughness R ₃₀ of the electroless Cu plating layers 17 and 18 was variously changed by appropriately changing the surface roughness R ₃₀ of the 14. Then, based on these studies, the relationship between the surface roughness R ₃₀ and yield after plating resist layer formed of an electroless Cu plating layers 17 and 18, are summarized in the graph of FIG.

As can be seen from this graph, of the wiring layers
When the narrowest conductor gap is X = 25 μm, the electroless Cu
Surface roughness R of jacks 17, 18₃₀But C in the figure₁₀₀Indicated by
As described above, the yield is almost 100% at 1.35 μm or less.
become. On the other hand, the surface roughness of the electroless Cu plating 17, 18
R₃₀Is 1.35 μm or more, the yield gradually decreases.
Start dropping. However, the narrowest conductor gap in the wiring layer
Compared to the case where X = 20 μm, the electroless Cu plating 1
Surface roughness R of 7, 18₃₀Even if becomes large, the yield
The rate of decline is small. From this graph, the resist
In order to increase the yield after the layer formation process to 80% or more,
Surface roughness R of the decomposed Cu plating layers 17, 18₃₀In the figure
₈₀As shown by R₃₀= 5.32 μm or less
You can see that. In order to increase the yield to 90% or more,
C in the figure₉₀As shown by R₃₀= 3.91 μm or less
In order to make the yield almost 100%,
C in the figure₁₀₀As shown by R_{Three 0}= 1.35 μm or less
I know what I should do.

Next, for the wiring layer 3 of the printed wiring board 1, the narrowest conductor gap X is set to 20 μm to 32 μm.
The following investigations were also conducted on the printed wiring board changed to the above in the same manner as the above investigations. That is, the resin insulating layer 13,
The yield after the resist layer forming step was investigated for a number of samples in which the surface roughness R ₃₀ of the electroless Cu plating layers 17 and 18 was variously changed by appropriately changing the surface roughness R ₃₀ of the 14. Then, based on these studies, the relationship between the surface roughness R ₃₀ and yield after plating resist layer formed of an electroless Cu plating layers 17 and 18, are summarized in the graph of FIG.

As can be seen from this graph, when the narrowest conductor gap in the wiring layer is X = 32 μm, the surface roughness R ₃₀ of the electroless Cu platings 17 and 18 is as shown by D ₁₀₀ in the figure. 1.100 μm or less, almost 100% yield
become. On the other hand, when the surface roughness R ₃₀ of the electroless Cu platings 17 and 18 is 1.74 μm or more, the yield gradually starts to decrease. However, when the conductor gap is X = 15,2
Compared to the above investigations, which are 0.25 μm, electroless Cu
When the surface roughness R ₃₀ of the plating 17, 18 is increased,
The rate of decrease in yield is even smaller. According to this graph, in order to increase the yield after the resist layer forming step to 90% or more, the electroless Cu plating layers 17 and 1 are required.
The surface roughness R ₃₀ of No. 8 was calculated as R ₃₀ = D ₉₀ as shown by D ₉₀ in the figure.
It is understood that it is sufficient to set the thickness to 5.59 μm or less. Also, it can be seen that the yield can be made almost 100% by setting R _{30 to} 1.74 μm or less, as indicated by D ₁₀₀ in the figure.

From the above investigations, it can be seen that the surface roughness R ₃₀ of the electroless Cu plating layers 17 and 18 may be larger as the narrowest conductor gap X among the wiring layers is larger (FIG. 9). 5 to 8). In other words, in order to obtain a desired yield, the smaller the narrowest conductor gap X, the more the electroless C
It is necessary to reduce the surface roughness R ₃₀ of the u-plated layers 17 and 18, and conversely, if the narrowest conductor gap X increases,
Having a correlation with a surface roughness R ₃₀ of electroless Cu plating layer 17 and 18 may be larger. Further, in order to obtain a higher yield must be such kicked smaller surface roughness R ₃₀ of electroless Cu plating layers 17 and 18.

Therefore, after the resist layer forming step, 80
%, In order to obtain 90% and almost 100% of the yield surface roughness R ₃₀ of electroless Cu plating layers 17 and 18 required to obtain respectively, electroless and narrowest conductor gap X of the wiring layer We examined the relationship between the surface roughness R ₃₀ of the Cu-plated layer 17, 18. This will be described below with reference to the graphs in FIGS.

First, the yield after forming the plating resist layer
Of the narrowest conductor gap X when no
Surface roughness R of the decomposed Cu plating layers 17, 18₃₀Relationship with
And shown in FIG. The horizontal axis of this graph is
The narrowest conductor gap X (μm) is shown, and the vertical axis is electroless.
30μ of the surface 17A, 18A of the Cu plating layers 17, 18
10 points average roughness R between m₃₀(Μm) (FIG. 10 and FIG.
Same for 11. ). Note that A in FIG.₈₀, B₈₀, C
₈₀Are points A shown in FIGS.₈₀, B₈₀, C ₈₀Into it
Each is supported.

In this graph, the narrowest conductor gap is represented by X from the graphs (see FIGS. 5 to 7) obtained from the above investigation.
= 15,20,25 μm is a graph obtained by obtaining the surface roughness R ₃₀ when the yield becomes 80% and approximating based on these points (A ₈₀ , B ₈₀ , C ₈₀ ).
This graph shows the equation R ₃₀ = 0.061exp (0.18
X). According to this graph, electroless Cu plating 17, 18 was applied to the narrowest conductor gap X in the wiring layer.
Of the surface roughness R ₃₀ of the formula: R ₃₀ ≦ 0.061 exp (0.
18X), the yield after forming the plating resist layer can be 80% or more.

Next, the relationship between the narrowest conductor gap X and the surface roughness R ₃₀ of the electroless Cu plating layers 17 and 18 when the yield after forming the plating resist layer is 90% or more is shown in FIG. Shown in A ₉₀ , B ₉₀ , C ₉₀ ,
Each point D ₉₀ is, A _90, B ₉₀ shown in FIGS. 5 to 8, C _90, D
Each corresponds to ₉₀ . Also in this graph, the narrowest conductor gaps are obtained when the yield is 90% for each of X = 15, 20, 25, and 32 μm from the graphs (see FIGS. 5 to 8) obtained from the above investigation. Surface roughness R
₃₀ is a graph approximated based on these points (A ₉₀ , B ₉₀ , C ₉₀ , D ₉₀ ). This graph shows the equation R ₃₀ =
It is represented by 0.15exp (0.12X). From this graph, the surface roughness R ₃₀ of the electroless Cu platings 17 and 18 for the narrowest conductor gap X in the wiring layer is calculated by the equation R ₃₀
If the value satisfies ≦ 0.15exp (0.12X),
The yield after the plating resist layer is formed can be 90% or more.

Next, the relationship between the narrowest conductor gap X and the surface roughness R ₃₀ of the electroless Cu plating layers 17 and 18 when the yield after the formation of the plating resist layer is approximately 100% is shown in FIG. Shown in Note that A ₁₀₀ , B ₁₀₀ , C
₁₀₀ and D ₁₀₀ are represented by A ₁₀₀ , B ₁₀₀ ,
C ₁₀₀ and D ₁₀₀ respectively. This graph also
From each graph (see FIGS. 5 to 8) obtained from the above survey,
The narrowest conductor gap is X = 15,20,25,32μ
For each m, of the yield is almost 100% value to obtain the largest surface roughness R ₃₀ respectively, a graph which approximates these points _{(A 100, B 100, C} 100, D 100) to the original It is. This graph is based on the equation R ₃₀ = 2.0e
xp (0.071X). From this graph, it can be seen that the electroless Cu
The surface roughness R ₃₀ of the platings 17 and 18 is calculated by the following equation: R ₃₀ ≦ 2.0
If the value satisfies exp (0.071X), the yield after forming the plating resist layer can be almost 100%.

As described above, according to the graphs of FIGS.
The narrowest conductor gap in the wiring layer is in the range of 15 ≦ X ≦ 25.
In the box, R₃₀≤0.061exp (0.18X)
Surface roughness of electroless Cu plating 17, 18 to satisfy
R₃₀The yield after plating resist layer formation
80% or more can be obtained. In addition, the most
When the narrow conductor gap is in the range of 15 ≦ X ≦ 32, R
₃₀≤ 0.15exp (0.12X)
Surface roughness R of electrolytic Cu plating 17, 18₃₀Set
For example, a yield after plating resist layer formation of 90% or more is obtained.
Can be Also, between the narrowest conductors in the wiring layer
When the gap is in the range of 15 ≦ X ≦ 32, R ₃₀≤2.0ex
Electroless Cu plating to satisfy p (0.071X)
Surface roughness R of 17, 18₃₀If you set the plating resist
Almost 100% yield after the formation of
You.

As described above, according to the method of manufacturing a printed wiring board of the present embodiment, in the step of forming the electroless plating layer, the narrowest conductor gap X in the wiring layer is reduced by 30 μm on the surface. 10 point average roughness R ₃₀ is less than R ₃₀ ≦
0.061exp (0.18X), R ₃₀ ≦ 0.15ex
p (0.12X) and R ₃₀ ≦ 2.0exp (0.0
71X) so that the electroless Cu plating layers 17, 1
8 are formed.

Therefore, in the resist layer forming step,
When a plating resist layer having a predetermined pattern is formed, the adhesion strength between the plating resist layer and the electroless Cu plating layers 17 and 18 can be sufficiently increased. Therefore, in this step, a part of the plating resist layer is
Peeling or floating from 7, 18 can be suppressed. Therefore, in the subsequent wiring layer forming step, the electrolytic C
When forming the u-plated layers 27 and 28, the electrolytic Cu-plated layers 27 and 28 can be reliably formed only at predetermined positions, so that the wiring layers can be reliably formed and the printed wiring board can be manufactured. The yield at the time can be improved.

In the above, the present invention has been described with reference to the respective embodiments. However, the present invention is not limited to the above embodiments, and it can be said that the present invention can be appropriately modified and applied without departing from the gist thereof. Not even. For example, in the above-described embodiment, the wiring layer has a conductor pattern in which conductors are arranged on a comb at a fixed conductor gap X (see FIG. 1B).
The present invention can be applied to a wiring layer having a conductor pattern in which conductors are not arranged in parallel. Even in such a case, since the plating resist layer is most easily peeled off from the electroless Cu plating layer in the portion where the conductor gap is the narrowest, by applying the present invention, the peeling and floating of the plating resist layer in this portion are suppressed. And the occurrence of a short circuit in this portion can be prevented.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a printed wiring board according to a first embodiment, in which FIG. 1A is a plan view as viewed from a main surface side, and FIG. 1B is a partially enlarged view of a broken line portion in FIG.

FIGS. 2A and 2B are partially enlarged cross-sectional views illustrating a method for manufacturing a printed wiring board according to Embodiment 1, in which FIG. 2A illustrates a substrate to be laminated, and FIG. 2B illustrates a state in which an electroless Cu plating layer is formed.

FIGS. 3A and 3B are partially enlarged cross-sectional views illustrating a method for manufacturing the printed wiring board according to Embodiment 1, in which FIG. 3A illustrates a state in which a dry film is attached, and FIG. 3B illustrates a state in which a plating resist layer is formed. Is shown.

FIGS. 4A and 4B are partially enlarged cross-sectional views illustrating a method for manufacturing the printed wiring board according to Embodiment 1, in which FIG. 4A illustrates a state in which an electrolytic Cu plating layer is formed, and FIG. Is shown.

FIG. 5 is a graph showing a relationship between a surface roughness of electroless Cu plating and a yield in a conductor gap of 20 μm according to the first embodiment.

FIG. 6 is a graph showing a relationship between a surface roughness of electroless Cu plating and a yield in a conductor gap of 15 μm according to the first embodiment.

FIG. 7 is a graph showing the relationship between the surface roughness of electroless Cu plating at a conductor gap of 25 μm and the yield according to the first embodiment.

FIG. 8 is a graph showing the relationship between the surface roughness and the yield of electroless Cu plating at a conductor gap of 32 μm according to the first embodiment.

FIG. 9 is a graph showing a relationship between a conductor gap and a surface roughness of electroless Cu plating at a yield of 80% according to the first embodiment.

FIG. 10 is a graph showing a relationship between a conductor gap and a surface roughness of electroless Cu plating at a yield of 90% according to the first embodiment.

FIG. 11 is a graph showing a relationship between a conductor gap and a surface roughness of electroless Cu plating at a yield of 100% according to the first embodiment.

12A and 12B are partially enlarged cross-sectional views illustrating a method for manufacturing a printed wiring board according to a conventional technique, wherein FIG. 12A shows a state in which an electroless plating layer is formed on a resin insulating layer, and FIG. Shows the state where the dry film is attached on the layer,
(C) shows a state where a plating resist layer is formed.

13A and 13B are partially enlarged cross-sectional views illustrating a method for manufacturing a printed wiring board according to the related art, in which FIG. 13A illustrates a state where an electrolytic plating layer is formed, and FIG. 13B illustrates a state where a wiring layer is formed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Printed wiring board 3, 4 Wiring layer 11 Substrate to be laminated 13, 14 Resin insulating layer 13A, 14A (of resin insulating layer) Surface 17, 18 Electroless Cu plating layer 17A, 18A (Electroless Cu plating layer) Surface 23 , 24 plating resist layer 27, 28 electrolytic Cu plating layer X conductor gap

Claims (3)

[Claims] A first conductor gap formed on the resin insulating layer;
A method for manufacturing a printed wiring board comprising a wiring layer having a conductor pattern of (μm), comprising:
10 while the average roughness R ₃₀ is ([mu] m), in the range of 15 ≦ X ≦ 25, and electroless plating layer forming step of forming an electroless plating layer satisfying the formula R ₃₀ ≦ 0.061exp (0.18X) A resist layer forming step of forming a plating resist layer having a predetermined pattern on the electroless plating layer, and forming an electrolytic plating layer on the electroless plating layer exposed from the plating resist layer, and then forming the plating resist layer And a wiring layer forming step of forming a wiring layer by etching the electroless plating layer exposed after the peeling. 2. The method according to claim 1, wherein the narrowest conductor gap is X on the resin insulating layer.
A method for manufacturing a printed wiring board comprising a wiring layer having a conductor pattern of (μm), comprising:
10 while the average roughness R ₃₀ is ([mu] m), in the range of 15 ≦ X ≦ 32, and electroless plating layer forming step of forming an electroless plating layer satisfying the formula R ₃₀ ≦ 0.15exp (0.12X) A resist layer forming step of forming a plating resist layer having a predetermined pattern on the electroless plating layer, and forming an electrolytic plating layer on the electroless plating layer exposed from the plating resist layer, and then forming the plating resist layer And a wiring layer forming step of forming a wiring layer by etching the electroless plating layer exposed after the peeling. 3. The method according to claim 1, wherein the narrowest conductor gap is X on the resin insulating layer.
A method for manufacturing a printed wiring board comprising a wiring layer having a conductor pattern of (μm), comprising:
10 while the average roughness R ₃₀ is ([mu] m), in the range of 15 ≦ X ≦ 32, and electroless plating layer forming step of forming an electroless plating layer satisfying the formula R ₃₀ ≦ 2.0exp (0.071X) A resist layer forming step of forming a plating resist layer having a predetermined pattern on the electroless plating layer, and forming an electrolytic plating layer on the electroless plating layer exposed from the plating resist layer, and then forming the plating resist layer And a wiring layer forming step of forming a wiring layer by etching the electroless plating layer exposed after the peeling.