JP2000323712A - Power mos device with increased channel width and its manufacture - Google Patents

Power mos device with increased channel width and its manufacture

Info

Publication number
JP2000323712A
JP2000323712A JP2000117765A JP2000117765A JP2000323712A JP 2000323712 A JP2000323712 A JP 2000323712A JP 2000117765 A JP2000117765 A JP 2000117765A JP 2000117765 A JP2000117765 A JP 2000117765A JP 2000323712 A JP2000323712 A JP 2000323712A
Authority
JP
Japan
Prior art keywords
conductivity type
layer
gate
power mos
mos device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000117765A
Other languages
Japanese (ja)
Other versions
JP4804610B2 (en
Inventor
Dexter Elson Semple
センプル，デクスター・エルソン
Jun Zeng
ゼング・ジュン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intersil Corp
Original Assignee
Intersil Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intersil Corp filed Critical Intersil Corp
Publication of JP2000323712A publication Critical patent/JP2000323712A/en
Application granted granted Critical
Publication of JP4804610B2 publication Critical patent/JP4804610B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

Abstract

PROBLEM TO BE SOLVED: To reduce the on-resistance of a power MOS device without increasing the channel density below a gate area. SOLUTION: This power MOS device is equipped with a semiconductor substrate 101 and a 1st conduction type upper layer 102 provided on the substrate. This upper layer has on its top surface a plurality of well areas 103 of a 2nd conduction type a plurality of heavily doped source areas 104 of a 1st conductivity type, and a wavy part 202 which is formed by selective etching and parallel to the source areas. A wavy gate area 205 is formed including the wavy part 202 to increase channel width by the well areas 103, source areas 104, and gate area 205. For the manufacture, a striped mask is formed on the top surface 201 of the upper layer and etched to form a wavy top surface having a plurality of parallel wavy parts 203. The striped mask is removed and an insulating film 206 and conductive film 207 are formed on the upper-layer top surface 201 having the wavy surface layer to constitute the wavy gate area 205.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置に関し、
特に、増加したチャネルを有するパワーＭＯＳ装置及び
その製造方法に関する。The present invention relates to a semiconductor device,
In particular, it relates to a power MOS device having an increased channel and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】電池を電源とする携帯型電子通信装置の
近年の増加により、効率よく電力を運用する低電圧、低
オン抵抗のパワーＭＯＳＦＥＴｓの需要が増えている。
低電圧ＭＯＳＦＥＴｓにおいて、チャネル抵抗が、全オ
ン抵抗の大部分を占めている。このため、チャネル抵抗
を低下させることで、結果としてオン抵抗が小さくなる
ことになる。2. Description of the Related Art With the recent increase of portable electronic communication devices using a battery as a power source, demand for low-voltage, low-on-resistance power MOSFETs for efficiently operating power is increasing.
In low-voltage MOSFETs, the channel resistance accounts for the majority of the total on-resistance. Therefore, lowering the channel resistance results in lowering the on-resistance.

【０００３】図１は、従来のデバイス１００を示す概略
図である。デバイス１００は、ドープした上側層１０２
を有する基体１０１の上にプラナＤＭＯＳストライプ構
造を有する。上側層１０２は、ドープしたＰウエル領域
１０３と、重くドープしたＮ＋ソース領域１０４とを具
える。上側層１０２の上側表面１０５上にはゲート領域
１０６が形成されており、このゲート領域１０６は絶縁
層１０７と導電層１０８を具える。FIG. 1 is a schematic diagram showing a conventional device 100. Device 100 includes doped upper layer 102
Has a planar DMOS stripe structure on a substrate 101 having Upper layer 102 includes a doped P-well region 103 and a heavily doped N + source region 104. A gate region 106 is formed on an upper surface 105 of the upper layer 102, and the gate region 106 includes an insulating layer 107 and a conductive layer 108.

【０００４】[0004]

【発明が解決しようとする課題】公知のデバイス１００
においてチャネル抵抗を減らす一つの方法は、ゲート領
域１０６の下の層１０２の領域１０９のチャネル密度を
増やすことである。しかし、チャネル密度を増加させる
ことは、デバイスのジオメトリの減少、及び／又は、設
備及び技術を制限するような製造工程の変更を余儀なく
する。本発明は、パワーデバイスにおけるオン抵抗を小
さくするにあたり、チャネル密度を増加させるアプロー
チに代わる手段を提供することである。The known device 100
One way to reduce the channel resistance in is to increase the channel density in the region 109 of the layer 102 below the gate region 106. However, increasing the channel density necessitates a reduction in device geometry and / or a change in the manufacturing process that limits equipment and technology. The present invention provides an alternative to increasing the channel density in reducing the on-resistance in power devices.

【０００５】[0005]

【課題を解決するための手段】本発明の増加したチャネ
ル幅を有するパワーＭＯＳ装置は、半導体基体と、前記
基体に設けられた第１導電型にドープした上側層であっ
て、前記第１導電型と逆の第２導電型にドープした複数
のウエル領域を有する上側層と、前記上側層のエッチン
グした上側表面に設けた第１導電型の重くドープした複
数のソース領域とを具え、前記エッチングした上側表面
が前記ソース領域に横たわって設けた平行な波形部分
（Parallel Corrugation）を具えるパワーＭＯＳ装置に
おいて、ゲートが第１のソース領域と隣接する第２のソ
ース領域とを分離し、絶縁層と導電材料とを具えている
ため、前記波形部分により前記ウエル領域、ソース領域
及びゲート領域の下のチャネルの幅を増加することを特
徴とする。According to the present invention, there is provided a power MOS device having an increased channel width, comprising: a semiconductor substrate; and a first conductivity type doped upper layer provided on the substrate, wherein the first conductivity type upper layer is provided. An upper layer having a plurality of well regions doped with a second conductivity type opposite to a mold, and a plurality of heavily doped source regions of a first conductivity type provided on an etched upper surface of the upper layer; In a power MOS device having a parallel corrugation having an upper surface lying on the source region, the gate separates the first source region from the adjacent second source region, and the insulating layer And a conductive material, so that the width of the channel under the well region, the source region, and the gate region is increased by the corrugated portion.

【０００６】本発明はまた、増加したチャネル幅を有す
るパワーＭＯＳ装置の製造方法であって、当該方法が、
上側表面を有し、第１導電型にドープした上側層を具え
る半導体基体を提供し、前記上側表面上にストライプマ
スクを形成し、前記上側表面を選択的にエッチングする
工程を具え、前記上側表面が複数の平行な波形部分を具
え、前記ストライプマスクを除去し、前記波形の表面上
に絶縁層を形成し、前記絶縁層上に導電層を形成し、こ
れらの絶縁層及び導電層が前記上側表面の前記波形部分
に横たわって設けられた波形のゲートを構成し、第１導
電型と逆の第２導電型ドーパントを前記波形表面に注入
してドープしたウエル領域を前記上側層に形成し、前記
第１導電型のドーパントを前記ゲートに隣接する前記波
形表面部分に注入して重くドープした表面領域を前記上
側層内に形成することを特徴とする。The present invention is also a method of manufacturing a power MOS device having an increased channel width, the method comprising:
Providing a semiconductor substrate having an upper surface and having an upper layer doped with a first conductivity type, comprising the steps of: forming a stripe mask on the upper surface, and selectively etching the upper surface; The surface comprises a plurality of parallel corrugated portions, the stripe mask is removed, an insulating layer is formed on the corrugated surface, a conductive layer is formed on the insulating layer, and the insulating layer and the conductive layer are Forming a wave-shaped gate lying over the wavy portion of the upper surface, forming a well region in the upper layer doped with a dopant of a second conductivity type opposite to the first conductivity type by injecting the dopant into the wavy surface; Implanting the dopant of the first conductivity type into the corrugated surface portion adjacent to the gate to form a heavily doped surface region in the upper layer.

【０００７】好適には、本発明は、増加したチャネル幅
を有するパワーＭＯＳデバイスに関し、このデバイスは
半導体基体とこの基体上に設けた第１導電型のドープし
た上側層とを具える。上側層は、ソース領域に横たわっ
て設けた平行な波形部分を具える上側層のエッチングさ
れた上側表面に第１導電型と逆の第２導電型の複数のド
ープしたウエル領域と、第１導電型の複数の重くドープ
したソース領域とを具える。一のソース領域を他のソー
ス領域から分離するゲートは、絶縁層と導電層を具え
る。波形部分がゲートの下のチャネル幅を増加させる。[0007] Preferably, the present invention relates to a power MOS device having an increased channel width, the device comprising a semiconductor substrate and a doped upper layer of a first conductivity type provided on the substrate. The upper layer includes a plurality of doped well regions of a second conductivity type opposite to the first conductivity type on an etched upper surface of the upper layer having parallel corrugations provided overlying the source region; A plurality of heavily doped source regions of the mold. A gate that separates one source region from another source region includes an insulating layer and a conductive layer. The corrugations increase the channel width under the gate.

【０００８】好適には、本発明は、第１導電型にドープ
した上側層を有する半導体基体上に増加したチャネル幅
を有するパワーＭＯＳ装置の形成する方法に関する。ス
トライプマスクを前記上側層の上側表面上に形成して、
上側表面を選択的にエッチングして複数の平行な波形部
分を具える波形表面を形成する。前記ストライプマスク
を除去後に、絶縁層を波形表面に形成し、重なる該絶縁
層の上に導電層を形成して、波形ゲート領域を具える絶
縁層と導電層が上側表面の平行な波形部分を横たわって
形成される。第１導電型と逆の第２導電型ドーパントを
注入して、上側層内にドープしたウエル領域を形成し、
第１導電型のドーパントをゲートに隣接する波形表面部
分に注入して、上側層内に重くドープしたソース領域を
形成する。Preferably, the present invention relates to a method of forming a power MOS device having an increased channel width on a semiconductor body having an upper layer doped with a first conductivity type. Forming a stripe mask on the upper surface of the upper layer,
The upper surface is selectively etched to form a corrugated surface comprising a plurality of parallel corrugations. After removing the stripe mask, an insulating layer is formed on the corrugated surface, a conductive layer is formed on the overlapping insulating layer, and the insulating layer including the corrugated gate region and the conductive layer form a parallel corrugated portion on the upper surface. Formed lying down. Implanting a second conductivity type dopant opposite to the first conductivity type to form a doped well region in the upper layer;
A first conductivity type dopant is implanted into the corrugated surface portion adjacent to the gate to form a heavily doped source region in the upper layer.

【０００９】ゲート形成の代替方法では、上側層をエッ
チングして上側表面の波形部分にほぼ対応する平行な波
形部分を具えるフロアを有するゲートトレンチを形成す
る。トレンチのフロアとサイドウォールを、絶縁層でラ
イニングし、次いでトレンチを導電材料で実質的に充填
してゲートトレンチを形成する。第１導電型のドーパン
トをゲート領域に隣接する波形表面部分に注入し、それ
によって上側層内に重くドープしたソース領域を形成す
る。[0009] In an alternative method of gate formation, the upper layer is etched to form a gate trench having a floor with parallel corrugations substantially corresponding to corrugations on the upper surface. The floor and sidewalls of the trench are lined with an insulating layer, and then the trench is substantially filled with a conductive material to form a gate trench. A dopant of the first conductivity type is implanted into a portion of the corrugated surface adjacent to the gate region, thereby forming a heavily doped source region in the upper layer.

【００１０】本発明は、デバイスのジオメトリを減らす
ことなくパワーＭＯＳ装置のチャネル幅を増加させる手
段を提供する。チャネル幅は、その上にあるゲート領域
が波形表面を有する結果増加する。The present invention provides a means for increasing the channel width of a power MOS device without reducing the device geometry. The channel width increases as a result of the overlying gate region having a corrugated surface.

【００１１】[0011]

【発明の実施の形態】以下に本発明の実施の形態を添付
の図面を参照して説明する。チャネルとなる表面エリア
を増加させる波形シリコン表面の配列を図２（ａ）に示
す。基体１０１は、上側層１０２を具える。この上側層
の上側表面２０１は平坦平行部分２０３と傾斜部分２０
４とを交互に配置することによって規定される平行な波
形部分２０２を具える。横方向の所定の範囲において、
交互に配置した平行部分２０３と傾斜部分２０４とを有
する表面２０１の全幅は、図１に示す平坦な表面１０５
の幅よりも大きい。Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 2A shows the arrangement of the corrugated silicon surface that increases the surface area serving as a channel. Substrate 101 includes upper layer 102. The upper surface 201 of this upper layer comprises a flat parallel portion 203 and an inclined portion 20.
4 comprises a parallel corrugated portion 202 defined by interleaving. In a predetermined range in the horizontal direction,
The overall width of the surface 201 having alternating parallel portions 203 and inclined portions 204 is equal to the flat surface 105 shown in FIG.
Greater than the width of.

【００１２】図２（ｂ）は、デバイス２００を図１に示
す従来のデバイス１００のように示す図である。デバイ
ス２００は、ドープした上側層１０２を有する基体１０
１に形成され、上側層１０２は、Ｐウエル領域１０３と
重くドープしたＮ＋ソース領域１０４とを具える。基体
１０１はモノクリスタルシリコンのような半導体材料層
を具え、ドープした上側層１０２はエピタキシャル層で
あってもよい。上側層１０２とソース領域１０４はＮ導
電型として、ウエル領域１０３はＰ導電型として示され
ているが、Ｐ型とＮ型、Ｎ型とＰ型のように導電型は逆
であってもよい。FIG. 2B is a diagram showing the device 200 like the conventional device 100 shown in FIG. Device 200 includes substrate 10 having doped upper layer 102.
1, the upper layer 102 includes a P-well region 103 and a heavily doped N + source region 104. Substrate 101 comprises a layer of semiconductor material such as monocrystalline silicon, and doped upper layer 102 may be an epitaxial layer. Although the upper layer 102 and the source region 104 are shown as having an N conductivity type and the well region 103 is being shown as having a P conductivity type, the conductivity types may be opposite, such as P type and N type, and N type and P type. .

【００１３】図２（ｂ）はまた、上側表面２０１を示し
ており、上側表面２０１は、平坦な平行部分２０３と傾
斜部分２０４とを交互に配置することによって規定され
る平行な波形部分２０２を具える。隣接するソース領域
１０４の間にまたがって設けられたゲート２０５は、絶
縁層２０６と、その上にある導電層２０７とを具え、波
形上側表面２０１上に形成されている。ウエル領域１０
３、ソース領域１０４及びゲート層２０６と２０７はす
べて上側表面２０１と同じ形をしている。FIG. 2 (b) also shows an upper surface 201, which defines a parallel corrugated portion 202 defined by alternating flat parallel portions 203 and inclined portions 204. Equipped. A gate 205 provided between adjacent source regions 104 includes an insulating layer 206 and a conductive layer 207 thereon, and is formed on the upper wavy surface 201. Well region 10
3. The source region 104 and the gate layers 206 and 207 all have the same shape as the upper surface 201.

【００１４】図３（ａ）〜（ｅ）に、パワーＭＯＳ装置
の製造方法を示す。図３（ａ）に示すように、ストライ
プマスクＳＭを基体１０１の上側層１０２上に形成す
る。マスクされた上側層１０２を選択的にエッチングす
ることによって、平坦な平行部分２０３と傾斜部分２０
４とを交互に配置することによって規定される平行な波
形部分２０２が形成される。FIGS. 3A to 3E show a method of manufacturing a power MOS device. As shown in FIG. 3A, a stripe mask SM is formed on the upper layer 102 of the base 101. By selectively etching the masked upper layer 102, the flat parallel portions 203 and the sloping portions 20 are formed.
4 alternately form a parallel corrugated portion 202 defined.

【００１５】例えば、カーライルその他（Carlile）の
「制御可能なサイドウォール角を有するシリコンのトレ
ンチエッチング（Trench Etches in Silicon with cont
rollable Sidewall Angles）」、ジェイ．エレクトロケ
ム．ソサエティ（J. Electrochem. Soc.）の「固体状態
の科学技術（SOLID-STATE SCIENCE AND TECHNOLOG
Y）」、１９８８年発行の２０５８〜２０６４ページに
示されているように、層１０２のエッチングは高さｈと
エッチング角θの波形部分２０２を形成するように制御
される。水酸化カリウムプロパノールやエチレンジアミ
ン−ピロカテコール混合物を反応物として使用するシリ
コンの非等方性エッチングが、ビーン「選択装置に関す
るアメリカ電気・電子通信学会会報（IEEE TRANSACTIONS
ON ELECTION DEVICES）」、１９７８年Ｖｏｌ．ＥＤ−
２５、Ｎｏ．１０の１８５〜１１９３ページに示されて
いる。For example, Carlile et al., “Trench Etches in Silicon with cont.
rollable Sidewall Angles) ", Jay. Electrochem. Society (J. Electrochem. Soc.) "SOLID-STATE SCIENCE AND TECHNOLOG
Y) ", 1988, pp. 2058-2064, the etching of layer 102 is controlled to form a corrugated portion 202 of height h and etching angle θ. Anisotropic etching of silicon using potassium hydroxide propanol or an ethylenediamine-pyrocatechol mixture as a reactant is a bean “IEEE TRANSACTIONS
ON ELECTION DEVICES) ", 1978, Vol. ED-
25, no. 10 pages 185-1193.

【００１６】図３（ｃ）は、図３（ｂ）のＡ−Ａ’線に
おける断面図であり、ストライプマスクＳＭを除去し、
ゲート２０５を上側層１０２上に波形部分２０２を横切
って形成した後の図である。図３（ｄ）は、図３（ｃ）
のＢ−Ｂ’線における断面図であり、ゲート２０５を構
成する絶縁層２０６と導電層２０７を示す。層２０６及
び２０７は共に波形部分２０２と同じ形をしている。FIG. 3C is a cross-sectional view taken along the line AA ′ of FIG. 3B, and the stripe mask SM is removed.
FIG. 11 is a view after a gate 205 is formed on the upper layer 102 across the corrugated portion 202. FIG. 3D shows the state shown in FIG.
3 is a cross-sectional view taken along line BB ′ of FIG. 3, showing an insulating layer 206 and a conductive layer 207 forming a gate 205. Both layers 206 and 207 have the same shape as corrugated portion 202.

【００１７】図３（ｅ）は、図３（ｄ）のＣ−Ｃ’線に
おける断面図であり、ホウ素などのドーパントを上側層
１０２へ注入して、Ｐウエル領域１０３を形成し、砒素
やリンなどのドーパントをゲート２０５に隣接する層１
０２に注入してＮ＋ソース領域１０４を形成した後の状
態を示す。図３（ａ）〜（ｅ）に示すマスキング、ドー
ピング他、一連の製造工程における変形例は、本発明の
範囲内に含まれる。FIG. 3E is a cross-sectional view taken along the line CC ′ of FIG. 3D. A dopant such as boron is implanted into the upper layer 102 to form a P-well region 103, and arsenic or arsenic is formed. Layer 1 adjacent to gate 205 with a dopant such as phosphorus
2 shows a state after the N + source region 104 is formed by implanting the N + source region 104. The masking, doping, and other modifications in the series of manufacturing steps shown in FIGS. 3A to 3E are included in the scope of the present invention.

【００１８】図４は、従来のデバイス１００に比較して
本発明のデバイス２００によって得られたチャネル幅の
増加を示す； デバイス１００の場合： 幅w=a1+a2+a3+a4+a5 デバイス２００の場合： 幅w'=a1+a2/cosθ+a3+a4/cosθ+a5 ０°＜θ＜９０°で高さｈの場合： 幅w=a1+2h/tanθ+a3+a5 幅w'=a1+2h/sinθ+a3+a5 w'-w=2h(1/sin1θ-1/tan1θ) θ＝４５°の場合： (w'-w)/w=0.828(h/w) θ＝６０°の場合： (w'-w)/w=1.15(h/w)FIG. 4 shows the increase in channel width obtained by device 200 of the present invention as compared to conventional device 100; for device 100: width w = a1 + a2 + a3 + a4 + a5 device 200 In the case of: width w '= a1 + a2 / cosθ + a3 + a4 / cosθ + a5 0 ° <θ <90 ° and height h: width w = a1 + 2h / tanθ + a3 + a5 width w ′ = a1 + 2h / sinθ + a3 + a5 w'-w = 2h (1 / sin 1 θ-1 / tan 1 θ) When θ = 45 °: (w'-w) /w=0.828 (h / w) When θ = 60 °: (w'-w) /w=1.15 (h / w)

【００１９】図４に示すように、デバイス１００と比較
したデバイス２００のチャネル幅の増加は（ｗ’−ｗ）
／ｗであり、波形部分の平坦部分と傾斜部分の間で測定
される波形部分の幅の比率（ｈ／ｗ）及びエッチング角
θに依存している。所定の高さｈでａ１＝ａ２＝ａ３＝
ａ４＝ａ５の場合、エッチング角θが４５°であれば、
デバイス１００と比較してデバイス２００のチャネル幅
はおよそ１７％増加する。エッチング角θが６０°であ
れば、他の状態が一定であれば、チャネル幅により大き
な改良があり、およそ４０％増加する。チャネル幅の増
加に伴って、これに対応するオン抵抗が減少する。本発
明のこれらの利点は、水平チャネルＭＯＳＦＥＴ及び垂
直チャネルＭＯＳＦＥＴの双方に適用可能である。As shown in FIG. 4, the increase in channel width of device 200 as compared to device 100 is (w'-w)
/ W, which depends on the ratio (h / w) of the width of the waveform portion measured between the flat portion and the inclined portion of the waveform portion and the etching angle θ. At a predetermined height h, a1 = a2 = a3 =
When a4 = a5 and the etching angle θ is 45 °,
The channel width of device 200 is increased by approximately 17% compared to device 100. If the etching angle θ is 60 °, and the other conditions remain constant, there is a greater improvement in channel width, increasing by about 40%. As the channel width increases, the corresponding on-resistance decreases. These advantages of the present invention are applicable to both horizontal and vertical channel MOSFETs.

【００２０】図５（ａ）は、半導体ウエハ５０１を示し
ており、ウエハ５０１はドープした上側層５０３を有す
る基体５０２を具える。上側層５０３内にはドープした
Ｐウエル領域５０４と重くドープしたＮ＋ソース領域５
０５が形成されている。ウエハの上側表面５０６は、平
坦平行部分５０７と傾斜部分５０８とを交互に配置して
規定した波形部分を具える。ゲートトレンチ５０９が、
表面５０６にエッチングされており、このゲートトレン
チは上側表面５０６の波形部分に対応する波形部分を具
える。FIG. 5A shows a semiconductor wafer 501 comprising a substrate 502 having a doped upper layer 503. In upper layer 503, doped P well region 504 and heavily doped N + source region 5
05 is formed. The upper surface 506 of the wafer comprises a wavy portion defined by alternating flat parallel portions 507 and inclined portions 508. The gate trench 509 is
Etched in surface 506, the gate trench has corrugations corresponding to the corrugations in upper surface 506.

【００２１】図５（ｂ）及び（ｃ）は、図５（ａ）に示
す本発明のトレンチゲートＭＯＳＦＥＴ５００のＡ−
Ａ’線、Ｂ−Ｂ’線における各断面図を示す。図５
（ａ）に示す特徴に加えて、図５（ｂ）及び（ｃ）に示
すデバイス５００は、ゲートトレンチ５０９をライニン
グする絶縁層５１１を具える。このトレンチ５０９は導
電材料５１２で実質的に満たされている。図５（ｂ）及
び（ｃ）は、トレンチ５０９のフロアの対応する部分５
１３ａ及び５１３ｂの深さの変化と、波形表面５０６の
平行部分５０６ａ及び５０６ｂの高さの変化を示す。FIGS. 5B and 5C are sectional views of the trench gate MOSFET 500 of the present invention shown in FIG.
The sectional views along line A 'and line BB' are shown. FIG.
In addition to the features shown in (a), the device 500 shown in FIGS. 5 (b) and (c) comprises an insulating layer 511 lining the gate trench 509. The trench 509 is substantially filled with the conductive material 512. FIGS. 5B and 5C show the corresponding part 5 of the floor of the trench 509.
13a and 513b, and the height of the parallel portions 506a and 506b of the corrugated surface 506 are shown.

【００２２】増加したチャネル幅を有するパワーＭＯＳ
装置は、半導体基体と、基体上に設けられた第１導電型
にドープした上側層とを具える。上側層はエッチングさ
れた上側表面に、第１導電型と逆の第２導電型にドープ
した複数のウエル領域と、第１導電型に重くドープした
複数のソース領域とを具えており、この上側層は、ソー
ス領域に横たわって設けられた平行な波形部分を具え
る。一の領域と他の領域とを分離するゲートは、絶縁層
と導電材料層を具える。波形部分が、ゲート領域、ウエ
ル領域及びソース領域の下のチャネルの幅を増加させ
る。第１導電型にドープした上側層を有する半導体基体
上に増加したチャネル幅を有するパワーＭＯＳ装置の製
造方法において、ストライプマスクを上側層の上側表面
に形成し、この上側表面を、選択的にエッチングして複
数の平行な波形部分を具える波形表面を形成する。スト
ライプマスクの除去に次いで、絶縁層を波形表面上に形
成し、この絶縁層上に導電層を形成し、これらの絶縁層
及び導電層で上側表面の平行な波形部分に横たわって設
けた波形ゲート領域を構成する。第１導電型と逆の第２
導電型のドーパントを注入して、上側層内にドープした
ウエル領域を形成し、第１導電型のドーパントを、ゲー
トに隣接する波形表面部分に注入して、上側層内に重く
ドープしたソース領域を形成する。Power MOS with increased channel width
The device comprises a semiconductor substrate and a first conductivity type doped upper layer provided on the substrate. The upper layer has, on the etched upper surface, a plurality of well regions doped to a second conductivity type opposite to the first conductivity type and a plurality of source regions doped heavily to the first conductivity type. The layer comprises parallel corrugations lying over the source region. A gate that separates one region from another region includes an insulating layer and a layer of conductive material. The corrugations increase the width of the channel below the gate, well and source regions. In a method of manufacturing a power MOS device having an increased channel width on a semiconductor substrate having an upper layer doped with a first conductivity type, a stripe mask is formed on an upper surface of the upper layer, and the upper surface is selectively etched. To form a corrugated surface comprising a plurality of parallel corrugated portions. Subsequent to the removal of the stripe mask, an insulating layer is formed on the corrugated surface, a conductive layer is formed on the insulating layer, and the insulating layer and the conductive layer are provided so as to lie on a parallel wavy portion of the upper surface. Configure the area. The second, opposite to the first conductivity type
Implanting a dopant of a conductivity type to form a doped well region in the upper layer, and implanting a dopant of a first conductivity type in a corrugated surface portion adjacent to the gate to form a heavily doped source region in the upper layer. To form

【図面の簡単な説明】[Brief description of the drawings]

【図１】 図１は、プラナＤＭＯＳ構造を有する従来の
装置を示す斜視図である。FIG. 1 is a perspective view showing a conventional device having a planar DMOS structure.

【図２】 図２（ａ）は半導体ウエハの波形エッチング
した上側表面を示す斜視図であり、図２（ｂ）は本発明
の増加したチャネル幅を有するパワーＤＭＯＳ装置を示
す斜視図である。FIG. 2 (a) is a perspective view showing a corrugated etched upper surface of a semiconductor wafer, and FIG. 2 (b) is a perspective view showing a power DMOS device having an increased channel width according to the present invention.

【図３】 図３（ａ）〜（ｅ）は、本発明のパワーＭＯ
Ｓ装置の製造工程を示す図である。3 (a) to 3 (e) show a power MO of the present invention.
It is a figure which shows the manufacturing process of S apparatus.

【図４】 図４は、従来の装置と比較した本発明の装置
によって提供されるチャネル幅の改良を示す図である。FIG. 4 is a diagram illustrating the improvement in channel width provided by the device of the present invention as compared to conventional devices.

【図５】 図５は、本発明のトレンチパワーＭＯＳ装置
を製造するための波形上側表面とゲートトレンチを有す
る半導体ウエハの斜視図である。図５（ｂ）及び図５
（ｃ）は、図５（ａ）に示すウエハにおいて形成される
トレンチゲート装置の断面図である。FIG. 5 is a perspective view of a semiconductor wafer having a corrugated upper surface and a gate trench for manufacturing a trench power MOS device of the present invention. 5 (b) and 5
FIG. 5C is a sectional view of the trench gate device formed on the wafer shown in FIG.

【符号の説明】[Explanation of symbols]

１００、２００ デバイス １０１、５０２ 基体 １０２、５０３ 上側層 １０３、５０４ Ｐウエル領域 １０４、５０５ Ｎ＋ソース領域 １０５、２０１、５０６ 上側表面 １０６ ゲート領域 １０７、２０６ 絶縁層 １０８、２０７ 導電層 １０９ 領域 ２０２ 波形部分 ２０３、５０７ 平坦平行部分 ２０４、５０８ 傾斜部分 ２０５ ゲート ５０１ 半導体ウエハ ５０９ ゲートトレンチ 100, 200 Device 101, 502 Base 102, 503 Upper layer 103, 504 P well region 104, 505 N + source region 105, 201, 506 Upper surface 106 Gate region 107, 206 Insulating layer 108, 207 Conductive layer 109 region 202 Waveform portion 203, 507 Flat parallel portion 204, 508 Inclined portion 205 Gate 501 Semiconductor wafer 509 Gate trench

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/336 Ｈ０１Ｌ 29/78 ６５８Ｂ ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI theme coat ゛ (Reference) H01L 21/336 H01L 29/78 658B

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】 半導体基体と、前記基体上に設けられた
第１導電型にドープした上側層とを具え、前記上側層の
エッチングされた上側表面に、第１導電型と逆の第２導
電型にドープした複数のウエル領域と、前記第１導電型
の重くドープしたソース領域とを具え、前記エッチング
した上側表面が前記ソース領域を横たわって設けられた
平行な波形部分を具える増加したチャネル幅を有するパ
ワーＭＯＳ装置において、ゲートが、一のソース領域を
隣接する第２のソース領域から分離しているとともに、
絶縁層と導電材料を具えており、前記波形部分が前記ウ
エル領域、ソース領域及びゲート領域の下のチャネルの
幅を増加させることを特徴とするパワーＭＯＳ装置。1. A semiconductor substrate and an upper layer doped on a first conductivity type provided on the substrate, wherein an etched upper surface of the upper layer has a second conductivity opposite to the first conductivity type. An increased channel comprising a plurality of well-doped well regions and a heavily doped source region of the first conductivity type, wherein the etched upper surface comprises a parallel corrugation provided over the source region. In a power MOS device having a width, a gate separates one source region from an adjacent second source region,
A power MOS device comprising an insulating layer and a conductive material, wherein the corrugations increase the width of a channel below the well region, source region, and gate region. 【請求項２】 請求項１に記載のパワーＭＯＳ装置にお
いて、前記第１導電型がＮ型で前記第２導電型がＰ型で
あり、前記ゲートが前記エッチングされた上側表面に設
けられ、前記上側表面から絶縁層で分離された導電材料
層を具え、前記導電材料層及び絶縁層が前記上側表面と
同形であることを特徴とするパワーＭＯＳ装置。2. The power MOS device according to claim 1, wherein said first conductivity type is N-type, said second conductivity type is P-type, and said gate is provided on said etched upper surface; A power MOS device comprising a conductive material layer separated from an upper surface by an insulating layer, wherein the conductive material layer and the insulating layer have the same shape as the upper surface. 【請求項３】 請求項２に記載のパワーＭＯＳ装置にお
いて、前記ゲートが、前記上側層へ延在するゲートトレ
ンチを具え、前記トレンチが前記絶縁層でライニングし
たフロアとサイドウォールを有し、前記トレンチが実質
的に前記導電材料で満たされており、前記トレンチフロ
アが前記ソース領域にまたがって設けられ、前記上側表
面にある前記波形部分にほぼ対応した平行な波形部分を
具え、前記基体がモノクリスタルシリコンを具えること
を特徴とするパワーＭＯＳ装置。3. The power MOS device according to claim 2, wherein said gate comprises a gate trench extending to said upper layer, said trench having a floor and a side wall lined with said insulating layer, A trench is substantially filled with the conductive material, the trench floor is provided across the source region, and comprises a corrugated portion substantially corresponding to the corrugated portion on the upper surface, wherein the substrate is monolithic. A power MOS device comprising crystal silicon. 【請求項４】 請求項１に記載のパワーＭＯＳ装置にお
いて、前記導電材料が高くドープしたポリシリコンを具
え、前記絶縁層が二酸化シリコンを具え、前記複数のソ
ース領域が平行ストライプ構造をなし、前記装置がパワ
ーＭＯＳＦＥＴ、絶縁ゲートバイポーラトランジスタ、
ＭＯＳ制御サイリスタ及びアキュムレーションＦＥＴで
構成される群から選択されることを特徴とするパワーＭ
ＯＳ装置。4. The power MOS device of claim 1, wherein said conductive material comprises highly doped polysilicon, said insulating layer comprises silicon dioxide, and said plurality of source regions form a parallel stripe structure. The device is a power MOSFET, an insulated gate bipolar transistor,
A power M selected from the group consisting of a MOS control thyristor and an accumulation FET;
OS device. 【請求項５】 上側表面を有し、第１導電型にドープし
た上側層を具える半導体基体を提供するステップと、前
記上側表面上にストライプマスクを形成するステップ
と、前記上側表面を選択的にエッチングするステップ
と、を具える増加したチャネル幅を有するパワーＭＯＳ
装置の製造方法において、上側表面が複数の平行な波形
部分を具え、前記ストライプマスクを除去し、前記波形
の表面上に絶縁層を形成し、前記絶縁層上に導電層を形
成し、前記絶縁層及び導電層が前記上側表面の前記波形
部分に横たわって設けられた波形ゲートを構成し、第１
導電型と逆の第２の導電型ドーパントを前記波形表面に
注入してドープしたウエル領域を前記上側層に形成し、
前記第１導電型のドーパントを前記ゲートに隣接する前
記波形表面部分に注入して重くドープした表面領域を前
記上側層内に形成することを特徴とするパワーＭＯＳ装
置の製造方法。5. Providing a semiconductor body having an upper surface and having an upper layer doped with a first conductivity type, forming a stripe mask on the upper surface, and selectively forming the upper surface. Power MOS with increased channel width, comprising:
The method of manufacturing a device, wherein the upper surface includes a plurality of parallel corrugated portions, the stripe mask is removed, an insulating layer is formed on the corrugated surface, and a conductive layer is formed on the insulating layer. A first layer and a conductive layer forming a corrugated gate provided overlying the corrugated portion on the upper surface;
Implanting a dopant of a second conductivity type opposite to the conductivity type into the corrugated surface to form a doped well region in the upper layer;
A method of manufacturing a power MOS device, comprising: implanting a dopant of the first conductivity type into the corrugated surface portion adjacent to the gate to form a heavily doped surface region in the upper layer. 【請求項６】 請求項５に記載の方法において、前記第
１導電型がＮ型で第２導電型がＰ型であり、前記基体が
モノクリスタルシリコンを具え、前記導電層が高くドー
プしたポリシリコンを具え、前記絶縁層が二酸化シリコ
ンを具えることを特徴とするパワーＭＯＳ装置の製造方
法。6. The method of claim 5, wherein said first conductivity type is N-type and said second conductivity type is P-type, said substrate comprises monocrystalline silicon, and said conductive layer is highly doped poly. A method of manufacturing a power MOS device, comprising silicon, wherein said insulating layer comprises silicon dioxide. 【請求項７】 請求項５に記載の方法において、前記ゲ
ート領域及び前記ソース領域が平行ストライプ構造をな
し、第１導電型の前記ドーパントが砒素又はリンであ
り、第２導電型の前記ドーパントがホウ素であることを
特徴とするパワーＭＯＳ装置の製造方法。7. The method of claim 5, wherein the gate region and the source region form a parallel stripe structure, the dopant of the first conductivity type is arsenic or phosphorus, and the dopant of the second conductivity type is A method for manufacturing a power MOS device, wherein the method is boron. 【請求項８】 上側表面を有し、第１導電型にドープし
た上側層を具える半導体基体を提供するステップと、前
記上側表面上にストライプマスクを形成するステップ
と、前記上側表面を選択的にエッチングするステップ
と、を具える増加したチャネル幅を有するパワーＭＯＳ
装置の製造方法において、上側表面が、複数の平行な波
形部分を具え、前記ストライプマスクを除去し、前記上
側層にゲートトレンチをエッチングし、前記ゲートトレ
ンチが前記平行な波形部分を横たわって設けられ、前記
上側表面における前記波形部分に実質的に対応している
平行な波形部分を具えるフロアを具え、前記トレンチの
サイドウォール及びフロアを絶縁層に沿ってライニング
し、前記トレンチを導電材料で実質的に満たしてトレン
チゲートを形成し、第１導電型と逆の第２導電型のドー
パントを前記波形表面に注入して、前記上側層にドープ
したウエル領域を形成し、前記第１導電型のドーパント
を前記トレンチゲートに隣接する前記波形表面部分に注
入して、前記上側層に重くドープしたソース領域を形成
することを特徴とするパワーＭＯＳ装置の製造方法。8. Providing a semiconductor substrate having an upper surface and having an upper layer doped with a first conductivity type, forming a stripe mask on the upper surface, selectively etching the upper surface. Power MOS with increased channel width, comprising:
In a method of manufacturing a device, an upper surface includes a plurality of parallel corrugations, removing the stripe mask, etching a gate trench in the upper layer, wherein the gate trench is provided overlying the parallel corrugations. A floor having parallel corrugations substantially corresponding to the corrugations on the upper surface, lining sidewalls and floors of the trenches along an insulating layer, and substantially trenching the trenches with a conductive material. Forming a trench gate, implanting a dopant of a second conductivity type opposite to the first conductivity type into the corrugated surface to form a doped well region in the upper layer, Implanting a dopant into the corrugated surface portion adjacent to the trench gate to form a heavily doped source region in the upper layer. Method of manufacturing a power MOS devices that. 【請求項９】 請求項８に記載の方法において、前記第
１導電型がＮ型で第２導電型がＰ型であって、前記基体
がモノクリスタルシリコンを具え、前記導電層が高くド
ープしたポリシリコンを具え、前記絶縁層が二酸化シリ
コンを具えることを特徴とするパワーＭＯＳ装置の製造
方法。9. The method of claim 8, wherein said first conductivity type is N-type and said second conductivity type is P-type, said substrate comprises monocrystalline silicon, and said conductive layer is highly doped. A method for manufacturing a power MOS device, comprising polysilicon, wherein said insulating layer comprises silicon dioxide. 【請求項１０】 請求項９に記載の方法において、前記
トレンチゲート及び前記ソース領域が平行ストライプ構
造をなし、第１導電型の前記ドーパントが砒素又はリン
であり、第２導電型の前記ドーパントがホウ素であるこ
とを特徴とするパワーＭＯＳ装置の製造方法。10. The method of claim 9, wherein the trench gate and the source region form a parallel stripe structure, the dopant of the first conductivity type is arsenic or phosphorus, and the dopant of the second conductivity type is A method for manufacturing a power MOS device, wherein the method is boron.
JP2000117765A 1999-04-30 2000-04-19 Power MOS device having increased channel width and manufacturing method thereof Expired - Fee Related JP4804610B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/303270 1999-04-30
US09/303,270 US6218701B1 (en) 1999-04-30 1999-04-30 Power MOS device with increased channel width and process for forming same

Publications (2)

Publication Number Publication Date
JP2000323712A true JP2000323712A (en) 2000-11-24
JP4804610B2 JP4804610B2 (en) 2011-11-02

Family

ID=23171290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000117765A Expired - Fee Related JP4804610B2 (en) 1999-04-30 2000-04-19 Power MOS device having increased channel width and manufacturing method thereof

Country Status (4)

Country Link
US (2) US6218701B1 (en)
EP (1) EP1049174A2 (en)
JP (1) JP4804610B2 (en)
KR (1) KR100727416B1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2010110246A1 (en) * 2009-03-25 2012-09-27 ローム株式会社 Semiconductor device
JP2013077761A (en) * 2011-09-30 2013-04-25 Toshiba Corp Silicon carbide semiconductor device
JP2015012294A (en) * 2013-07-02 2015-01-19 ゼネラル・エレクトリック・カンパニイ Metal-oxide-semiconductor (mos) devices with increased channel periphery and methods of manufacturing the same
US20180151720A1 (en) * 2016-11-30 2018-05-31 Alpha And Omega Semiconductor Incorporated Folded channel trench mosfet

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002141507A (en) * 2000-10-31 2002-05-17 Mitsubishi Electric Corp Semiconductor device and its manufacturing method
US20040036131A1 (en) * 2002-08-23 2004-02-26 Micron Technology, Inc. Electrostatic discharge protection devices having transistors with textured surfaces
US7170118B2 (en) * 2003-08-01 2007-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Field effect transistor (FET) device having corrugated structure and method for fabrication thereof
KR100605499B1 (en) 2004-11-02 2006-07-28 삼성전자주식회사 MOS transistor having recessed gate electrode method of fabricating the same
KR100608377B1 (en) 2005-05-02 2006-08-08 주식회사 하이닉스반도체 Method for fabricating cell transistor of memory device
US20060255412A1 (en) * 2005-05-13 2006-11-16 Nirmal Ramaswamy Enhanced access devices using selective epitaxial silicon over the channel region during the formation of a semiconductor device and systems including same
ITTV20060092A1 (en) * 2006-05-31 2007-12-01 Luca Toncelli PROCEDURE FOR THE MANUFACTURE OF MANUFACTURED ARTICLES IN GRANULATE CONGLOMERATE OF STONE MATERIAL AND POLYESTER RESIN IN THE FORM OF SHEETS OR BLOCKS.
TW200843105A (en) * 2007-04-25 2008-11-01 Promos Technologies Inc Vertical transistor and method for preparing the same
IT1401729B1 (en) * 2010-06-17 2013-08-02 St Microelectronics Srl PROCEDURE FOR THE MANUFACTURE OF INTEGRATED POWER DEVICES WITH SURFACE CORRUGATIONS AND INTEGRATED POWER DEVICE WITH SURFACE CORRUGATIONS
KR101194919B1 (en) 2010-07-06 2012-10-25 에스케이하이닉스 주식회사 Semiconductor device and method for forming the same
US9024328B2 (en) 2013-07-02 2015-05-05 General Electric Company Metal-oxide-semiconductor (MOS) devices with increased channel periphery and methods of manufacture
CN104009088B (en) * 2014-05-29 2017-04-12 西安电子科技大学 Grid-controlled vertical double-diffusion metal-oxide semiconductor field effect transistor
TWI679768B (en) * 2019-01-14 2019-12-11 力晶積成電子製造股份有限公司 Stepped device and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61161766A (en) * 1985-01-10 1986-07-22 Matsushita Electronics Corp Longitudinal mosfet
JPH0311765A (en) * 1989-06-09 1991-01-21 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPH0323674A (en) * 1989-06-21 1991-01-31 Mitsubishi Electric Corp Semiconductor device
JPH0575121A (en) * 1991-09-18 1993-03-26 Fujitsu Ltd Semiconductor device
JPH05347414A (en) * 1992-06-12 1993-12-27 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH08264764A (en) * 1995-03-22 1996-10-11 Toshiba Corp Semiconductor device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4234887A (en) * 1979-05-24 1980-11-18 International Business Machines Corporation V-Groove charge-coupled device
US4393391A (en) * 1980-06-16 1983-07-12 Supertex, Inc. Power MOS transistor with a plurality of longitudinal grooves to increase channel conducting area
US5019522A (en) * 1986-03-21 1991-05-28 Advanced Power Technology, Inc. Method of making topographic pattern delineated power MOSFET with profile tailored recessed source
US4748103A (en) * 1986-03-21 1988-05-31 Advanced Power Technology Mask-surrogate semiconductor process employing dopant protective region
US4998151A (en) * 1989-04-13 1991-03-05 General Electric Company Power field effect devices having small cell size and low contact resistance
US4985740A (en) * 1989-06-01 1991-01-15 General Electric Company Power field effect devices having low gate sheet resistance and low ohmic contact resistance
US5119153A (en) * 1989-09-05 1992-06-02 General Electric Company Small cell low contact resistance rugged power field effect devices and method of fabrication
JP2994670B2 (en) * 1989-12-02 1999-12-27 忠弘 大見 Semiconductor device and manufacturing method thereof
JPH04144287A (en) * 1990-10-05 1992-05-18 Mitsubishi Electric Corp Semiconductor device
US5430315A (en) * 1993-07-22 1995-07-04 Rumennik; Vladimir Bi-directional power trench MOS field effect transistor having low on-state resistance and low leakage current
KR100200485B1 (en) * 1996-08-08 1999-06-15 윤종용 Mos transistor and manufacturing method thereof
JP3461274B2 (en) * 1996-10-16 2003-10-27 株式会社東芝 Semiconductor device
US5897343A (en) * 1998-03-30 1999-04-27 Motorola, Inc. Method of making a power switching trench MOSFET having aligned source regions

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61161766A (en) * 1985-01-10 1986-07-22 Matsushita Electronics Corp Longitudinal mosfet
JPH0311765A (en) * 1989-06-09 1991-01-21 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPH0323674A (en) * 1989-06-21 1991-01-31 Mitsubishi Electric Corp Semiconductor device
JPH0575121A (en) * 1991-09-18 1993-03-26 Fujitsu Ltd Semiconductor device
JPH05347414A (en) * 1992-06-12 1993-12-27 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH08264764A (en) * 1995-03-22 1996-10-11 Toshiba Corp Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2010110246A1 (en) * 2009-03-25 2012-09-27 ローム株式会社 Semiconductor device
JP2013077761A (en) * 2011-09-30 2013-04-25 Toshiba Corp Silicon carbide semiconductor device
JP2015012294A (en) * 2013-07-02 2015-01-19 ゼネラル・エレクトリック・カンパニイ Metal-oxide-semiconductor (mos) devices with increased channel periphery and methods of manufacturing the same
US20180151720A1 (en) * 2016-11-30 2018-05-31 Alpha And Omega Semiconductor Incorporated Folded channel trench mosfet
US10199492B2 (en) * 2016-11-30 2019-02-05 Alpha And Omega Semiconductor Incorporated Folded channel trench MOSFET

Also Published As

Publication number Publication date
JP4804610B2 (en) 2011-11-02
US20010002327A1 (en) 2001-05-31
US6218701B1 (en) 2001-04-17
EP1049174A2 (en) 2000-11-02
KR100727416B1 (en) 2007-06-13
US6677202B2 (en) 2004-01-13
KR20010014813A (en) 2001-02-26

Similar Documents

Publication Publication Date Title
US9818860B2 (en) Silicon carbide semiconductor device and method for producing the same
US7714383B2 (en) Semiconductor device
TW493239B (en) Trench MOSFET with double-diffused body profile
US6365942B1 (en) MOS-gated power device with doped polysilicon body and process for forming same
JP5118270B2 (en) MOS gate device having a buried gate
JP3973395B2 (en) Semiconductor device and manufacturing method thereof
JP2000323712A (en) Power mos device with increased channel width and its manufacture
JP2003124464A5 (en)
JP2004522319A (en) Manufacturing of semiconductor devices with Schottky barrier
US10636883B2 (en) Semiconductor device including a gate trench and a source trench
JP2005501408A (en) Trench double-diffused metal oxide semiconductor transistor incorporating a trench Schottky rectifier
JP5298565B2 (en) Semiconductor device and manufacturing method thereof
TW200302575A (en) High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon
JP2005056912A (en) Semiconductor device and its fabricating process
TW201511293A (en) MOSFET with integrated schottky diode
JP2004064063A (en) High voltage vertical type dmos transistor, and method for producing the same
US8017494B2 (en) Termination trench structure for mosgated device and process for its manufacture
KR101430833B1 (en) Power mosfet and methods for forming the same
JP2003086800A (en) Semiconductor device and manufacturing method therefor
US20090166734A1 (en) Trench gate mosfet and method for fabricating the same
TWI803288B (en) Integrated planar-trench gate power mosfet
US8072027B2 (en) 3D channel architecture for semiconductor devices
TWI808856B (en) Bottom source trench mosfet with shield electrode
US20230352580A1 (en) Three-dimensional transistor device having conformal layer
JPH04306881A (en) Semiconductor device and manufacture thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070219

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20070406

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20070406

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100430

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101130

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110225

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110329

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110627

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110712

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110810

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140819

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees