JP2000323699A - Photoelectric transducer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a photoelectric transducer device which can enhance an S/N ratio by a method wherein, out of control interconnections which are arranged and installed in the vertical or lateral direction with reference to a plurality of photoelectric transfer elements arranged two-dimensionally, the odd number control interconnections and the even number control interconnections are taken out to respective opposite sides. SOLUTION: A plurality of photoelectric transducer elements are arranged two-dimensional on a substrate. With reference to the photoelectric transducer element, control interconnections g1, g3, g5,... g1999 are arranged on the left side L, and control interconnections g2, g4, g6,... g2000 are arranged on the right side R. That is to say, the odd number control interconnections are formed at the left side L, and the even number control interconnections are formed at the right side R. The odd number control interconnections and the even number control interconnections are taken out respectively to opposite sides, and ten respective chips SRl-1 to SRl-10, SRl-11 to SRl-20 and IC1 to IC10, IC11 to IC20 are connected on the sides on which the control interconnections are taken out. As a result, the S/N ratio of the photoelectric transducer device can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device, and more particularly, to a one-dimensional or two-dimensional photoelectric conversion device capable of performing the same-magnification reading of a facsimile, a digital copying machine, an X-ray imaging device, or the like.

[0002]

2. Related Background Art Conventionally, a reading system using a reduction optical system and a CCD type sensor has been used as a reading system of a facsimile, a digital copying machine, an X-ray imaging device, or the like. However, in recent years, with the development of a photoelectric conversion semiconductor material represented by hydrogenated amorphous silicon (hereinafter, a-Si), a photoelectric conversion element and a signal processing unit are formed on a large-area substrate, and the size of the information source is increased to 1: 1. The development of a so-called contact type sensor that reads data using an optical system has been advanced or is being put to practical use. In particular, since a-Si can be used not only as a photoelectric conversion material but also as a semiconductor material of a thin film field effect transistor (hereinafter referred to as TFT), the photoelectric conversion semiconductor layer and the TFT semiconductor layer can be formed simultaneously. It is convenient.

FIGS. 4 (a) and 4 (b) are schematic cross-sectional views for explaining an example of the configuration of a conventional optical sensor. FIGS. 4 (a) and 4 (b) are optical cross-sectional views, respectively. FIG. 4C is a schematic circuit diagram for explaining a driving method, showing an example of a layer configuration of the sensor, and is an example of a typical driving method common to FIGS. 4A and 4B. Is shown. FIG. 4 (a),
4B are both photo-diode type optical sensors. FIG. 4A is called a PIN type, and FIG. 4B is called a Schottky type. 4 (a) and 4 (b), reference numeral 1 denotes an insulating substrate, 2 denotes a lower electrode, 3 denotes a p-type semiconductor layer (hereinafter referred to as a p-layer), 4 denotes an intrinsic semiconductor layer (hereinafter referred to as an i-layer), 5 Denotes an n-type semiconductor layer (hereinafter referred to as an n-layer), and 6 denotes a transparent electrode. In the Schottky type shown in FIG. 4B, the material of the lower electrode 2 is appropriately selected, and a Schottky barrier layer is formed so that unnecessary electrons are not injected into the i-layer 4 from the lower electrode 2.

In FIG. 4 (c), reference numeral 10 denotes an optical sensor which symbolizes the optical sensor, 11 denotes a power source, 1
Reference numeral 2 denotes a detection unit such as a current amplifier. Optical sensor 10
The direction indicated by middle C is the transparent electrode 6 side in FIGS. 4A and 4B, and the direction indicated by A is the lower electrode 2 side. Is set to be applied. Here, the operation will be briefly described.

As shown in FIGS. 4A and 4B, light is incident from the direction indicated by the arrow, and when it reaches the i-layer 4, the light is absorbed and electrons and holes are generated. i layer 4
Has an electric field applied by the power supply 11, the electrons are C
Side, that is, the transparent electrode 6 moves through the n-layer 5, and the hole moves to the A side, that is, the lower electrode 2. Therefore, a photocurrent has flowed through the optical sensor 10. When light is not incident, neither electrons nor holes are generated in the i-layer 4, the n-layer 5 functions as a hole injection blocking layer for the holes in the transparent electrode 6, and the electrons in the lower electrode 2 correspond to FIG. In FIG. 4A, the p-type layer 3 functions as a pin layer, and in the Schottky type in FIG. 4B, the Schottky barrier layer functions as an electron injection blocking layer. Both electrons and holes cannot move, and no current flows. Thus, the current flowing through the circuit changes depending on the presence or absence of light. This is shown in FIG.
If it is detected by the detection unit 12 in (c), it operates as an optical sensor.

[0006]

However, it is difficult to produce a photoelectric conversion device having a high SN ratio and a low cost with the above-mentioned conventional optical sensor. The reason will be described below.

The first reason is that both the PIN type shown in FIG. 4A and the Schottky type shown in FIG. 4B require two injection blocking layers.

In the PIN type shown in FIG. 4A, the n-layer 5, which is an injection-blocking layer, needs to have a property of guiding electrons to the transparent electrode 6 and simultaneously preventing holes from being injected into the i-layer 4. If either of the characteristics is missed, the photocurrent is reduced, or a current when light is not incident (hereinafter, referred to as a dark current) is generated and increased, which causes a reduction in the SN ratio. This dark current itself includes noise, which is considered as noise and fluctuations called shot noise, so-called quantum noise. Even if the dark current is subtracted by the detection unit 12, the quantum noise accompanying the dark current is reduced. It is not possible.

Usually, the i-layer 4 and n
It is necessary to optimize the conditions for forming the layer 5 and the annealing conditions after the formation. However, the p-layer 3 which is another injection blocking layer also needs to have the same characteristics although the electron and the hole are reversed, and similarly, it is necessary to optimize each condition. Usually, the conditions for the optimization of the former n-layer and the optimization of the latter p-layer are not the same, and it is difficult to satisfy both conditions simultaneously.

That is, the necessity of two injection blocking layers in the same optical sensor makes it difficult to form an optical sensor having a high SN ratio.

The same applies to the Schottky type shown in FIG. Also, in the Schottky type shown in FIG. 4B, a Schottky barrier layer is used for one of the injection blocking layers, but this utilizes the difference in work function between the lower electrode 2 and the i-layer 4, and the lower electrode Material 2 is limited, and the influence of the localized level of the interface greatly affects the characteristics, and it is more difficult to satisfy the conditions.

In order to further improve the characteristics of the Schottky barrier layer, a distance between the lower electrode 2 and the i-layer 4 is 100
Thin silicon and metal oxide films before and after Angstrom
It has also been reported that a nitride film is formed, but this improves the effect of guiding holes to the lower electrode 2 by using the tunnel effect and preventing injection of electrons into the i-layer 4. Therefore, the material of the lower electrode 2 needs to be limited. In addition, the oxide film and the nitride film are required to be as thin as about 100 angstroms in order to utilize the opposite properties of blocking injection of electrons and moving holes by a tunnel effect. And it is difficult to control the thickness and film quality, and the productivity is reduced.

Further, the necessity of two injection blocking layers not only reduces the productivity but also increases the cost. This is because the injection blocking layer is important in characteristics,
This is because if a defect occurs due to dust or the like in any of the places, desired characteristics as an optical sensor cannot be obtained.

The second reason will be described with reference to FIG. FIG.
Shows the layer configuration of a field effect transistor (TFT) formed of a thin semiconductor film. The TFT may be used as a part of a control unit in forming a photoelectric conversion device. In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals. In FIG. 2, 7 is a gate insulating film, and 60 is an upper electrode. The formation method will be described step by step. A lower electrode 2 serving as a gate electrode (G), a gate insulating film 7, an i-layer 4, an n-layer 5, source and drain electrodes (S, D) on an insulating substrate 1.
The upper electrode 60 acting as a film is sequentially formed, the upper electrode 60 is etched to form source and drain electrodes, and then the n-layer 5 is etched to form a channel portion. T
The characteristics of the FT are sensitive to the state of the interface between the gate insulating film 7 and the i-layer 4 and are usually deposited continuously in the same vacuum in order to prevent the contamination.

When a conventional optical sensor is formed on the same substrate as the TFT, this layer structure becomes a problem, resulting in an increase in cost and a decrease in characteristics. The reason for this is that the configuration of the conventional optical sensor shown in FIG. 4 is different from that of the PIN type shown in FIG.
While the i-layer / n-layer / electrode and the Schottky type shown in FIG. 4B have the structure of electrode / i-layer / n-layer / electrode, the TFT
The reason for this is that both layers have different structures in the structure of electrode / insulating film / i-layer / n-layer / electrode. This indicates that the optical sensor and the TFT cannot be formed simultaneously in the same process, and the yield is reduced and the cost is increased due to the complexity of a process in which a photolithography process and the like are repeated to form a necessary layer in a necessary place. Further, in order to make the i-layer / n-layer common, an etching step of the gate insulating layer 7 and the p-layer 3 is required. 4 cannot be formed in the same vacuum,
The important interface between the gate insulating film 7 and the i-layer 4 of the FT is contaminated by the etching of the gate insulating film, which causes deterioration of characteristics and reduction of the SN ratio.

In the case where an oxide film or a nitride film is formed between the lower electrode 2 and the i-layer 4 in order to improve the Schottky characteristics shown in FIG. 4B, the order of the film configuration is the same. However, as described above, the oxide film and the nitride film need to be around 100 angstroms, and it is difficult to share the oxide film and the nitride film with the gate insulating film. FIG. 3 shows the results of our experiments on the yield of the gate insulating film and the TFT. When the thickness of the gate insulating film is 1000 Å or less, the yield sharply decreases, and when the thickness is 800 Å, the yield is about 30%.
At 500 Å, the yield was 0%, and at 250 Å, even the operation of the TFT could not be confirmed.
An oxide film or a nitride film of an optical sensor using a tunnel effect;
Obviously, it is difficult to share a gate insulating film of a TFT, which must insulate electrons and holes, as shown by data.

Further, although not shown, a capacitance element (hereinafter referred to as a capacitor), which is an element necessary for obtaining an integrated value of a charge or a current, has the same configuration as that of a conventional optical sensor and has a small leakage and a good quality. It is difficult to make something special. The purpose of a capacitor is to accumulate charge between two electrodes, so an intermediate layer between the electrodes must have a layer to prevent the movement of electrons and holes, whereas a conventional photosensor has a semiconductor between the electrodes. This is because it is difficult to obtain an intermediate layer having good characteristics with little thermal leakage because only the layer is used.

As described above, poor matching in process or characteristics with TFTs and capacitors, which are important elements in configuring a photoelectric conversion device, is caused by arranging a large number of optical sensors one-dimensionally or two-dimensionally. However, when the entire system for sequentially detecting this optical signal is composed of many steps and becomes complicated, the yield is extremely low, and this is a serious problem in producing a low-cost, high-performance, multifunctional device. There is.

[Object of the Invention] An object of the present invention is to provide a photoelectric conversion device having a high SN ratio and stable characteristics, a driving method thereof, and a system having the same.

Another object of the present invention is to provide a photoelectric conversion device having a high yield and easy production and a system having the photoelectric conversion device.

In addition, the present invention provides a photoelectric conversion device which can be formed in the same process as a TFT, can be manufactured at low cost without complicating the production process, a driving method thereof, and a system having the same. The purpose is to provide.

[0022]

According to the present invention, there is provided a photoelectric conversion apparatus comprising a plurality of photoelectric conversion elements arranged two-dimensionally on a substrate, as a means for solving the above-mentioned problems. Odd-numbered and even-numbered control wirings or signal wirings arranged vertically or horizontally with respect to a plurality of photoelectric conversion elements arranged in parallel are taken out on opposite sides, and a plurality of integrated circuits are taken out at each takeout side. Provided is a photoelectric conversion device connected to a circuit element.

The present invention also relates to a photoelectric conversion device in which a plurality of photoelectric conversion elements are two-dimensionally arranged on a substrate, wherein the plurality of photoelectric conversion elements are vertically arranged with respect to the two-dimensionally arranged photoelectric conversion elements. Alternatively, it has control wiring or signal wiring arranged in the left-right direction and a plurality of integrated circuit elements connected to the control wiring or signal wiring, and connects the control wiring or signal wiring continuous for each integrated circuit element. The present invention also provides a photoelectric conversion device in which the integrated circuit elements are divided left and right or up and down.

The present invention also relates to a plurality of substrates each having a photoelectric conversion unit provided on a base and having a plurality of two-dimensionally arranged photoelectric conversion elements for receiving X-rays and converting the signals into electric signals. Provided is a photoelectric conversion device including an integrated circuit element provided for a signal supplied to an element or a signal output from the photoelectric conversion element, and a base and a case for housing the integrated circuit element.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings as necessary.

Embodiment 1 FIGS. 1A and 1B
Is a schematic layer configuration diagram for explaining the photoelectric conversion unit of the photoelectric conversion device according to the first embodiment of the present invention, respectively,
It is a schematic circuit diagram of a photoelectric conversion device.

In FIG. 1A, reference numeral 1 denotes an insulating substrate made of glass or the like, and reference numeral 2 denotes a lower electrode made of Al or Cr. Reference numeral 70 denotes an insulating layer formed of silicon nitride SiN or the like that blocks passage of both electrons and holes.
The thickness is set to 500 Å or more, which is a thickness that does not allow electrons and holes to pass through due to the tunnel effect. 4 is hydrogenated amorphous silicon (a-S
i: H), a photoelectric conversion semiconductor layer formed of an intrinsic semiconductor i layer, and 5 is an injection formed of an a-Si n ⁺ layer for preventing injection of holes into the photoelectric conversion semiconductor layer 4 from the transparent electrode 6 side. The blocking layer and the transparent electrode 6 are formed of a compound containing indium or tin, such as ITO, or an oxide.

In FIG. 1B, reference numeral 100 denotes a symbol of the photoelectric conversion unit shown in FIG.
G indicates an electrode on the lower electrode 2 side. Reference numeral 120 denotes a detection unit, and 110 denotes a power supply unit. The power supply unit 110 includes a switch 113 that switches between a positive power supply 111 that applies a positive potential to the D electrode and a negative power supply 112 that applies a negative potential. Switch 113 is refr in refresh mode.
In the photoelectric conversion mode, control is performed so as to be connected to the read side.

Here, the operation of the photoelectric conversion unit 100 used in this embodiment will be described. FIG. 5 (a), FIG.
(B) is an energy band diagram of the photoelectric conversion unit showing the operation in the refresh mode and the photoelectric conversion mode of the present embodiment, and shows the state of each layer of the photoelectric conversion unit in the thickness direction.

In the refresh mode (a), the D electrode is given a negative potential with respect to the G electrode.
The holes indicated by black circles in the layer 4 are guided to the D electrode by the electric field. At the same time, electrons indicated by white circles are injected into the i-layer 4. At this time, some holes and electrons recombine in the n-layer 5 and the i-layer 4 and disappear. If this state continues for a sufficiently long time, holes in the i-layer 4 are swept out of the i-layer 4 (FIG. 5).
(A)).

In the photoelectric conversion mode (b) in this state, a positive potential is applied to the D electrode with respect to the G electrode, so that electrons in the i layer 4 are instantaneously guided to the D electrode. However, holes are not led to the i-layer 4 because the n-layer 5 functions as an injection blocking layer. When light enters the i-layer 4 in this state, the light is absorbed and electron-hole pairs are generated. These electrons are guided to the D electrode by the electric field, and the holes move in the i-layer 4 and reach the interface of the insulating layer 70. However, since they cannot move into the insulating layer 70, they stay in the i-layer 4. At this time, the electrons move to the D electrode, and the holes become
To move to the interface, to maintain electrical neutrality inside the device,
A current flows from the G electrode to the detection unit 120. This current is proportional to the incident light because it corresponds to the electron-hole pair generated by the light (FIG. 5B).

After the photoelectric conversion mode (b) is maintained for a certain period, when the state is again changed to the refresh mode (a), i
The hole remaining in the layer 4 is guided to the D electrode as described above, and at the same time, the charge corresponding to this hole is detected by the detection unit 12.
Flows to zero. The amount of holes corresponds to the total amount of light incident during the photoelectric conversion mode period, and the charge flowing to the detection unit 120 corresponds to the total amount of light. At this time, a charge corresponding to the amount of electrons injected into the i-layer 4 also flows, but since this amount is approximately constant, it may be detected by subtracting it.

That is, the photoelectric conversion unit 1 in this embodiment
00 can output the amount of light incident in real time and also output the total amount of light incident in a certain period. This is a major feature of this embodiment. The detecting unit 120 may detect either one or both depending on the purpose.

Here, the operation of this embodiment will be described with reference to FIG.

FIG. 6 shows the operation of the photoelectric conversion device of FIG.
It is a timing chart. V in the figure _dgIs the photoelectric conversion unit 10
0 is the potential of the D electrode with respect to the G electrode, and P is the incidence of light.
Indicates the state of light incidence when ON, and light input when OFF.
There is no shooting. That is, it indicates a dark state. I_sIs detected
Indicates the current flowing into the unit 120, and the horizontal axis indicates the passage of time
Is shown.

First, when the switch 113 is connected in the refresh direction, a refresh mode is entered, V _dg becomes a negative voltage, and holes are swept out as shown in FIG.
Further, as electrons are injected into the i-layer 4, the detection unit 120
, A negative rush current E shown by E in FIG. 6 flows. Thereafter, the refresh mode ends, and the switch 113
When connected in the ad direction, electrons in the i-layer 4 are swept out and a positive rush current E 'flows to enter the photoelectric conversion mode. At this time, if light is incident, a photocurrent A indicated by A flows. If the operation is similar to that of the dark state, no current flows as indicated by A '. Therefore, if the photocurrent A is integrated directly or for a certain period, the incidence of light can be detected.

Further, from the state of A, the switch 113 is set to re.
When connected in the fresh direction, an inrush current B flows. This is an amount reflected on the total amount of light incident during the immediately preceding photoelectric conversion mode period, and the rush current B may be integrated or a value equivalent to integration may be obtained. If no light is incident in the immediately preceding photoelectric conversion mode, the rush current becomes small as B ', and if the difference is detected, the incident light can be detected. Since the inrush currents E 'and E "described above are approximately equal to the inrush current B', they may be subtracted from the inrush current B.

Further, even during the same photoelectric conversion mode period, if the incident state of light changes, I _S changes like C and C ′. Even if this is detected, the incident state of light can be detected. In other words, this indicates that it is not always necessary to set the refresh mode every time a detection opportunity occurs.

However, when the period of the photoelectric conversion mode is long or the illuminance of the incident light is strong for some reason, the current may not flow despite the incident light as shown in D. This is as shown in FIG.
Many holes remain in the i-layer 4 and the electric field in the i-layer 4 decreases due to the holes, and the generated electrons are not conducted to the D electrode, and recombine with the holes in the i-layer 4. is there. If the light incident state changes in this state, the current may flow in an unstable manner. However, when the refresh mode is set again, the holes in the i-layer 4 are swept out, and in the next photoelectric conversion mode, as shown by A ″. A current equal to A is obtained.

In the above description, the incident light is described as being constant. However, the current of A, B, and C continuously changes depending on the intensity of the incident light, and the intensity is not limited to the detection of the presence or absence of the incident light. It goes without saying that it can be quantitatively detected.

In the above description, when the holes in the i-layer 4 are to be swept out in the refresh mode, it is ideal that all the holes are swept out. The value is not different from the case where all are swept out in A or C, and there is no problem. In addition, by sweeping out so that a constant amount always remains, the amount of light can be quantitatively detected also by the current of B.
That is, it is sufficient that the current value does not reach the state of D, that is, the state of FIG. 5C at the detection opportunity in the next photoelectric conversion mode, the voltage of V _dg in the refresh mode, the period of the refresh mode, and the n-layer. The characteristics of the fifth injection blocking layer may be determined.

Further, in the refresh mode,
Therefore, injection of electrons into the i-layer 4 is not a necessary condition,_dgNo electricity
The pressure is not limited to negative. Part of the hole is i-layer
It only has to be swept out of 4. Many holes remain in i-layer 4
, If V _dgIs a positive voltage even if i
The electric field in layer 4 is applied in the direction that leads the hole to the D electrode.
It is. Similarly, the characteristics of the injection blocking layer of the n-layer 5 indicate that electrons are transferred to the i-layer.
It is not a requirement that 4 can be injected.

FIGS. 7 (a), 7 (b), 7 (c), and 7 (d) show examples of the configuration of the detection unit. 121 is an ammeter represented by a current Amp, 122 is a voltmeter, 123 is a resistor, 124 is a capacitor, 125
Is a switch element, and 126 is an operational amplifier.

FIG. 7 (a) directly detects current.
The output of the ammeter 121 is a voltage or an amplified current.
FIG. 7B shows a state in which a current flows through the resistor 123 and a voltage is detected by the voltmeter 122. FIG. 7C shows that the electric charge is accumulated in the capacitor 124, and the voltage is detected by the voltmeter 122. In FIG. 7D, the operational amplifier 126 detects the integrated value of the current as a voltage. 7 (c) and 7 (d), the switch element 125 serves to give an initial value for each detection, and can be replaced with a high-resistance resistor depending on the detection method.

The ammeter or voltmeter is composed of a transistor, an operational amplifier combining the transistor, a resistor, a capacitor, and the like.
Anything that operates at high speed can be used. The detection unit is not limited to these four types, and it is sufficient if the current or charge can be detected directly or the integrated value can be detected. A detector that detects the current or voltage value, a resistor, a capacitor, and a switch element are combined, and a plurality of The conversion units may be configured to output simultaneously or sequentially.

When configuring a line sensor or an area sensor, the potentials of 1000 or more photoelectric conversion units are controlled and detected in a matrix in combination with the wiring and switch elements of the power supply unit. In this case, if a part of the switch element, the capacitor, and the resistor are formed on the same substrate as the photoelectric conversion unit, it is advantageous in terms of the SN ratio and the cost. In this case, since the photoelectric conversion unit of this embodiment has the same film configuration as a TFT which is a typical switch element, it can be formed simultaneously in the same process and a low-cost photoelectric conversion device with a high SN ratio can be realized.

[Embodiment 2] FIG. 8 is a circuit diagram showing a second embodiment of the photoelectric conversion device of the present invention. The same parts as those in the above-described drawings are denoted by the same reference numerals. The layer configuration of the photoelectric conversion unit 100 is the same as that in FIG. 1
Reference numeral 14 denotes a power supply for applying a positive potential to the D electrode, reference numeral 115 denotes a power supply for applying a positive potential to the G electrode in the refresh mode of the photoelectric conversion unit, and reference numeral 116 denotes a switch element for switching each mode. At this time, the power supply 115 is the power supply 1
The voltage is set to be equal to or higher than 14.

In this embodiment, there are four thin modes.
These are a photoelectric conversion unit refresh mode, a G electrode initialization mode, an accumulation mode, and a detection mode, respectively.
The refresh mode of the photoelectric conversion unit is the refresh mode of the above embodiment, and the G electrode initialization mode, the accumulation mode, and the detection mode are the photoelectric conversion mode of the embodiment and an electric field is applied to each layer of the photoelectric conversion unit 100 in the same direction. In addition, the operation of the photoelectric conversion unit 100 is basically the same.
Hereinafter, each mode will be sequentially described.

In the photoelectric conversion unit refresh mode, the switch element 116 is connected to the refresh position in the drawing, and a positive potential is applied to the G electrode by the power supply 115. A positive potential is applied to the D electrode by the power supply 114, that is, the potential V with respect to the potential of the G electrode of the D electrode.
_dg is approximately 0 or a negative voltage is applied. Then, the holes in the photoelectric conversion unit 100 are swept out and refreshed.

Next, the switch element 116 is connected to the GND position and shifts to the G power supply initialization mode, and the G electrode is set to GN.
D potential is applied. At this time, V _dg becomes a positive voltage,
The photoelectric conversion unit 100 enters the photoelectric conversion mode after the inrush current flows.

Next, the switch element 116 is set to the open position, the mode shifts to the accumulation mode, and the G electrode is opened DC. However, the potential is actually maintained by the equivalent capacitance component _CS and stray capacitance _CO of the photoelectric conversion unit 100 indicated by the dotted line. Here, when light is incident on the photoelectric conversion unit 100, a corresponding current flows out of the G electrode, and the potential of the G electrode rises. That is, light incident information is accumulated as charges in C _S and C _O. When the switch element 116 is connected to the sense position after a certain accumulation time, the mode shifts to the detection mode, and the potential of the G electrode is returned to the GND potential again. At this time, the electric charges simultaneously accumulated in C _S and C _O are detected by the detection unit 120.
However, this charge is stored in the photoelectric conversion unit 100 in the accumulation mode.
It is detected by the detection unit 120 as equal to the integral of the current flowing out of the detector, that is, as the total amount of incident light.

Further, the switch element 116 is set to ref again.
It is connected to the "resh" position, and the following operation is repeated.

The feature of this embodiment is that the integrated value of the current flowing during a certain long-term storage time can be obtained in a short period of the detection mode by a simple combination of elements. This shows that a photoelectric conversion device having a high SN ratio having a photoelectric conversion unit can be configured at low cost.

The operation of the photoelectric conversion unit of this embodiment is basically the same as that of the first embodiment, except that the potential of the G electrode increases and the voltage V _dg decreases during the photoelectric conversion mode. This is said to likely become a state indicated by the quantity of incident small light (c) in FIG. 5, may become a limiting amount of incident light in a normal operation, this is positively large storage in parallel with the stray capacitance C _O It can be easily improved by inserting a capacitor.

The detection unit 120 includes a capacitor 124,
The switch is composed of a switch element 125 and an operational amplifier 126. The charge flowing in the detection mode is stored in the capacitor 124, converted into a voltage, and output through a buffer amplifier. Therefore, the G electrode is set to a complete GND potential in the detection mode. It does not affect the basic operation. The capacitor 124 is initialized by the switch element 125 in another mode. Further, the changeover switch element 116 does not need to be multipolar, for example, TF
A switch element such as T can be composed of three switches.

[Embodiment 3] FIGS. 9A, 9B, and 9C are layer configuration diagrams showing another embodiment of the photoelectric conversion unit 100, respectively. The same parts as those in the above-described drawings are denoted by the same reference numerals.

In FIG. 9A, 101 is a transparent insulating substrate, and 21 is a lower transparent electrode using a transparent conductive layer. Reference numeral 61 denotes an upper electrode, which is not necessarily required to be transparent, and may be a metal such as Al. The incident light passes through the transparent insulating substrate 101, the transparent electrode 21, and the insulating layer 70 and enters the i-layer 4.

In FIG. 9B, reference numeral 62 denotes an upper electrode, which does not completely cover the n-layer 5. Therefore,
Light can pass through the n-layer 5 and enter the i-layer 4. That is, the electrode 62 is made of a metal such as Al and need not be transparent. The carriers are output to the outside through the upper electrode 62.

FIG. 9C shows that the electrode 61 is directly deposited on the i-layer 4. In this configuration, injection of holes from the electrode 61 to the i-layer 4 is prevented by the Schottky barrier layer, which is formed from the difference in work function between the electrode 61 and the i-layer 4. Therefore, the above-described n-layer 5 does not need to be deposited, and a further low-cost photoelectric conversion device can be configured.

As is clear from the above description, the photoelectric conversion unit is not limited to the one shown in the embodiment. That is, there is a first electrode layer, an insulating layer that blocks movement of holes and electrons, a photoelectric conversion semiconductor layer, and a second electrode layer, and between the second electrode layer and the photoelectric conversion semiconductor layer, What is necessary is just to have an injection blocking layer for blocking the injection of holes.

In the above description, the relationship between holes as carriers and electrons may be reversed. For example, the injection blocking layer may be a p-layer. In this case, in the above description, the operation is the same if the application of the voltage or the electric field is reversed and other components are configured.

Further, the photoelectric conversion semiconductor is not limited to the i-layer. What is necessary is that it has a photoelectric conversion function of generating a pair of electrons and holes upon incidence of light. The layer structure may be a multilayer structure instead of a single layer, or a structure in which the composition or the like is continuously changed in the layer thickness direction to continuously change the characteristics.

Further, the insulating substrate need not be entirely an insulator, and may be a conductor or a semiconductor on which an insulator is deposited. The order of depositing the respective layers on the insulating substrate is not limited to the first electrode, the insulating layer, or the like, but may be reversed, that is, the second electrode, the injection blocking layer, or the like.

Needless to say, the above-described driving method can be applied to the case where the photoelectric conversion unit having the configuration described with reference to FIGS. 9A to 9C is provided.

[Embodiment 4] FIG. 10A is a schematic layer configuration diagram of a photoelectric conversion element 100, a TFT 200 serving as a switching element, and a wiring layer 400 in a photoelectric conversion apparatus according to the present embodiment, and FIG. FIG. 2 is a schematic circuit diagram of a photoelectric conversion device. In FIG. 10A, the parts indicated by the same numbers as those in FIG. 3 indicate the same parts.

In this embodiment, the lower electrode 2 and the upper electrode 6 are formed of opaque electrodes, and the upper electrode 6 does not completely cover the injection blocking layer 5 so that light can enter from the upper side through the injection blocking layer 5. ing. However, if the upper or lower electrode is formed of a transparent electrode such as ITO, light can enter even if the upper electrode 6 covers the injection blocking layer 5.

Further, reference numeral 202 denotes a gate electrode formed of Al or Cr, etc., 207 denotes a gate insulating layer formed of silicon nitride SiN, and 204 denotes hydrogenated amorphous silicon a.
A semiconductor layer 205 formed of an intrinsic semiconductor i-layer of Si, 205
Is an ohmic contact layer formed of an n-layer of a-Si for transferring electrons between the semiconductor layer 204 and the source electrode 206 and the drain electrode 208.

Source electrode 206 and drain electrode 20
8 is made of metal such as Al or Cr or polysilicon. The upper electrode 106 of the photoelectric conversion element 100 and the TFT
The 200 source electrodes 206 are connected by wirings 406 of Al or Cr.

As is apparent from the figure, the photoelectric conversion unit and the TFT
Can be simultaneously formed on the same insulating substrate 1 with the same material, and the wiring layer is also formed by the photoelectric conversion unit and the T
It can be formed simultaneously with each electrode of the FT, and can be formed by a simple process by using a common film.

Although FIG. 10A shows an example in which one TFT 200 as a switching element is connected, the number is not limited to one.

In FIG. 10B, reference numeral 100 denotes FIG.
(A) is a symbol of the photoelectric conversion element, wherein D indicates an electrode on the upper electrode 6 side and G indicates an electrode on the lower electrode 2 side.
Reference numeral 120 denotes a detection unit, 110 denotes a power supply unit, and the power supply unit 110
Is composed of a positive power supply 111 for applying a positive potential to the D electrode and a negative power supply 112 for applying a negative potential. In the figure, reference numerals 210 and 211 symbolize the TFT shown in FIG. 10A, and g, s, and d indicate a gate electrode 202, a source electrode 206, and a drain electrode 208, respectively. In FIG. 10A, as described above, the TFT 2
Although only one TFT is shown as 00, both TFTs 210 and 211 are actually formed on the same insulating substrate as shown in FIG. Each gate electrode is connected to the control unit 130
The control unit 130 controls the refresh-TFT 210 to be turned on in the refresh mode, and the read-TFT 211 to be turned on in the photoelectric conversion mode.

In this embodiment, the switch 113 described in the first embodiment is specifically shown as a read-TFT 211 and a refresh-TFT 210, and the selection of the read and the refresh in the first embodiment is performed by the control unit 130. FIG. 10B clearly shows that the signal is supplied from the first embodiment, but the description in the first embodiment can be applied to the method of driving the photoelectric conversion unit.

In this embodiment, at least a part of the photoelectric conversion portion and the TFT as a representative switch element can be formed in the same layer configuration, so that necessary layers can be simultaneously deposited and patterned in the same process, and a high yield can be obtained. Low cost, high S
A photoelectric conversion device having an excellent N ratio can be provided.

[Embodiment 5] FIG. 11A shows a fifth embodiment of the present invention.
Schematic configuration diagram of a photoelectric conversion unit 100, a TFT 200 as a switch element, a capacitor 300 as a capacitance element, and a wiring layer 400 in the photoelectric conversion device according to the example of
FIG. 11B is a schematic circuit diagram of a photoelectric conversion device applicable to FIG. FIG. 11 (a) and FIG. 11 (b)
10A and 10B denote the same members, and a description thereof will not be repeated.

In FIG. 11A, reference numeral 302 denotes Al.
307 is an insulating layer formed of silicon nitride SiN, 304 is a semiconductor layer formed of an intrinsic semiconductor i layer of hydrogenated amorphous silicon a-Si, and 305 is a semiconductor layer 304. A-Si for transferring electrons between the capacitor and the capacitor upper electrode 306
Is an ohmic contact layer formed by the n-layer. The upper electrode 306 of the capacitor is formed of Al or Cr.
Here, the insulating layer 307 / semiconductor layer 304 / ohmic contact layer 305 functions as an intermediate layer of the capacitor 300, and includes the insulating layer 307, whereby a good capacitor with little leakage is formed. The photoelectric conversion element 10
0 and the lower electrode 302 of the capacitor are A
They are connected by a wiring 402 of l or Cr.

As is clear from the drawing, the layer structure of each element is the same, each layer can be formed simultaneously with the same material on the same insulating substrate 1, and the wiring layer must be formed simultaneously with the electrodes of each element. It can be formed by a simple process by using a common film.

In FIG. 11B, DETECT T driven by a signal from the control unit 130 is different from FIG. 10B.
The point that an FT (detection TFT) 212 is interposed between the photoelectric conversion unit 100 and the detection unit 120;
The difference is that one electrode of the zero is grounded via the capacitor 300.

In this embodiment, only one TFT is shown in FIG. 11A, but only a typical example is shown in the same manner as in the fourth embodiment.
The read TFT 211, refr shown in FIG.
Esh TFT210 and DETECT TFT212
Can be formed on the same substrate.

As shown in FIG. 11B, the TFT 210
212 are formed on the same insulating substrate. Each gate electrode is connected to a control unit 130, and the control unit 130 refreshes in a fresh mode.
-TFT210, read-TFT in photoelectric conversion mode
211 is turned on. Also, det
The ect-TFT 212 is controlled so as to be appropriately turned on / off at the timing of detecting the integrated value of the output of the photoelectric conversion element accumulated in the capacitor 300.

The driving method described in the first embodiment can be applied to the driving of the photoelectric conversion device of the present embodiment as in the fourth embodiment. However, in this embodiment, the capacitor 3
Since the electric charge is stored at 00, it will be described again with reference to FIGS.

In this embodiment, the D electrode does not completely cover the n-layer, but the electron can freely move between the D-electrode and the n-layer. Yes, and the following explanation assumes that. The G electrode is supplied with the GND potential via the detection unit during the detection period, and is also approximately GND by the capacitor 300 during the accumulation period.
It is kept at the D potential.

In FIG. 5A in the refresh mode, since the D electrode is given a negative potential with respect to the G electrode, holes indicated by black circles in the i layer 4 are guided to the D electrode by an electric field. At the same time, electrons indicated by white circles are injected into the i-layer 4. At this time, some holes and electrons recombine in the n-layer 5 and the i-layer 4 and disappear. If this state continues for a sufficiently long time, holes in the i-layer 4 are swept out of the i-layer 4.

In this state, in the photoelectric conversion mode shown in FIG. 5B, a positive potential is applied to the D electrode with respect to the G electrode, so that the electrons in the i layer 4 are instantaneously guided to the D electrode. However, holes are not led to the i-layer 4 because the n-layer 5 functions as an injection blocking layer. When light enters the i-layer 4 in this state, the light is absorbed and electron-hole pairs are generated. These electrons are guided to the D electrode by the electric field, and the holes move in the i-layer 4 and reach the interface between the i-layer 4 and the insulating layer 70. However, since they cannot move into the insulating layer 70, they stay in the i-layer 4. At this time, the electrons move to the D electrode, and the holes move to the i-layer 4.
In order to maintain electrical neutrality in the device, a current flows from the G electrode to the capacitor 300 in order to move to the interface of the insulating layer 70 in the device. This current is proportional to the incident light because it corresponds to electron-hole pairs generated by the light. After maintaining the photoelectric conversion mode in FIG. 5B for a certain period, when the state in FIG. 5A in the refresh mode is returned again, the holes remaining in the i-layer 4 are led to the D electrode as described above, and at the same time, A current corresponding to this hole flows through the capacitor 300. The amount of holes corresponds to the total amount of light incident during the photoelectric conversion mode period, and the current corresponds to the total amount of light. At this time, a current corresponding to the amount of electrons injected into the i-layer 4 also flows, but since this amount is approximately constant, it may be detected by subtracting it. That is, the photoelectric conversion element 100 in the present embodiment can output the amount of light incident in real time, and can also output the total amount of light incident in a certain period. This is a major feature of this embodiment. The capacitor 300 accumulates a desired output among these outputs and decrements the integrated value thereof.
The detection may be performed by the detection unit 120 by turning on the t-TFT.

Next, the operation of this embodiment will be described. FIG. 6 is a timing chart of the operation in the photoelectric conversion device of FIG. In the figure, V _dg is the potential of the D electrode with respect to the G electrode of the photoelectric conversion element 100, P indicates the state of light incidence, ON indicates the state of light incidence, and OFF indicates no light incidence, that is, the dark state Is shown. I _S indicates the current flowing into the capacitor 300, and the horizontal axis indicates the passage of time. First, the control unit 130 refresh-T
When FT210 is turned on, it enters refresh mode and V
_dg becomes a negative voltage, holes are swept out as shown in FIG. 2A, and a negative rush current E shown in FIG. 6E flows through the capacitor 300 as electrons are injected into the i-layer 4. After that, the refresh mode ends and refresh
-The TFT 210 is turned off and the read-TFT 21
When 1 is controlled to be on, V _dg becomes a positive voltage, electrons in the i layer 4 are swept out, a positive rush current E 'flows, and the device enters the photoelectric conversion mode. At this time, if light is incident, a photocurrent indicated by A flows. If the operation is similar to that of the dark state, no current flows as indicated by A '. Therefore, if the photocurrent A is integrated for a certain period, the incidence of light can be detected. Also, from the state of A, the refresh-TFT 210 is turned on.
Rush current B flows. This is an amount reflected on the total amount of light incident during the immediately preceding photoelectric conversion mode period, and the light incident can be detected by integrating this rush current B. If light is not incident in the immediately preceding photoelectric conversion mode, the rush current becomes small as B ', and if the difference is detected, the incident light can be detected. Since the inrush currents E 'and E "described above are approximately equal to the inrush current B', they may be subtracted from the inrush current B. That is, the capacitor 300 integrates from just before the inrush current B to immediately after the inrush current E". do it. This is a feature of this embodiment, and (inrush current B-inrush current E ″) can be obtained without any special subtractor.

Further, even during the same photoelectric conversion mode period, if the incident state of light changes, I _S changes like C and C ′. Even if this is integrated, the incident state of light can be detected. In other words, this indicates that it is not always necessary to set the refresh mode every time a detection opportunity occurs.

However, if the period of the photoelectric conversion mode becomes longer or the illuminance of incident light is strong for some reason, current may not flow even though light is incident as shown in D. This is, as shown in FIG.
Many holes remain in the layer 4 and the i-layer 4
This is because the electric field in the inside becomes small, and the generated electrons are not guided to the D electrode and recombine with the holes in the i-layer 4. If the light incident state changes in this state, the current may flow in an unstable manner. However, when the refresh mode is set again, the holes in the i-layer 4 are swept out, and in the next photoelectric conversion mode, as shown by A ″. A current equal to A is obtained.

Here, a method of obtaining an integrated value by the capacitor 300 will be described. First, detect-TFT2
12 is turned on by the control unit 130, and a GND potential is applied to the capacitor 300 via the detection unit. At this time, the detection unit 120
It is not necessary to detect the flowing charge. Then detec
The t-TFT 212 is turned off and the integration starts. During the integration period, the current flowing through the capacitor 300 is
Is stored as an electric charge. At this time, although slightly, the potential of the capacitor 300 rises.
00 has almost no effect. When the detect-TFT 212 is turned on after integrating for a certain period, the electric charge stored in the capacitor 300 is changed to the detect-TFT2.
It flows to the detection unit 120 through 12. Since this current corresponds to the integrated value integrated for a certain period of time,
It is sufficient to detect with.

In the above description, the incident light has been described as being constant. However, the currents of A, B, and C change continuously depending on the intensity of the incident light, and the intensity is not limited to the detection of the presence or absence of the incident light. Needless to say, it can be detected.

In the above description, the refresh
When sweeping holes in the i-layer 4 in mode, all holes
Ideally, but some holes
There is an effect even if it is just a
Value is the same as when all are swept out, and there is no problem.
No. Also, if it is swept so that a constant amount always remains, the B
The amount of light can also be quantitatively detected by the flow.
That is, at the next photoelectric conversion mode detection opportunity, the current
The value is in the state of D, that is, the state of FIG.
If not, V in refresh mode_dgVoltage,
Characteristics of the injection blocking layer of the n-layer 5 and the period of the fresh mode
You only have to decide the sex. In addition, refresh mode
Injection of electrons into the i-layer 4 is not a necessary condition,_dg
Is not limited to negative. Many holes i
If staying in layer 4 _dgIs a positive voltage
Even so, the electric field in the i-layer is applied in the direction that leads the hole to the D electrode.
Because. Similarly, the characteristics of the injection blocking layer of the n layer
It is not a necessary condition that the i-layer 4 can be implanted.

As the detecting section, many types described using an example in FIG. 7 can be used.

In this embodiment, since the capacitor 300 is provided, it is possible to accumulate the photoelectrically converted signal for a desired period, thereby achieving higher sensitivity and higher SN ratio.

[Embodiment 6] FIG. 12 is a circuit diagram showing a sixth embodiment of the photoelectric conversion device of the present invention. The same parts as those in the above-described drawings are denoted by the same reference numerals. Photoelectric conversion element 100 and TFTs 220 to 2 serving as switching elements
Regarding the layer configuration of No. 22, the photoelectric conversion element 1 shown in FIG.
00, the TFT 200 is applicable. Reference numeral 114 denotes a power supply V _d for applying a positive potential to the D electrode, and 115 denotes a power supply V _g for applying a positive potential to the G electrode in the refresh mode of the photoelectric conversion element. At this time, the power supply 115 is set equal to or higher than the power supply 114. Each TFT 220-2
The gate electrodes 22 are controlled by the control units 131 to 133 respectively.
n / off is controlled. A portion 120 surrounded by a broken line is a detection portion, and detects light incident on the photoelectric conversion element 100 as described below.

In this embodiment, there are four modes in detail.
They are a photoelectric conversion element refresh mode, a G electrode initialization mode, an accumulation mode, and a detection mode, respectively.
The photoelectric conversion element refresh mode corresponds to the refresh mode of the above-described embodiment, and the G electrode initialization mode, accumulation mode, and detection mode correspond to the photoelectric conversion mode of the above-described embodiment. , An electric field is applied in the same direction, and the operation of the photoelectric conversion element 100 is basically the same. Hereinafter, each mode will be sequentially described. After the three TFTs 220 to 222 are turned off, in the photoelectric conversion element refresh mode,
FT220 is on, a positive potential V _g is applied to the electrode G by the power supply 115. The D electrode positive potential V _d are given by the power supply 114, that is, the potential V _dg of the relative potential of the G electrode of the D electrode will be given the (V _d -V _g). Then, the holes in the photoelectric conversion element 100 are swept out and refreshed. Next, after the TFT 220 is turned off, the TFT 221 is turned on by the control unit 132,
The mode shifts to the G electrode initialization mode, and the G electrode is supplied with the GND potential. At this time, V _dg becomes a positive voltage, and the photoelectric conversion element 100 enters the photoelectric conversion mode after a rush current flows.
Next, the TFT 221 is turned off, and the G electrode is opened DC. However, the potential is actually maintained by the equivalent capacitance component _CS and the stray capacitance _CO of the photoelectric conversion element 100 indicated by the dotted line. Here, when light is incident on the photoelectric conversion element 100, a corresponding current flows out of the G electrode, and the potential of the G electrode rises. That is, light incident information is accumulated as charges in C _S and C _O. Control unit 133 after a certain accumulation time
As a result, the TFT 222 is turned on, and the mode shifts to the detection mode. At this time, the charges accumulated in C _S and C _O are
Flows to the operational amplifier 126 side, and this charge corresponds to the integrated value of the current flowing out of the photoelectric conversion element 100 in the accumulation mode, that is, the operational amplifier 1
26, a capacitor 124, and a switch element 125. The control unit (not shown) turns on the switch element 125 and discharges the capacitor 124 to initialize the integrator before shifting to the detection mode. Further, after the TFT 222 is turned off, the TFT 220 is turned on again by the control unit 131, and the following operation is repeated.

As described above, the feature of this embodiment is that the integrated value of the current flowing during a certain long accumulation time is obtained by combining the elements.
This shows that the detection mode can be obtained in a short time, the cost of the high-cost operational amplifier is light, and a high SN ratio photoelectric conversion device having a plurality of photoelectric conversion elements can be configured at low cost. The operation of the photoelectric conversion element of this embodiment is basically the same as that of the first embodiment, except that the potential of the G electrode increases and the voltage V _dg decreases during the photoelectric conversion mode. This tends to cause the state shown in FIG. 5C with a small amount of incident light, which may limit the amount of incident light in normal operation. This is because a large storage capacitor must be actively connected in parallel with the stray capacitance C _O. It can be easily improved by inserting.

FIG. 13 (a) is a schematic plan view of the photoelectric conversion device shown in FIG. 12, and FIG. 13 (b) is a schematic cross section taken along AB shown in the schematic plan view of FIG. 13 (a). The figure is shown. Parts that cannot be shown in detail in FIG. 13A are indicated by the same symbols as in FIG. 100 is a photoelectric conversion element, 220
Reference numerals 222 denote TFTs, 402 and 406 denote wirings for electrically connecting the elements, and are connected via contact holes 408. In FIG. 13B, 412 and 41
Reference numeral 6 denotes a wiring connected to another component. Here, a method of forming each element will be described in order with reference to FIG.

First, about 500 angstroms of Cr is deposited as a lower metal layer 2 on a glass substrate 1, which is an insulating material, by sputtering or the like, and then patterned by photolithography to etch unnecessary areas.
As a result, the lower electrode of the photoelectric conversion element 100, the TFT 22
Gate electrodes 0 to 222, and lower wirings 402 and 41
2 are formed.

Next, SiN is formed in the same vacuum by CVD.
Layer 70 / i-layer 4 / n-layer 5 is approximately 2000/50
Deposit 00 ° / 500 °. These layers are the insulating layer / photoelectric conversion semiconductor layer / hole injection blocking layer of the photoelectric conversion element 100 and the gate insulating film / semiconductor layer / ohmic contact layer of the TFTs 220 to 222. It is also used as a cross section insulating layer for upper and lower wiring. The thickness of each layer is not limited to this and can be optimally designed according to the voltage, current, charge, incident light amount, etc. used as a photoelectric conversion device. However, at least SiN cannot pass electrons and holes, and at the same time, as a TFT gate insulating film. It is desirable that the thickness be 500 Å or more that can function.

After the deposition of each layer, the area to become the contact hole 408 is etched, and thereafter, about 10000 Å of Al is deposited as the upper metal layer 6 by sputtering or the like. Further, the unnecessary area is etched by patterning by photolinography and the photoelectric conversion element 100 is etched.
Upper electrodes, source electrodes and drain electrodes which are main electrodes of the TFTs 220 to 222, and upper wirings 406 and 4
16 are formed. At the same time, in the contact hole 408, the lower wiring 402 and the upper wiring 406 are connected.

Further, only the channel portions of the TFTs 220 to 222 are etched by RIE for the n-layer, and then unnecessary Si layers are etched.
Each element is separated by etching the N layer 70 / i layer 4 / n layer 5. With this, the photoelectric conversion element 100 and the TFTs 220 to
222, lower wirings 402, 412, upper wirings 406, 4
16 and the contact hole 408 are completed. Although not shown, the upper part of each element is usually covered with a passivation film such as SiN to improve the durability.

As described above, in this embodiment, the common lower metal layer 2 and the SiN layer 7 on which the photoelectric conversion element 100, the TFTs 220 to 222, and the wiring section 300 are simultaneously deposited.
/ I layer 4 / n layer 5, and upper metal layer 6 and each layer can be formed only by etching.
There is only one injection blocking layer in the same 00, and it can be formed in the same vacuum, and the gate insulating film / i-layer interface, which is important for TFT characteristics, can be formed in the same vacuum. It enables the production of high-performance photoelectric conversion devices at low cost.

[Embodiment 7] FIG. 14 is a circuit diagram showing a photoelectric conversion device according to a seventh embodiment of the present invention. Note that portions having the same functions as those in the above-described drawings are denoted by the same reference numerals.
The layer configurations of the photoelectric conversion element 100, the TFTs 220 to 222, and the capacitor 300 are the same as those in FIG. 114 is a power supply V _d for applying a positive potential to the D electrode,
115 indicates G in the refresh mode of the photoelectric conversion element.
Electrodes is a power supply V _g which gives a positive potential. At this time, power supply 1
Reference numeral 15 is set equal to or higher than the power supply 114. Gate electrodes of the TFTs 220 to 222 are controlled on / off by the control units 131 to 133, respectively.
A portion 120 surrounded by a broken line is a detection portion, and detects light incident on the photoelectric conversion element 100 as described below.

In this embodiment, there are four modes in detail.
They are a photoelectric conversion element refresh mode, a G electrode initialization mode, an accumulation mode, and a detection mode, respectively.
The photoelectric conversion element refresh mode corresponds to the refresh mode of the above-described embodiment, and the G electrode initialization mode, accumulation mode, and detection mode correspond to the photoelectric conversion mode of the above-described embodiment. , An electric field is applied in the same direction, and the operation of the photoelectric conversion element 100 is basically the same. Hereinafter, each mode will be sequentially described. After the three TFTs 220 to 222 are turned off, in the photoelectric conversion element refresh mode,
FT220 is on, a positive potential V _g is applied to the electrode G by the power supply 115. The D electrode positive potential V _d are given by the power supply 114, that is, the potential V _dg of the relative potential of the G electrode of the D electrode will be given the (V _d -V _g). Then, the holes in the photoelectric conversion element 100 are swept out and refreshed. Next, after the TFT 220 is turned off, the TFT 221 is turned on by the control unit 132,
The mode shifts to the G electrode initialization mode, and the G electrode is supplied with the GND potential. At this time, V _dg becomes a positive voltage, and the photoelectric conversion element 100 enters the photoelectric conversion mode after a rush current flows.
Next, the TFT 221 is turned off, and the G electrode is opened DC. However, the potential is maintained by the capacitor 300. Here, when light is incident on the photoelectric conversion element 100, a corresponding current flows out of the G electrode, and the potential of the G electrode rises. That is, light incident information is accumulated in the capacitor 300 as electric charges. After a certain accumulation time, the control unit 133 turns on the TFT 222 and shifts to the detection mode. At this time, the electric charge stored in the capacitor 300 is
Flows to the operational amplifier 126 side, and this charge corresponds to the integrated value of the current flowing out of the photoelectric conversion element 100 in the accumulation mode, that is, the operational amplifier 1
26, a capacitor 124, and a switch element 125. The control unit (not shown) turns on the switch element 125 and discharges the capacitor 124 to initialize the integrator before shifting to the detection mode. Further, after the TFT 222 is turned off, the control unit 131 turns on the TFT 220 again, and the following operation is repeated.

The feature of the present embodiment is that the integrated value of the current flowing during a fixed long accumulation time can be obtained in a short time in the detection mode by a simple combination of elements, and the operational amplifier is expensive. This indicates that a photoelectric conversion device having a high SN ratio and a plurality of photoelectric conversion elements with a light load can be configured at low cost. In the operation of the photoelectric conversion device of the present embodiment, the potential of the G electrode increases and V _dg decreases during the photoelectric conversion mode as in the first embodiment. This easily leads to the state shown in FIG. 5C with a small amount of incident light, which can limit the amount of incident light in normal operation. This can be improved by making the capacitor 300 sufficiently large. Conversely, when detection of a small amount of light is sufficient, the photoelectric conversion element 1 indicated by a dotted line without forming the capacitor 300 as an active element.
The stray capacitance C _{S of} 00 operates as a capacitance element and can operate. This stray capacitance C _S can be adjusted by the area of the upper electrode 106 of the photoelectric conversion element 100.

FIG. 15A is a plan view of the photoelectric conversion device shown in FIG. 14, and FIG. 15B is a cross-sectional view taken along a line AB shown in the plan view of FIG. Parts that cannot be shown in detail in FIG. 15A are indicated by the same symbols as in FIG. 100 is a photoelectric conversion element, 220 to 222 are TFTs,
Reference numeral 300 denotes a capacitor, and reference numerals 402 and 406 denote wirings for electrically connecting the elements, which are connected through contact holes 408. In FIG. 15B, 412 and 4
Reference numeral 16 denotes a wiring connected to another component. Here, a method for forming each element will be described in order with reference to FIG.

First, about 500 angstroms of Cr is deposited as a lower metal layer 2 on a glass substrate 1, which is an insulating material, by sputtering or the like, and then patterned by photolithography to etch unnecessary areas.
As a result, the lower electrode of the photoelectric conversion element 100, the TFT 22
Gate electrodes 0 to 222, a lower electrode of the capacitor 300, and lower wirings 402 and 412 are formed.

Next, the SiN layer 70 / i-layer 4 / n-layer 5 were each formed by CVD at about 2,000 / 500 in the same vacuum.
0 ° / 500 ° is deposited. These layers are the insulating layer / photoelectric conversion semiconductor layer / hole injection blocking layer of the photoelectric conversion element 100, the gate insulating film / semiconductor layer /
It becomes an ohmic contact layer and an intermediate layer of the capacitor 300. It is also used as a cross section insulating layer for upper and lower wiring. The thickness of each layer is not limited to this and can be optimally designed according to the voltage, current, charge, incident light amount, etc. used as a photoelectric conversion device. However, at least SiN cannot pass electrons and holes, and at the same time, as a TFT gate insulating film. It is desirable that the thickness be 500 Å or more that can function.

After the deposition of each layer, the area to become the contact hole 408 is etched, and then about 10,000 Å of Al is deposited as the upper metal layer 6 by sputtering or the like. Further, the unnecessary area is etched by patterning by photolithography, and the photoelectric conversion element 100 is etched.
, A source electrode and a drain electrode which are main electrodes of the TFTs 220 to 222, an upper electrode of the capacitor 300, and upper wirings 406 and 416. At the same time, in the contact hole 408, the lower wiring 402 and the upper wiring 406 are connected.

Further, only the channel portions of the TFTs 220 to 222 are etched by RIE for the n-layer, and then unnecessary Si is etched.
Each element is separated by etching the N layer 70 / i layer 4 / n layer 5. With this, the photoelectric conversion element 100 and the TFTs 220 to
222, lower wirings 402, 412, upper wirings 406, 4
16 and the contact hole 408 are completed.

Although not shown, the upper part of each element is usually covered with a passivation film such as SiN to improve the durability.

As described above, in this embodiment, the photoelectric conversion element 100, the TFTs 220 to 222, the capacitor 300,
And the common lower metal layer 2, SiN layer 70 / i layer 4 / n layer 5, and upper metal layer 6 on which the wiring section 400 and the wiring section 400 are simultaneously deposited. In addition, there is only one injection blocking layer in the photoelectric conversion element 100, and it can be formed in the same vacuum. Further TF
The gate insulating film / i-layer interface, which is important for the characteristics of T, can be formed in the same vacuum. Further, since the intermediate layer of the capacitor 300 includes an insulating layer with less heat leakage, a capacitor having good characteristics is formed. As described above, this embodiment enables production of a low-cost, high-performance photoelectric conversion device.

[Embodiment 8] FIG. 16 is a schematic overall circuit diagram of a photoelectric conversion device according to an eighth embodiment of the present invention.
FIG. 17A is a schematic plan view of each component corresponding to one pixel in the present embodiment, and FIG. 17B is a schematic A- of FIG.
It is B sectional drawing. In FIG. 16, S11 to S33 are photoelectric conversion elements, in which the lower electrode side is denoted by G and the upper electrode side is denoted by D.

The nine photoelectric conversion elements S11 to S33 are arranged one-dimensionally in a line, that is, in a line, on the same insulating substrate, ie, a glass substrate, and function as a sensor unit as a line sensor. C11 to C33 are storage capacitors which are capacitive elements, and Re11 to Re33 are initialization T
FT, Rf11 to Rf33 are refresh TFTs, Tf
11 to T33 are transfer TFTs. Transfer TFT ・ T
11, g, d, and s denote a gate electrode, a drain electrode, and a source electrode, respectively. When the potential of the gate electrode is set to a low voltage (hereinafter, referred to as Lo), non-conduction (off) occurs between the drain electrode and the source electrode. When a high voltage (hereinafter, referred to as Hi) is applied, the transistor is turned on and functions as a switch element. The same applies to other TFTs in the figure.

Reference numerals g1 to g5 denote wirings for controlling each TFT, and each TFT is controlled by a control pulse Hi / Lo generated by the shift register SR1. V _d is read power source connected in common to the D electrode of the photoelectric conversion elements S11 to S33, V _g is refresh TFT · Rf11
Rf33 are refresh power supplies commonly connected to the drain electrodes of Rf33. One pixel is composed of one photoelectric conversion element, a capacitor, and three TFTs, and its signal output is connected to a detection integrated circuit IC by a matrix signal wiring MTX. The photoelectric conversion device of this embodiment divides a total of nine pixels into three blocks, simultaneously processes the output of three pixels per block, and sequentially converts and outputs the outputs through the matrix signal wiring MTX by the integrated circuit IC for detection. . M1 to M3 in the detection integrated circuit IC are read switches, which are controlled via control lines sg1 to sg3 by Hi / Lo control pulses generated by the shift register SR2, and whose output is connected to the integration detector Amp. ing.
The integration detector Amp integrates the electric charge flowing through the read switches M1 to M3 and outputs the result as Vout.

In FIG. 16A, a portion surrounded by a broken line is formed on the same glass substrate having a large area, and a plan view of a portion corresponding to the first pixel is shown in FIG. FIG. 17B is a cross-sectional view of a portion indicated by a broken line AB in the drawing.
17, the same parts as those in FIG. 16 are indicated by the same symbols.

In FIGS. 17A and 17B, S11 is a photoelectric conversion element, Re11, Rf11, and T11 are TFTs,
C11 is a capacitor, and MTX is a matrix signal wiring. Here, a method for forming each element will be described in order with reference to FIG.

First, about 500 angstroms of Cr is deposited as a lower metal layer 2 on a glass substrate 1 which is an insulating material by sputtering or the like, and then patterned by photolithography to etch unnecessary areas.
Thereby, the lower electrode of the photoelectric conversion element S11, the TFT R
Gate electrode of e11, Rf11, T11, capacitor C
Eleven lower electrodes and the lower wiring of the matrix signal wiring MTX are formed.

Next, the SiN layer 70 / i-layer 4 / n-layer 5 are formed by CVD at about 2000/500 in the same vacuum.
0 ° / 500 ° is deposited. Each of these layers is a photoelectric conversion element S
11 insulating layer / photoelectric conversion semiconductor layer / hole injection blocking layer,
Gate insulating film of TFT / Re11, Rf11, T11 /
It becomes a semiconductor layer / ohmic contact layer and an intermediate layer of the capacitor C11. Also, the matrix signal wiring MT
It is also used as an insulating layer for X cross section. The thickness of each layer is not limited to this, and can be optimally designed according to the voltage, current, charge, incident light amount, etc. used as the photoelectric conversion device.
iN is preferably not less than 500 angstroms that cannot pass electrons and holes and can function as a gate insulating film of a TFT.

After depositing each layer, an area to be a contact hole is etched.
Is deposited to about 10000 angstroms by sputtering or the like. Further, unnecessary areas are etched by patterning by photolithography, and the upper electrode of the photoelectric conversion element S11, the source electrode and the drain electrode which are the main electrodes of the TFTs Re11, Rf11 and T11, the capacitor C11
And the upper wiring of the matrix signal wiring MTX are formed. At the same time, the lower wiring and the upper wiring are connected in the contact hole.

Further, the TFTs Re11, Rf11,
Only the n-layer is etched by RIE in the channel portion of T11,
Thereafter, the unnecessary SiN layer 70 / i layer 4 / n layer 5 is etched to separate each element. With this, the photoelectric conversion element S1
1, TFTs Re11, Rf11, T11, matrix signal wiring MTX, and contact holes are completed.
The first pixel has been described above, but it goes without saying that other pixels are formed at the same time.

Although not shown, in order to improve the durability, the upper portion of each element is usually covered with a passivation film such as SiN, and a thin glass plate of about 50 μm is bonded.

As described above, in this embodiment, the common lower metal layer 2 and the SiN layer 7 on which the photoelectric conversion element, TFT, capacitor, and matrix signal wiring are simultaneously deposited.
It can be formed only by etching the 0 / i layer 4 / n layer 5, the upper metal layer 6, and each layer. Further, the photoelectric conversion element has only one injection blocking layer and can be formed in the same vacuum. Further, the gate insulating film / i-layer interface, which is important for TFT characteristics, can be formed in the same vacuum. Further, since the intermediate layer of the capacitor includes an insulating layer with less heat leakage, a capacitor having good characteristics is formed.

Next, the operation of the photoelectric conversion device of this embodiment will be described with reference to FIGS. FIG. 18 is a timing chart showing the operation of this embodiment. As described above, the photoelectric conversion element in this embodiment operates as an optical sensor that outputs a photocurrent proportional to incident light in the photoelectric conversion mode if refreshed periodically.
Here, the operation of the pixels in the first block in the photoelectric conversion device will be described first.

It is assumed that a certain accumulation period has elapsed after the refresh in the photoelectric conversion elements S11 to S13 in FIG. Then, charges proportional to the integral value of the optical information incident during this period are accumulated in the capacitors C11 to C13. Here, a Hi control pulse is applied to the wiring g1 by the shift register SR1 as shown in FIG. Then transfer TFT
-T11 to T13 turn on and become conductive. At the same time, when control pulses are sequentially applied to the control lines sg1 to sg3 by the shift register SR2, the charges of the capacitors C11 to C13 are transferred to the integration detector Amp through the transfer TFTs T11 to T13, the matrix signal wiring MTX, and the read switches M1 to M3. The data is transferred and sequentially output to Vout as v1 to v3 (although not shown, the integration detector Amp is initialized before the transfer of each charge). This output is proportional to the integral value of the optical information incident on the photoelectric conversion elements S11 to S13 during a certain accumulation period. Next, when a control pulse is applied to the wiring g2 as shown in FIG.
T · Rf11 to Rf13 conduct and the photoelectric conversion elements S11 to S11
G electrode in S13 is increased by the refresh power supply V _g. Then, the holes in the photoelectric conversion element are swept out and refreshed. Next, when a control pulse is applied to the wiring g3, the resetting TFTs Re11 to Re13 conduct, and the refreshing of the photoelectric conversion elements S11 to S13 ends, and the capacitors C11 to C13 are initialized. Wiring g
When 3 becomes Lo, the G electrodes of the photoelectric conversion elements S11 to S13 become DC open, but the capacitors C11 to C1 become open.
3 holds the potential. From here, the accumulation period of the next cycle is started, and the optical information incident on the photoelectric conversion elements S11 to S13 is accumulated in the capacitors C11 to C13 until the next control pulse is applied to the wiring g1, and the operation is repeated thereafter.

The operation of the first block has been described so far. However, the control wirings g2 to g4 are provided in the second block, and the control wirings g3 to g5 are provided in the third block. A pulse is applied, and they operate simultaneously while shifting each block time. However, since the operation is performed by shifting one pulse at a time, signals of a plurality of blocks do not simultaneously flow through the matrix signal wiring MTX, and the light incident on the photoelectric conversion elements S11 to S33 is denoted by vout as v1 to v9 as illustrated. Information is output as an optical signal.

In FIG. 17B, the portions indicated by broken lines are the light path (arrow) and the original 1000 when the original is read by using the photoelectric conversion device constructed in this embodiment. LED
For example, the document 1000 is illuminated from the back surface of the glass substrate 1 through a window beside the photoelectric conversion element. Reflected light containing information on characters and pictures written on the document 1000 is incident on the photoelectric conversion elements S11 to S33 arranged in a line, and is sequentially output by the present photoelectric conversion device. After outputting one line, the original is shifted by an appropriate amount, and one line is read. This can be repeated to convert the image information of the entire original into an electric signal. In this embodiment, one line is composed of nine pixels. However, the present invention is not limited to this. For example, 1728 pixels are arranged in a line at 8 pixels per mm, divided into 36 blocks, and processed in units of 48 pixels. Then, a photoelectric conversion device for A4 facsimile can be configured.

As described above, the photoelectric conversion device of this embodiment divides a plurality of photoelectric conversion elements into n blocks, and sets m for each block.
By controlling the TFTs simultaneously with one control line, the optical signals of the n × m photoelectric conversion elements are output to the matrix signal wiring, so that the optical signals can be output with a small number of control wirings and a small number of detection circuits. It is possible. The gate of m TFTs of one block is controlled by one control wiring, and the m TFs of other functions of other blocks are controlled.
The number of control wirings is further reduced by controlling the gate of T at the same time.

As described above, in this embodiment, the common lower metal layer 2 and the SiN layer 7 on which the photoelectric conversion elements, TFTs, capacitors, and matrix signal wirings are simultaneously deposited.
It can be formed only by etching the 0 / i layer 4 / n layer 5, the upper metal layer 6, and each layer. The fact that the number of steps for forming each layer is small as described above makes it difficult for defects to occur during the steps. In particular, when a photoelectric conversion device having a large number of pixels as described above is manufactured, the yield can be improved. As described above, this embodiment enables production of a large-area, high-performance photoelectric conversion device at low cost.

[Embodiment 9] FIG. 20 is an overall circuit diagram showing a ninth embodiment of the photoelectric conversion device of the present invention, and FIG. 20 (a) is a plan view of each component corresponding to one pixel in this embodiment. FIG. 2
0 (b) is a sectional view taken along line AB in FIG. 20 (a). Parts having the same functions as those in FIGS. 16 and 17 are denoted by the same reference numerals. In FIG. 19, S11 to S33 are photoelectric conversion elements, in which the lower electrode side is indicated by G and the upper electrode side is indicated by D.
C11 to C33 are storage capacitors, and T11 to T33 are transfer TFTs. V _S is a read power supply, V _g is refresh power supply, the switches SWs, S
It is connected to the G electrodes of all the photoelectric conversion elements S11 to S33 via Wg. The switch SWs is directly connected to the refresh control circuit RF via the inverter, and the switch SWg is directly connected to the refresh control circuit RF.
SWg is on during the refresh period,
In other periods, SWs is controlled to be turned on.
One pixel has one photoelectric conversion element, one capacitor, and TF
The signal output is connected to a detection integrated circuit IC by a signal wiring SIG. The photoelectric conversion device according to the present embodiment divides a total of nine pixels into three blocks and simultaneously transfers the outputs of three pixels per block.
The signals are sequentially converted into outputs by the integrated circuit IC for detection through G and output (Vout). Each pixel is two-dimensionally arranged by arranging three pixels in one block in the horizontal direction and sequentially arranging the three blocks in the vertical direction.

In FIG. 20, a portion surrounded by a broken line is formed on the same insulating substrate having a large area, and a plan view of a portion corresponding to the first pixel is shown in FIG. The broken line A in the figure
FIG. 20B is a cross-sectional view of the portion indicated by -B. S1
1 is a photoelectric conversion element, T11 is a TFT, C11 is a capacitor, and SIG is a signal wiring. In this embodiment, the capacitor C11 and the photoelectric conversion element S11 are not specially separated from each other, and the capacitor C11 is formed by increasing the area of the electrode of the photoelectric conversion element S11. This is a feature of the present embodiment because it is possible because the photoelectric conversion element and the capacitor of the present embodiment have the same layer configuration. The method of forming each layer is almost the same as that of the first embodiment, but since there is no contact hole, there is no etching for the formation. Further, a passivation silicon nitride film SiN and a phosphor CsI such as cesium iodide are formed above the pixels. When an X-ray (X-ray) is incident from above, it is converted into light (broken arrow) by the phosphor CsI, and this light is incident on the photoelectric conversion element.

Next, the operation of the photoelectric conversion device of this embodiment will be described with reference to FIGS. FIG. 21 is a timing chart showing the operation of this embodiment.

First, shift registers SR1 and SR
2, Hi is applied to the control wirings g1 to g3 and sg1 to sg3. Then, the transfer TFTs T11 to T33 and the switches M1 to M3 are turned on to conduct, and all the photoelectric conversion elements S1
The D electrodes 1 to S33 have the GND potential (integral detector A
mp input terminal is designed to GND potential).
The G electrodes of Zenhikariden conversion element S11~S33 and on the refresh control circuit RF outputs a Hi switch SWg is simultaneously a positive potential by the refresh power supply V _g. Then, all the photoelectric conversion elements S11 to S33 enter the refresh mode and are refreshed. Then G electrodes of the refresh control circuit RF is on the switch SWs outputs Lo Zenhikariden transducer S11~S33 becomes negative potential by the reading power supply V _S. Then, all the photoelectric conversion elements S11 to S3
3 is in the photoelectric conversion mode, and at the same time, the capacitors C11 to C
33 is initialized. In this state, the shift register SR1
Control lines g1 to g3, sg1 to sg
Lo is applied to 3. Then, the transfer TFTs T11-T11
The switches M1 to M3 of T33 are turned off, and the D electrodes of all the photoelectric conversion elements S11 to S33 are DC open, but the potential is held by the capacitors C11 to C33. However, at this time, no X-rays have been incident, so that no light enters the photoelectric conversion elements S11 to S33 and no photocurrent flows. In this state, when X-rays are emitted in a pulsed manner, pass through a human body or the like, and enter the phosphor CsI, they are converted into light, and the light enters the respective photoelectric conversion elements S11 to S33. This light contains information on the internal structure of the human body and the like.
The photocurrent flowing by this light is accumulated as a charge in each of the capacitors C11 to C33, and is held even after the end of X-ray incidence. Next, a control pulse of Hi is applied to the control line g1 by the shift register SR1, and the shift register S
The transfer TFTs T11 to T13 and the switches M1 to M13 are applied by applying a control pulse to the control lines sg1 to sg3 of R2.
3, v1 to v3 are sequentially output. Similarly, other optical signals are sequentially output under the control of the shift registers SR1 and SR2. Thereby, two-dimensional information of the internal structure of the human body or the like is obtained as v1 to v9. The operation up to this point is performed to obtain a still image, but the operation up to here is repeated to obtain a moving image.

[0132] G electrodes of the photoelectric conversion element in the present embodiment are connected in common, because it controls the common wiring via the switch SWg and a switch SWs to the power supply V _g and the reading power supply V _S potential refreshing All the photoelectric conversion elements can be simultaneously switched between the refresh mode and the photoelectric conversion mode. Therefore, light output can be obtained with one TFT per pixel without complicated control.

In this embodiment, nine pixels are two-dimensionally arranged in 3 × 3, and three pixels are simultaneously transferred and output in three divisions. However, the present invention is not limited to this. For example, 5 × 5 pixels per 1 mm (vertical and horizontal) are used. If the pixels are two-dimensionally arranged as 2000 × 2000 pixels, a 40 cm × 40 cm X-ray detector can be obtained.
If this is combined with an X-ray generator instead of an X-ray film to constitute an X-ray radiograph, it can be used for chest X-ray examination and breast cancer examination. Then, unlike a film, the output can be instantly projected on a CRT, and further, the output can be converted into digital, processed by a computer, and converted into an output suitable for the purpose. It can also be stored on a magneto-optical disk, and past images can be searched instantaneously. Also, the sensitivity is better than that of a film, and a clear image can be obtained with weak X-rays having little effect on the human body.

FIGS. 22 and 23 are conceptual diagrams showing the implementation of a detector having 2000 × 2000 pixels. 2000
In the case of configuring × 2000 detectors, the number of elements in the broken line shown in FIG. 19 may be increased in the vertical and horizontal directions. In this case, the number of control wirings is g1 to g2000, and the number of control wirings is 2,000.
The number of IGs is also sig1 to sig2000 and 2000.
Also, the shift register SR1 and the integrated circuit IC for detection are 20
The control and processing of 00 pieces must be performed, and the scale becomes large.
Performing this process with one chip element is disadvantageous in terms of yield, cost, and the like during manufacture because one chip becomes very large. Therefore, the shift register SR1 is formed on one chip for every 100 stages, for example, and 20 (SR1-1 to SR1)
-20) may be used. The integrated circuit for detection is also 10
0 processing circuits are formed on one chip, and 20 (I
C1 to IC20).

In FIG. 22, 20 chips (SR
1-1 to SR1-20) and 20 chips mounted on the lower side (D)
And 100 control lines and signal lines per chip.
Each wire is connected to the chip by wire bonding.
The broken line in FIG. 22 corresponds to the broken line in FIG. Also external
The connection to is omitted. SWg, SWs,
V _g, V_S, RF, etc. are also omitted. Detection integrated circuit IC
There are 20 outputs (Vout) from 1 to IC20
However, these are combined into one via a switch or the like,
What is necessary is just to output 0 lines as they are and perform parallel processing.

Alternatively, as shown in FIG. 23, 10 chips (SR1-1 to SR1-10) are located on the left side (L), and
10 chips (SR1-11 to SR1-20), 10 chips (IC1 to 10) on the upper side, and 10 chips (IC11 to 20) on the lower side (D). This configuration is
Connect each wiring to the bottom, left and right (U, D, L, R)
Since the wires are distributed every 000 lines, the density of wiring on each side is reduced, and the density of wire bonding on each side is also small, so that the yield is improved. .., G1999 on the left (L) and g2, g4, g6,..., G2000 on the right (R), that is, odd-numbered control lines are on the left (L) and even-numbered Distribute control to the right (R). In this case, the wirings are drawn out at equal intervals and wired, so that the yield is further improved without concentration. Also, the wiring to the upper side (U) and the lower side (D) may be similarly distributed. Although not shown, as another embodiment, the wiring is distributed on the left side (L) by g1 to g100,
, g1801 to g1900, and g101 to g200, g301 to g400,
.., G1901 to g2000, that is, a continuous control line is distributed for each chip, and the control lines are distributed alternately to the left and right (L, R). In this case, the inside of one chip can be controlled continuously, the drive timing is easy, the circuit is not complicated, and an inexpensive device can be used. The same applies to the upper side (U) and the lower side (D), and an inexpensive circuit capable of continuous processing can be used.

The examples shown in FIG. 22 and FIG.
After the circuit indicated by the broken line is formed on one substrate, a chip may be mounted on the substrate, or the circuit board and the chip indicated by the broken line may be mounted on another large substrate. Alternatively, the chip may be mounted on a flexible substrate and attached to the circuit board indicated by a broken line to make a tangent.

Although a large-area photoelectric conversion device having such a large number of pixels cannot be realized by a complicated process using a conventional optical sensor, the process of the photoelectric conversion device according to the present invention is performed by each element. Are formed simultaneously with a common film, so that the number of steps is small, and simple steps are sufficient, so that a high yield can be achieved, and a low-cost, large-area, high-performance photoelectric conversion device can be produced. Further, the capacitor and the photoelectric conversion element can be configured in the same element, and the number of elements can be substantially reduced by half, and the yield can be further improved.

Next, the inrush current and the refresh operation by the TFT will be described again for understanding the present invention. FIG. 24 is a 1-bit equivalent circuit diagram of a photoelectric conversion device including a TFT 1700 and a power supply 1115, and FIG.
5 is a timing chart showing the operation.

Here, in order to simplify the explanation, the TFT 1
A positive potential is applied to the G electrode of the photoelectric conversion element through 700
1 bit of the photoelectric conversion device shown in FIG.
The description will be made with reference to a circuit diagram. And D of the photoelectric conversion element
The potential of the electrode is V_D Designed for reflation
The potential of the G electrode during the flash operation is V _rG
Shall be set to

Here, since the photoelectric conversion element 100 has the same configuration as that of the photoelectric conversion element 100 shown in Embodiment 1 described above, it will be described below with reference to FIG.

[0142] As shown in FIG.
When the potential (V _O ) of the G electrode of 0 is refreshed to the potential (V _D ) of the D electrode or more (V _O = V _rG ≧ V _D ), the holes and i remaining in the i layer 4 of the photoelectric conversion element 1100 All the holes trapped by the interface defects existing at the interface between the layer 4 and the insulating layer 70 are completely swept out to the D electrode. Conversely, electrons flow from the D electrode into the i-layer 4 at this time,
A part thereof is trapped by an interface defect existing at the interface between the i-layer 4 and the insulating layer 70. Hereinafter, this current is referred to as a negative inrush current. After the refresh operation is completed, the photoelectric conversion element 1
When the potential of the G electrode of 00 is initialized to a GND potential or the like, i
All the electrons trapped in the layer 4 and at the interface defects are D
Swept out to the electrodes. Hereinafter, this current is referred to as a positive inrush current. Since the interface defect existing at the interface between the i-layer 4 and the insulating layer 70 generally has a deep energy level, the energy for moving the electrons and holes existing at the interface defect position, and the electrons and holes from other positions to the interface defect position. Is relatively high in energy, and the apparent mobility is low.
Therefore, it takes several tens of microseconds to several seconds until the positive rush current becomes zero, that is, until all the electrons trapped in the interface defect are swept out to the D electrode, and the G electrode reset operation ends. A large inrush current flows. As a result, the charge accumulated in the capacitance of the G electrode includes the charge due to the rush current, which is a noise component, and as a result, the S / N ratio is reduced by the charge.

For the above reason, FIG. 24 and FIG.
This will be described in detail with reference to FIG.

In FIG. 25, Pa, Pb, Pc and Pd are the switch element 1125 and the transfer TFT 13 in FIG.
00, refresh TFT 1700, reset TF
The timing of a high-level pulse for driving T1400 is shown. Here, H indicates a high level that turns on each drive element. Generally, +5 V to +12 V for a crystalline silicon semiconductor switch element and + for a-Si TFTs.
A voltage of 8 to +15 V is used. In general, 0 V is often used for L. As shown by arrows in FIG. 24, I _S and V _O indicate the current flowing in the direction of the arrow and the potential of the G electrode when the photoelectric conversion element 100 is irradiated with a constant signal light, respectively. Here, the pulse width of Pa to Pd is 2
FIG. 25 shows I _S and V _O during the operation of 0 microsecond.

In FIG. 25, V _O is kept at a constant high potential from the rising of the refresh pulse of Pc to the rising of the reset pulse of Pd. Therefore, a positive rush current does not occur during that period, and a positive rush current is generated only at the rising edge of the Pd pulse, which is considered to be due to the sweeping out of the electrons trapped by the interface defects described above. Since it takes about 80 to 100 microseconds in the device manufactured by us until the positive inrush current is attenuated and becomes almost zero, when the pulse of Pd which starts to accumulate signal charges in the capacitance of the G electrode, the positive A large amount of inrush current is generated, and the charges and voltage values in the hatched portions in the figure are accumulated as noise components. As a result, the accumulated S / N ratio decreases. As a method of reducing the positive rush current, it is conceivable to lengthen the time of the Pd reset pulse. However, there is a limit to that time, and by increasing the time, the signal reading time of the entire apparatus becomes longer. This causes a reduction in the speed of the device, that is, a decrease in performance.

Next, the condition of the applied voltage when the photoelectric conversion element 100 is refreshed will be described with reference to FIG.

FIG. 26 is an energy band diagram of the photoelectric conversion element 100. Each electrode (D electrode and G electrode) at both ends is in an open state. Photoelectric conversion element 10
0 is a commonly-known MIS (Metal-Insu
It has a lateral-semiconductor structure, and a state in which the total capacity is relatively small (depression state) and a state in which the total capacity is relatively large (accumulation state) appear depending on voltage conditions applied to the electrodes at both ends.

Although both ends of each device in FIG. 26 are open, the energy band diagram is shown in FIG.
The case of (b) is the same as the energy band diagram in the depletion state, and the case of FIG. 26 (c) is the same as the energy band diagram in the accumulation state.

Generally, the MIS capacitor is in the state shown in FIG. 26A, that is, the state in which the band of the i-layer is flat (flat band voltage V _FB = 0 V) immediately after fabrication, or in FIG.
State (b), that is, a slightly depleted state (3V ≧ V _FB
> 0V) in many cases. Further, by applying a voltage to both ends of the MIS capacitor, V _FB can be set to arbitrary positive and negative values to some extent.

From the above, the conditions of the voltage value that causes a positive inrush current (a long decay time and a large current value) are summarized below.

First, when the flat band voltage V _FB of the i-layer of the photoelectric conversion element 100 is zero, if the potential (V _rG ) of the G electrode during refresh is higher than the potential (V _D ) of the D electrode,
That is, if the V _rG> V _D, positive inrush current flows.

When the flat band voltage V _FB of the i-layer of the photoelectric conversion element 100 is not zero, the potential of the G electrode (V _rG ) at the time of refreshing is a voltage obtained by subtracting V _FB from the potential of the D electrode (V _D ). Higher than or equal to the value, ie V
inrush current positive if _rG ≧ V _D -V _FB is the flow.

The above mechanism will be described with reference to FIG.

FIG. 27 is an energy band diagram of the photoelectric conversion element 1100 when V _rG ≧ V _D −V _FB , and shows the state in the thickness direction of each layer from the lower electrode layer 2 to the transparent electrode layer 6 in FIG. Is represented. In FIG. 27A of the refresh operation, since the D electrode is given a negative potential with respect to the G electrode, holes indicated by black circles in the i layer 4 are guided to the D electrode by an electric field. At the same time, electrons indicated by white circles are injected into the i-layer 4. The holes trapped in the interface defects between the i-layer 4 and the insulating layer 70 take a certain amount of time to be led to the D electrode, and some of the electrons injected into the i-layer 4 have a certain time. Is trapped in interface defects between the i-layer 4 and the insulating layer 70. At this time, some holes and electrons are n
The layer 5 and the i-layer 4 recombine and disappear. If this state continues for a sufficiently long time, holes in the i-layer 4 are swept out of the i-layer 4. In this state, when the photoelectric conversion operation is as shown in FIG. 27B, the D electrode is given a positive potential with respect to the G electrode, so that the electrons in the i layer 4 are instantaneously guided to the D electrode. And i
The electrons trapped by the interface defect between the layer 4 and the insulating layer 70 are led to the D electrode with some time. The electrons trapped by this interface defect are the cause of the rush current of the above-mentioned problem. Here, the holes are not guided to the i-layer 4 because the n-layer 5 functions as an injection blocking layer. When light enters the i-layer 4 in this state, the light is absorbed and electron-hole pairs are generated. These electrons are guided to the D electrode by the electric field,
The holes move in the i-layer 4 and reach the interface between the i-layer 4 and the insulating layer 70. However, since it cannot move into the insulating layer 70, i
It will stay in layer 4. Some holes are trapped by interface defects. FIG. 27C shows a state after the photoelectric conversion operation shown in FIG. 27B is maintained for a certain period.

Hereinafter, another embodiment of the present invention will be described in detail with reference to the drawings.

[Embodiment 10] FIG. 28 shows a tenth embodiment of the present invention.
FIG. 3 is a schematic equivalent circuit diagram of one bit of the photoelectric conversion device according to the example of FIG. FIG. 29 is a timing chart when the photoelectric conversion device of FIG. 28 is actually driven.

In FIG. 28, the portions indicated by the same reference numerals as those in FIG. 24 are the same, and the description is omitted. The difference between the schematic equivalent circuit shown in FIG. 24 and this embodiment is the size of the power supply connected to the TFT 1700.

Here, the photoelectric conversion unit 100 corresponds to FIG.
Since it has the same structure as (a), the injection blocking layer between the i-layer and the second electrode layer is an n-type semiconductor layer, and the carriers whose injection is blocked are holes. Therefore, assuming that the charge of one carrier whose injection is blocked is q, q> 0 in this case.

In this embodiment, the signal detecting section is the one shown in FIG.
8 includes a detection unit within the dotted line, a TFT 1300, and a unit for applying a high-level pulse Pb.

FIG. 28 differs from FIG. 24 in that the potential V _rG of a power supply 1115 for applying a positive potential to the G electrode and the potential V _rG of a power supply 114 for applying a positive potential to the D electrode in the refresh operation of the photoelectric conversion element 100 are different from those of FIG. _The only difference is that it is lower than _D. More specifically, the photoelectric conversion element 100
In order to make the energy band of the i-layer flat,
Since the flat band voltage (V _FB ) to be applied to the electrode exists, in the example of FIG. 24, the driving is performed in a state of V _rG ≧ V _D −V _FB , whereas in the example of FIG. Then V _rG
Drive in the state of <V _D -V _FB .

Next, the operation of the photoelectric conversion device of this embodiment will be described with reference to FIG.

FIG. 29 is different from FIG.
Current I of conversion element 100_SAnd current I _S Of the G electrode by
Potential V_OIs the behavior.

In FIG. 29, the refresh pulse of Pc rises, and the voltage V _rG is applied to the G electrode of the photoelectric conversion unit 100.
When (V _rG <V _D −V _FB ) is applied, the photoelectric conversion unit 100
Some of the holes remaining in the i-layer are swept out to the D electrode. At this time, it is considered that almost all of the holes trapped by the interface defect between the i-layer and the insulating layer remain as they are. Also, at this time, an amount of electrons corresponding to a part of the holes swept out to the D electrode or less flows from the D electrode into the i-layer, but the electric field in the i-layer has a low potential on the G-electrode side. Therefore, it is considered that the number of electrons trapped by the interface defect between the i-layer and the insulating layer is almost zero. Therefore, FIG.
I _S without only small negative inrush current occurring at the time of the refresh pulse rise of the Pc, also has shorter decay time at 9. FIG. 2 also shows that the voltage V _O of the G electrode from the rising of the refresh pulse of Pc to the rising of the reset electrode of Pd substantially coincides with V _rG , and that the potential is lower than V _D −V _FB .
9 shows.

Next, the G electrode reset pulse rises,
When the G electrode of the photoelectric conversion unit 100 is grounded to GND, some of the electrons remaining in the i-layer flow out to the D electrode. At this time, since no electrons exist at the interface defect between the i-layer and the insulating layer, it is considered that the electrons flow out in a small amount and instantaneously. At this time, it seems that the holes existing in the interface defects hardly move. Therefore, when the Pd G electrode reset pulse rises, _IS has only a small positive rush current, and the decay time is short. When the operation from the rising to the falling of the Pd G electrode reset pulse is performed in about 20 microseconds, the rush current becomes almost zero at the time of the falling of the Pd pulse which starts the photoelectric conversion operation as shown in the figure. Therefore, almost all charges starting to be accumulated from the falling edge of the pulse of Pd become charges due to the signal light incident on the photoelectric conversion unit 100, and reading out the signal voltage makes it possible to obtain information with a high SN ratio. . Here, the elements for signal detection within the square dotted line shown in FIG. 28 are not particularly limited, as long as the current or charge can be detected directly or by an integrated value.
In the case where reading is performed by an ammeter or the like without being stored in the memory 124, the reading capacitor 1124 and the potential initializing switch element 1125 can be omitted, but this is the same as described above.

Hereinafter, the basic mechanism in the tenth embodiment of the present invention will be described in more detail with reference to the drawings.

FIGS. _{30A to 30C} show V _rG <V _D
FIG. 28 is an energy band diagram illustrating the operation of the photoelectric conversion unit 100 in the case of −V _FB , and corresponds to the energy band diagrams illustrated in FIGS. 27 (a) to 27 (c).

In FIG. 30A of the refresh operation, since the D electrode is given a positive potential with respect to the G electrode,
Some of the holes indicated by black circles in the i-layer 4 become D
Guided to the electrodes. At the same time, electrons indicated by white circles are injected into the i-layer 4. Here, the holes trapped by the interface defects between the i-layer 4 and the insulating layer 70 hardly move, and electrons are not trapped by the interface defects.

In this state, when the photoelectric conversion operation is as shown in FIG. 30B, the G electrode is applied with a larger negative potential than the D electrode, so that the electrons in the i layer 4 are instantaneously guided to the D electrode. Since almost no electrons are trapped in the interface defect, there is almost no rush current which is a problem in the above-described photoelectric conversion device shown in FIG.

FIG. 30 shows the photoelectric conversion operation for a certain period.
FIG. 30C shows the state after the state shown in FIG.

As described above, in the present embodiment, since there is almost no electron at the interface defect between the i-layer 4 and the insulating layer 70, it is not necessary to spend a long time for entering and exiting the electron. Inrush current, which is a noise component, can be greatly reduced.

[Eleventh Embodiment] An eleventh embodiment will be described with reference to FIGS. FIG. 31 is a schematic equivalent circuit diagram of a photoelectric conversion device showing an eleventh embodiment of the present invention.
However, here, a case of a photoelectric conversion element array having nine one-dimensionally arranged photoelectric conversion elements is taken as an example.

FIG. 32 shows a photoelectric conversion section 100 having a plurality of pixels in the longitudinal direction, a refresh TFT section 1700, a transfer TFT section 1300, a reset TFT section 1400,
FIG. 14 is a schematic plan view showing one pixel in a set of wiring sections 1500.

In FIG. 32, the photoelectric conversion unit 100 has a lower electrode 2 which also serves as a light shielding film for light from the substrate side. Light emitted from the substrate side is reflected by an original surface (not shown) positioned vertically above the drawing through the lighting window 17, and the reflected light enters the photoelectric conversion element 100. The photocurrent generated by the carriers generated here is converted to the photoelectric conversion element 10.
It is stored in an equivalent capacitance component of 0 and other stray capacitance. The accumulated charges are transferred to the signal line matrix wiring section 500 by the transfer TFT 300 and read as a voltage by a signal processing section (not shown).

Here, the second electrode layer is not particularly a transparent electrode. In the embodiment, the injection-blocking layer between the i-layer and the second electrode layer is n-type, and the carriers whose injection is blocked are holes. Therefore, if the charge of one carrier whose injection is blocked is q, q> 0 also in this case.

Next, a method of driving the photoelectric conversion device according to the eleventh embodiment will be described with reference to a circuit diagram.

In FIG. 31, photoelectric conversion elements S1 to S9
, Three blocks constitute one block, and three blocks constitute a photoelectric conversion element array. Refreshing TFT-F1 connected to each of the photoelectric conversion elements S1 to S9
To F9, TFT-R1 to R9 for initializing the G electrode potential of photoelectric conversion elements S1 to S9, and TFT-T for signal charge transfer
The same applies to 1 to T9.

The individual electrodes having the same order in each block of the photoelectric conversion elements S1 to S9 are each provided with a transfer TFT-T.
It is connected to one of the common lines 1102 to 1104 via 1 to T9. More specifically, the first transfer TFT-T1, T4, T7 of each block is on the common line 1102, the second transfer TFT-T2, T5, T8 of each block is on the common line 1103, and Third transfer TF of
T-T3, T6, and T9 are connected to the common line 1104, respectively. The common lines 1102 to 1104 are connected to the amplifier 112 via the switching transistors T100 to T120, respectively.
6 is connected.

In FIG. 3, common lines 1102 to 110
04 are grounded via common capacitors C100 to C120, respectively, and are connected to a switching transistor CT1.
To CT3. Here, the gate electrodes of the switching transistors CT1 to CT3 are commonly connected and turned on at the same timing as the pulse of Pa shown in FIG.
The residual charge of the transistor 104 is discharged to GND, and the potential is initialized. In this embodiment, the refresh means is a TFT.
-F1 to F9, shift register 1108, power supply 111
5. The power supply 114 is provided, and the signal detection unit is a detection unit shown in a dotted line in FIG.
6 inclusive.

Next, the operation of the eleventh embodiment will be described in chronological order.

First, when signal light enters the photoelectric conversion elements S1 to S9, electric charges are accumulated in the equivalent capacitance component of each photoelectric conversion unit 100 and each floating capacitance according to the intensity of the signal light. When a high level is output from the first parallel terminal of the shift register 1106 and the transfer TFTs-T1 to T3 are turned on, the charges accumulated in the respective capacitance components and the respective floating capacitances are respectively transferred to the common capacitor C100. To C120. Subsequently, the high level output from the shift register 1107 shifts, and the switching transistors T100 to T120 are sequentially turned on. Thus, the first capacitors transferred to the common capacitors C100 to C120
The optical signals of the blocks are sequentially read through the amplifier 1126.

After the transfer TFTs T1 to T3 are turned off, a high level is output from the first parallel terminal of the shift register 1108, and the refresh TFTs T1 to T3 are turned off.
F3 is turned on, and the potential of the G electrodes of the photoelectric conversion elements S1 to S3 increases. At this time, the potential V _{rG of the} power supply 1115
Are the potential V _D of the power supply 114 and all the photoelectric conversion elements S1 to S
9, the maximum flat band voltage V _FB is V _rG <V
Set to the relationship of _D - _VFB . Then, the photoelectric conversion element S1
Some of the holes in .about.S3 are swept out to the common power supply line 1403.

Next, a high level is output from the first parallel terminal of the shift register 1109, and the reset TFT-R
1 to R3 are turned on so that the photoelectric conversion element S1
Are reset to GND. Then, the common capacitors C100 to C1 are supplied by the pulse of Pa.
The potential of 20 is initialized. Common capacitor C100 ~
When the potential of C120 is completely initialized, the shift register 1106 shifts, and a high level is output from the second parallel terminal. Thereby, the transfer TFTs T4 to T4
6 is turned on, and the photoelectric conversion element S4 of the second block is turned on.
The signal charges accumulated in the equivalent capacitance component and the floating capacitance of S6 to S6 are transferred to the common capacitors C100 to C120. Then, as in the case of the first block, the shifting of the shift register 1107 turns on the switching transistors T100 to T120 sequentially, and the optical signals of the second block stored in the common capacitors C100 to C120 are sequentially read.

Similarly, in the case of the third block, a charge transfer operation and an optical signal read operation are performed.

As described above, by a series of operations from the first block to the third block, one operation in the main scanning direction of the original is performed.
Reading of the signal for the line is completed, and the read signal is output in an analog manner according to the magnitude of the reflectance of the document, that is, the magnitude of the incident light amount.

In the description of the tenth and eleventh embodiments, holes and electrons may be reversed. For example, the injection blocking layer may be a p-layer. In this case, in the tenth and eleventh embodiments described above, if the direction in which the voltage or the electric field is applied is reversed and the other parts are configured in the same manner, the same operation result as in the above-described embodiment can be obtained. In such a case, the charge q of one carrier whose injection is blocked by the injection blocking layer is q <0.

In the eleventh embodiment, a one-dimensional line sensor has been described. However, if a plurality of line sensors are arranged, a two-dimensional area sensor can be used, and an X-ray imaging device or the like can read an image at the same magnification. It is needless to say that the photoelectric conversion device can be configured by using the block division driving described in the above embodiment.

As described above, the eleventh embodiment is the first embodiment.
Since the photoelectric conversion element, TFT, and matrix signal wiring portion have the same film configuration in addition to the embodiment of Example 0, they can be formed simultaneously in the same process, so that miniaturization and high yield are possible, low cost, and high SN ratio. Can be realized.

[Embodiment 12] FIG. 33 is a schematic equivalent circuit diagram of one bit of the photoelectric conversion device of this embodiment, and FIG. 34 is a timing chart for explaining an example of driving the photoelectric conversion device of FIG. It is.

In FIG. 33, the same members as those in FIG. 28 indicate the same members. 33, one electrode of a capacitor 1200 is electrically connected to the photoelectric conversion unit 100 instead of the TFT 1700 of FIG. 28, and the other electrode of the capacitor 1200 is connected to the refresh pulse generating means Pc.

The capacitor 1200 functions as a pulse applying capacitance means for applying a positive potential to the G electrode in the refresh operation of the photoelectric conversion unit 100.

Reference numeral 1300 denotes a TFT for transferring signal charges in the detection operation, and reference numeral 1400 denotes an initialization TFT for initializing the potential of the G electrode. The inside of the square dotted line represents a signal detection unit, which is generally constituted by an IC or the like, and is shown as one example in FIG. Here, 1124 is a read capacitor, 1
Reference numeral 125 denotes a switch element for initializing the read capacitor 1124, and 1126 denotes an operational amplifier. The signal detection unit is not limited to this example, and may be any device as long as it can detect current or charge directly or by an integrated value. For example, when the signal charge is not stored in the reading capacitor 1124 and read by an ammeter or the like, the reading capacitor 1124 and the potential initialization switch element 1125 can be omitted.

Hereinafter, an example of the operation of the photoelectric conversion device of this embodiment will be described with reference to FIG.

In the refresh operation of the photoelectric conversion element, the refresh high-level pulse Pc is applied to the electrode opposite to the G electrode of the capacitor 1200 as shown in FIG. The configuration is such that the potential of the electrode rises.
Therefore, the holes remaining in the photoelectric conversion unit 100 are swept out to the D electrode, and the photoelectric conversion unit 100 is refreshed. Thereafter, at the same time as the refresh pulse of Pc falls, the potential of the G electrode, which is the opposite electrode of the capacitor 1200, also instantaneously drops. Therefore, the sweeping out of the holes remaining in the photoelectric conversion unit 1100 to the D electrode ends, and the photoelectric conversion ends. It works. Actually, since a positive rush current as shown in FIG. 34 is generated and attenuated gradually in the photoelectric conversion unit 1100, the photoelectric conversion operation starts after the rush current flows. Next, the TFT 1400 is turned off by a low potential (hereinafter, also referred to as low level) pulse of Pd, and the G electrode is opened DC. However, actually, the potential is maintained by the capacitance of the capacitor 1200 and the equivalent capacitance component and stray capacitance of the photoelectric conversion unit 1100. Here, when an optical signal of the photoelectric conversion unit 1100 is incident, a corresponding current flows from the G electrode and the potential of the G electrode rises. In other words, light incident information is accumulated as charges in the capacitance of the G electrode. After a certain accumulation time, the transfer TFT 1300 is turned from the off state to the on state by the high-level pulse of Pb, and the accumulated electric charge flows to the capacitor 1124. This electric charge is the current of the electric current flowing out of the photoelectric conversion unit 100 in the photoelectric conversion operation. It is a value proportional to the integral value, that is, the operational amplifier 1
It is detected by the detection unit through 126. Before this transfer operation, the potential of the capacitor 1124 is
It is preferable that the potential is initialized to the GND potential by a high-level pulse of 5 Pa. And the transfer TFT 130
0 is turned off, the refresh TFT 17
00 is turned on by the high level pulse of Pc,
Hereinafter, a series of operations are repeated. In this embodiment, the refreshing means includes a capacitor 1200, a means for applying a high-level pulse Pc, and a power supply 114, and the signal detecting unit is a detecting means within a dotted line in FIG.
0 and means for applying a high-level pulse Pb.

In the present embodiment, a positive potential is applied to the G electrode of the photoelectric conversion element via the capacitor 1200 in the refresh operation to prevent a positive rush current when signal charges are accumulated.

As a method for reducing the positive rush current, Pd
It is conceivable to lengthen the initialization pulse time of
There is a limit to the time, and if the time is increased, the signal reading time of the entire apparatus is prolonged, which causes a reduction in the speed of the apparatus, that is, a reduction in performance.

Therefore, in this embodiment, the refresh operation is performed by the capacitor and the appropriate timing is set so that, for example, the time from the fall of the pulse of Pc to the fall of the G electrode potential initialization pulse of Pd is reduced. When operated in 100 μs, V _O as shown in FIG.
And the inrush current accumulated as is approximately zero. Therefore P
The charge that starts to be accumulated from the falling edge of the pulse d is
Almost all of the charges are caused by the signal light incident on the photoelectric conversion unit 100, and the signal voltage is read out to obtain SN.
It is possible to obtain information with a high ratio. Further, the potential V _{O (refresh)} of the G electrode when a high level pulse (V _res ) of Pc is applied is calculated. If the sum of the stray capacitance connected to the G electrode and the equivalent capacitance component of the photoelectric conversion element 1100 is C _O , and the capacitance of the capacitor 1200 is C _X , V
_{O (refresh)} is represented by the following equation.

[0197] _{V O (refresh) = {C} X / (C O + C X)} V by the magnitude of × V _res Accordingly fabricated capacitor C _{X
O (refresh)} can be changed freely, and the degree of freedom in actual design increases.

As is apparent from the above description, by applying a positive potential to the G electrode of the photoelectric conversion element via the capacitor 1200, the accumulation of signal charges is performed in a state where the positive rush current is almost zero. It can be carried out.

Here, the second electrode layer is not a transparent electrode. In addition, the injection blocking layer between the i-layer and the second electrode layer of the photoelectric conversion unit 100 is n-type, and carriers whose injection is blocked are holes. Therefore, if the charge of one carrier whose injection is blocked is defined as q, q> 0 in this case.

In the description of this embodiment, holes and electrons may be reversed. For example, the injection blocking layer may be a P layer. In this case, if the direction in which the voltage or the electric field is applied is reversed in the present embodiment and the other parts are configured in the same manner, the same operation result as in the above-described embodiment can be obtained. In such a case, the charge q of one carrier whose injection is blocked by the injection blocking layer is q
<0.

[Thirteenth Embodiment] A thirteenth embodiment of the present invention will be described with reference to FIGS.

FIG. 35 is a schematic equivalent circuit diagram of a photoelectric conversion device for explaining a thirteenth embodiment of the present invention. However, here, a case of a photoelectric conversion element array having nine one-dimensionally arranged photoelectric conversion elements is taken as an example. FIG. 36 shows a photoelectric conversion element portion having a plurality of pixels in a longitudinal direction, a refresh capacitor portion, a transfer TFT portion,
FIG. 3 is a schematic plan view showing one pixel of a set of a reset TFT portion and a wiring portion. FIG. 37 is a cross-sectional view of one pixel. Note that FIG. 37 is schematically drawn for easy understanding, and the position of the wiring portion does not always match FIG. The reset TFT section 1400 is not shown. 35 to 37, the same parts as those in FIG. 33 are denoted by the same reference numerals.

In FIG. 36, the photoelectric conversion unit 100 has a lower electrode layer 2 which also functions as a light shielding film for light from the substrate side. Light emitted from the substrate side is reflected by an original surface (not shown) positioned vertically above the drawing through the lighting window 17, and the reflected light enters the photoelectric conversion unit 100. The photocurrent generated by the carriers generated here is accumulated in the equivalent capacitance component of the photoelectric conversion unit 100 and other stray capacitance.
The accumulated charges are transferred to the signal line matrix wiring section 1500 by the transfer TFT 1300 and read as a voltage by a signal processing section (not shown).

Referring to FIG. 37, the layer structure of each part will be briefly described.

In the figure, 100 is a photoelectric conversion unit, 1200 is a refresh capacitor, 1300 is a transfer TFT, 15
Reference numeral 00 denotes a wiring portion, and these are the first electrode layers 2-1 and 2-1.
−2, 2-3, 2-4, insulating layer 70, i-layer 4, n-layer 5,
It has a configuration of a total of five common layers including the second electrode layers 6-1, 6-2, 6-3, and 6-4. Here, the second electrode layer is not particularly a transparent electrode.

Also in this embodiment, the photoelectric conversion unit 10
0 has the same structure as in the first embodiment, so that the injection blocking layer between the i-layer 4 and the second electrode layer 6-1 is n-type,
The carriers whose injection is blocked are holes. Therefore, if the charge of one carrier whose injection is blocked is q, q> 0 also in this case.

Next, a method for driving the photoelectric conversion device of this embodiment will be described with reference to FIG.

In FIG. 35, photoelectric conversion elements S1 to S9
, Three blocks constitute one block, and three blocks constitute a photoelectric conversion element array. Refresh capacitors C1 connected to the photoelectric conversion elements S1 to S9, respectively.
To C9, the TFT-R1 to R9 for initializing the G electrode potential of the photoelectric conversion elements S1 to S9, and the signal charge transfer TFT-T
The same applies to 1 to T9.

In each of the blocks of the photoelectric conversion elements S1 to S9, the individual electrodes having the same order are each provided with a transfer TFT-T.
It is connected to one of the common lines 1102 to 1104 via 1 to T9. More specifically, the first transfer TFT-T1, T4, T7 of each block is on the common line 1102, the second transfer TFT-T2, T5, T8 of each block is on the common line 1103, and Third transfer TF of
T-T3, T6, and T9 are connected to the common line 1104, respectively. The common lines 1102 to 1104 are connected to the amplifier 112 via the switching transistors T100 to T120, respectively.
6 is connected.

In FIG. 35, common lines 1102-1
104 are grounded via common capacitors C100 to C120, respectively, and the switching transistor CT
1 to CT3. Here, the gate electrodes of the switching transistors CT1 to CT3 are commonly connected, and turned on at the same timing as the pulse of Pa shown in FIG.
The residual charge of 1104 is discharged to GND, and the potential is initialized.

In this embodiment, the refreshing means includes capacitors C1 to C9, a shift register 1108, and a power supply 1114, and the signal detecting section includes a detecting means within a dotted line in FIG. 35, TFT-T1 to T9, and a shift register. 1106.

Next, the operation of this embodiment will be described in chronological order.

First, when signal light is incident on the photoelectric conversion elements S1 to S9, charges are supplied from the power supply 114 to the refresh capacitors C1 to C9 and the equivalent capacitance components of the photoelectric conversion units 100 and the respective floating capacitances according to the intensity of the signal light. Stored. Then, a high level is output from the first parallel terminal of the shift register 1106, and the transfer TFTs-T1 to T3 are turned on, so that the transfer TFTs-T1 to T3 are accumulated in the refresh capacitors C1 to C3, the respective capacitance components, and the respective floating capacitances. Charge
Each is transferred to the common capacitors C100 to C120.
Subsequently, the high level output from the shift register 1107 shifts, and the switching transistors T100 to
T120 is sequentially turned on. Thereby, the optical signals of the first block transferred to the common capacitors C100 to C120 are sequentially read out through the amplifier 1126.

After the transfer TFTs T1 to T3 are turned off, a high level is output from the first parallel terminal of the shift register 1108, and the refresh capacitor C1 is output.
The potential at both ends of C3 increases. And the photoelectric conversion element S
Holes in 1 to S3 are swept out to the common power supply line 1403.

Next, a high level is output from the first parallel terminal of the shift register 1109, and the reset TFT-R1 is output.
ＲR3 are turned on, the photoelectric conversion elements S1Ｓ
The potential of the G electrode in S2 is initialized to GND. Then, the common capacitors C100 to C12 are supplied by the pulse of Pa.
The potential of 0 is initialized. Common capacitors C100 to C
When the potential of 120 is completely initialized, the shift register 1106 shifts, and a high level is output from the second parallel terminal. Thereby, the transfer TFT-T4 to T6
Is turned on, and the signal charges accumulated in the refresh capacitors C4 to C6 of the second block and the stray capacitance and the equivalent capacitance of the sensor are transferred to the common capacitors C100 to C100.
Transferred to C120. Then, as in the case of the first block, the shifting of the shift register 1107 turns on the switching transistors T100 to T120 sequentially, and the optical signals of the second block stored in the common capacitors C100 to C120 are sequentially read.

Similarly, in the case of the third block, a charge transfer operation and an optical signal read operation are performed.

As described above, by a series of operations from the first block to the third block, one operation in the main scanning direction of the original is performed.
The reading of the signal for the line is completed, and the read signal is output in an analog manner according to the magnitude of the reflectance of the document.

As described with reference to FIG. 37 in the present embodiment, the photoelectric conversion element, the refresh capacitor, the transfer TFT, the reset TFT, and the matrix signal wiring portion are composed of the first electrode layer, the insulating layer, the i-layer, Although a common layer configuration of all five layers including an n-layer and a second electrode layer is provided, it is not necessary that all element portions have the same layer configuration, and at least the photoelectric conversion element has this configuration (MIS Structure)
It is sufficient for the other element portions to have a layer configuration having a function as each element. However, the same layer configuration is convenient for improving the yield and reducing the cost.

In the above description of the present embodiment, holes and electrons may be reversed. For example, the injection blocking layer may be a P layer. In this case, the same operation result as in the first embodiment can be obtained by reversing the direction in which the voltage or the electric field is applied in the above-described embodiment and configuring the other parts in the same manner. In such a case, the charge q of one carrier whose injection is blocked by the injection blocking layer is q <0.

Further, in this embodiment, a one-dimensional line sensor has been described.
It goes without saying that a photoelectric conversion device that becomes a dimensional area sensor and performs an equal-magnification reading, such as an X-ray imaging device, can be configured by using the block division driving described in the above embodiment.

As described above, in this embodiment, since the photoelectric conversion element, TFT, and matrix signal wiring portion have the same film configuration,
Since they can be formed simultaneously in the same process, miniaturization and high yield can be achieved, and a photoelectric conversion device with low cost and high SN ratio can be realized.

As is clear from the above description, the photoelectric conversion element of this embodiment is not limited to the one shown in the embodiment. That is, there are a first electrode layer, an insulating layer for preventing movement of holes and electrons, a photoelectric conversion semiconductor layer, and a second electrode layer, and between the second electrode layer and the photoelectric conversion semiconductor layer, What is necessary is just to have an injection blocking layer that blocks injection of holes. Further, the photoelectric conversion semiconductor layer may have a photoelectric conversion function of generating a pair of electrons and holes upon incidence of light. The layer configuration may be not a single layer but a multilayer, and the characteristics may be continuously changed.

Similarly, a TFT only needs to have a gate electrode, a gate insulating film, a semiconductor layer capable of forming a channel, an ohmic contact layer, and a main electrode. For example, the ohmic contact layer may be a p-layer. In this case, the holes may be used as carriers by reversing the control voltage of the gate electrode.

Similarly, a capacitor only needs to have a lower electrode layer, an intermediate layer including an insulating layer, and an upper electrode layer. For example, the capacitor can also be used as an electrode portion of each element without special separation from a photoelectric conversion element or a TFT. The configuration may be as follows.

Further, the insulating substrate does not need to be entirely an insulator, and may be a conductor or a semiconductor on which an insulator is deposited.

Further, since the photoelectric conversion element itself has a function of storing electric charge, an integrated value of optical information can be obtained for a certain period without a special capacitor.

[Embodiment 14] FIG. 3 described in Embodiment 13
The photoelectric conversion device of the schematic equivalent diagram shown in FIG. 3 can be driven at the timing shown in the timing chart shown in FIG.

The operation of the photoelectric conversion device according to this embodiment will be described below with reference to FIG.

In the refresh operation of the photoelectric conversion element, a refresh high-level pulse Pc is applied to the electrode of the capacitor 1200 opposite to the G electrode as shown in FIG. The configuration is such that the potential of the electrode rises.
Therefore, the holes remaining in the photoelectric conversion unit 100 are swept out to the D electrode, and the photoelectric conversion unit 100 is refreshed.

Then, at the same time when the refresh pulse of Pc falls, the counter electrode G of the capacitor 1200 is turned off.
Since the potential of the electrode also instantaneously drops, the sweeping out of the holes remaining in the photoelectric conversion unit 100 to the D electrode ends, and the photoelectric conversion operation starts. Actually, the photoelectric conversion unit 100 includes FIG.
Since the positive inrush current as shown in FIG. 8 is gradually attenuated, the photoelectric conversion operation starts after the inrush current flows.

Next, the TFT 1400 is turned off by a low potential (hereinafter also referred to as low level) pulse of Pd, and the G electrode is opened DC. However, actually, the potential is maintained by the capacitance of the capacitor 1200 and the equivalent capacitance component and the stray capacitance of the photoelectric conversion unit 100. Here, when an optical signal of the photoelectric conversion unit 100 is incident, a corresponding current flows from the G electrode and the potential of the G electrode rises.

That is, light incident information is accumulated as charges in the capacitance of the G electrode. TFT for transfer after a certain storage time
1300 is turned on from the off state by the high level pulse of Pb, and the accumulated electric charge is stored in the capacitor 1124.
However, this charge is transferred to the photoelectric conversion unit 10 by the photoelectric conversion operation.
It is a value proportional to the integral value of the current flowing from 0, that is, detected by the detection unit through the operational amplifier 1126 as the total amount of incident light. Before this transfer operation, it is desirable that the potential of the capacitor 1124 is initialized to the GND potential by the high-level pulse of Pa of the TFT 1125.

When the transfer TFT 1300 is turned off, the refresh TFT 1700 is turned on again by the high-level pulse of Pc, and a series of operations is repeated thereafter. In the present embodiment, the refreshing means includes a capacitor 1200, a means for applying a high-level pulse Pc, and a power supply 114, and the signal detecting unit is the one shown in FIG.
3 may include a detection unit within a dotted line, a TFT 1300, and a unit for applying a high-level pulse Pb.

In this embodiment, in the refresh operation, a positive potential is applied to the G electrode of the photoelectric conversion element via the capacitor 1200, and the positive potential is set to a potential lower than a predetermined potential, so that the I _S shown in FIG. 5 prevents a positive inrush current at the time of accumulating signal charges as indicated by a solid line. (Note that when the potential is higher than a predetermined potential, the broken line looks like a broken line.) As a method of reducing the positive rush current, it is conceivable to lengthen the time of the Pd initialization pulse. Increasing the time lengthens the signal reading time of the entire apparatus, which causes a reduction in the speed of the apparatus, that is, a reduction in performance.

Therefore, in the present invention, the refresh operation is performed.
Operation with a capacitor and appropriate timing settings.
Thus, for example, from the falling edge of the Pc pulse,
It takes about 1 to the fall of the Pd G electrode potential initialization pulse.
When the operation is performed in 00 μsec, as shown in FIG._Oage
The inrush current that is accumulated is almost zero. Therefore Pd
The charge that starts to accumulate from the falling edge of the pulse is almost
All of them are caused by the signal light that has entered the photoelectric conversion unit 100.
And read the signal voltage to obtain the S / N ratio.
It is possible to obtain high information. In addition, Pc
Bell pulse (V _res ) Is applied, the potential V of the G electrode
_{O (refresh)}Is calculated. Floating volume connected to G electrode
And the sum of the equivalent capacitance component of the photoelectric conversion unit 100
C_O, The capacitance of the capacitor 1200 is C_XThen V
_{O (refresh)}Is represented by the following equation.

[0236] _{V O (refresh) = {C} X / (C O + C X)} V by the magnitude of × V _res Accordingly fabricated capacitor C _{X
O (refresh)} can be changed freely, and the degree of freedom in actual design increases.

As is apparent from the above description, by applying a positive potential to the G electrode of the photoelectric conversion element via the capacitor 1200, the accumulation of signal charges is performed in a state where the positive rush current is almost zero. However, by adjusting the potential applied to the G electrode of the photoelectric conversion element via the capacitor 1200, the value of the positive rush current can be reduced, and the decay time can be shortened.

The potentials of the D electrode and the G electrode of the photoelectric conversion element in the refresh operation have been described in detail in Embodiment 9 with reference to FIGS. 24 to 27, and will not be described here.

In this embodiment, excellent characteristics are obtained by driving under the following conditions.

In the refresh operation of the photoelectric conversion unit 100, the potential V _{rG of the} power supply 1115 for giving the positive potential of the G electrode.
There is to lower than the potential V _D of the power supply 114 to provide a positive potential to the D electrode. More specifically, the photoelectric conversion unit 1
Since 00 has a flat band voltage (V _FB ) applied to the G electrode in order to flatten the energy band of the i-layer, it is actually driven in a state of V _rG <V _D −V _FB. .

The specific operation has been described in detail with reference to FIGS. 29 and 30 in the tenth embodiment, and a description thereof will be omitted.

In this embodiment, the i-layer 4 and the insulating layer 70
Since almost no electrons are present at the interface defect, a long time is not spent for the ingress and egress of electrons, and as a result, the rush current which is a noise component can be greatly reduced.

The capacitance of the capacitor 1200 is C _X , the sum of the stray capacitance connected to the G electrode and the equivalent capacitance component of the photoelectric conversion unit 100 is C _O , and the high-level pulse V of Pc.
_res to the G electrode potential during refresh V _rG is _{V rG = V O (refresh)} = {C X / (C O + C X)} × V
_The above effect can be obtained by driving under the condition that the value of {C _X / (C _O + C _X )} × V _res is smaller than V _D −V _FB , and Vs shown in FIG. 38 can be obtained. _rG = V _{O (re fresh)}
The accumulated inrush current can be further reduced as compared with V _O obtained under the condition of ≧ (V _D −V _FB ).

Here, the second electrode layer is not a transparent electrode. In addition, the injection blocking layer between the i-layer and the second electrode layer of the photoelectric conversion unit 100 is n-type, and carriers whose injection is blocked are holes. Therefore, if the charge of one carrier whose injection is blocked is defined as q, q> 0 in this case.

In the description of this embodiment, holes and electrons may be reversed. For example, the injection blocking layer may be a P layer. In this case, if the direction in which the voltage or the electric field is applied is reversed in the present embodiment, and the other portions are configured in the same manner, the same operation result as in the above embodiment can be obtained. In such a case, the charge q of one carrier whose injection is blocked by the injection blocking layer is q
<0.

[Embodiment 15] An example in which another drive is performed using the photoelectric conversion device described in Embodiment 13 will be described.

The operation of this embodiment will be described in time series.

First, when signal light is incident on the photoelectric conversion elements S1 to S9, charges are supplied from the power supply 114 to the refresh capacitors C1 to C9 and the equivalent capacitance components of the photoelectric conversion units 100 and the respective floating capacitances according to the intensity of the signal light. Stored. Then, a high level is output from the first parallel terminal of the shift register 1106, and the transfer TFTs-T1 to T3 are turned on, so that the transfer TFTs-T1 to T3 are accumulated in the refresh capacitors C1 to C3, the respective capacitance components, and the respective floating capacitances. Charge
Each is transferred to the common capacitors C100 to C120.
Subsequently, the high level output from the shift register 1107 shifts, and the switching transistors T100 to
T120 is sequentially turned on. Thereby, the optical signals of the first block transferred to the common capacitors C100 to C120 are sequentially read out through the amplifier 1126.

After the transfer TFTs-T1 to T3 are turned off, a high level is output from the first parallel terminal of the shift register 1108 and the refresh capacitor C1 is output.
The potential at both ends of C3 increases. At this time, the conditions described in the first embodiment are used for the potentials of the D electrode and the G electrode of the photoelectric conversion elements S1 to S3. That is, _assuming that the D electrode potential during the refresh operation is V _{D1 to} V _D3 , the G electrode potential is V _{rG1 to} V _rG3 , and the flat band voltage of each photoelectric conversion element is V _{FB1 to} V _FB3 , V _rG1 <V _D1 − V _FB1 , V _rG2 <V _D2 −V _FB2 , V _rG3
<V _D3 −V _FB3 . Then, holes in the photoelectric conversion elements S1 to S3 are swept out to the common power supply line 1403.

Next, a high level is output from the first parallel terminal of the shift register 1109, and the reset TFT-R1 is output.
To R3 are turned on, the photoelectric conversion elements S1 to S3 are turned on.
The potential of the G electrode in S2 is initialized to GND. Then, the common capacitors C100 to C12 are supplied by the pulse of Pa.
The potential of 0 is initialized. Common capacitors C100 to C
When the potential of 120 is completely initialized, the shift register 1106 shifts, and a high level is output from the second parallel terminal. Thereby, the transfer TFT-T4 to T6
Is turned on, and the signal charges accumulated in the refresh capacitors C4 to C6 of the second block and the stray capacitance and the equivalent capacitance of the sensor are transferred to the common capacitors C100 to C100.
Transferred to C120. As in the case of the first block, the switching transistors 1100 to T120 are sequentially turned on by the shift of the shift register 1107, and the optical signals of the second block stored in the common capacitors C100 to C120 are sequentially read. The conditions of the potentials of both electrodes of the photoelectric conversion elements S4 to S6 during the refresh operation are the same as those of the photoelectric conversion elements S1 to S3.

Similarly, in the case of the third block, a charge transfer operation and an optical signal read operation are performed.

As described above, a series of operations from the first block to the third block perform one operation in the main scanning direction of the original.
The reading of the signal for the line is completed, and the read signal is output in an analog manner according to the magnitude of the reflectance of the document.

As described with reference to FIG. 37 in this embodiment, the photoelectric conversion element, the refresh capacitor, the transfer TFT, the reset TFT, and the matrix signal wiring portion are
It has a common layer structure of all five layers including a first electrode layer, an insulating layer, an i-layer, an n-layer, and a second electrode layer, but it is necessary that all element portions have the same layer structure. However, it is sufficient that at least the photoelectric conversion element has this structure (MIS structure) and the other element portions have a layered structure having a function as each element. However, having the same layer configuration is convenient for improving the yield and reducing the cost.

In the description of the present embodiment, holes and electrons may be reversed. For example, the injection blocking layer may be a P layer. In this case, the same operation result as in the first embodiment can be obtained by reversing the direction in which the voltage or the electric field is applied in the above-described embodiment and configuring the other parts in the same manner. In such a case, the charge q of one carrier whose injection is blocked by the injection blocking layer is q <0.

Further, in this embodiment, a one-dimensional line sensor has been described.
It goes without saying that a photoelectric conversion device that becomes a dimensional area sensor and performs an equal-magnification reading, such as an X-ray imaging device, can be configured by using the block division driving described in the above embodiment.

As described above, in this embodiment, since the photoelectric conversion element, the TFT, and the matrix signal wiring portion have the same film configuration,
Since they can be formed simultaneously in the same process, miniaturization and high yield can be achieved, and a photoelectric conversion device with low cost and high SN ratio can be realized.

As is clear from the above description, the photoelectric conversion element of the present invention is not limited to the one shown in this embodiment. That is, there are a first electrode layer, an insulating layer for preventing movement of holes and electrons, a photoelectric conversion semiconductor layer, and a second electrode layer, and between the second electrode layer and the photoelectric conversion semiconductor layer, What is necessary is just to have an injection blocking layer that blocks injection of holes. Further, the photoelectric conversion semiconductor layer may have a photoelectric conversion function of generating a pair of electrons and holes upon incidence of light. The layer configuration may be not a single layer but a multilayer, and the characteristics may be continuously changed.

Similarly, a TFT only needs to have a gate electrode, a gate insulating film, a semiconductor layer capable of forming a channel, an ohmic contact layer, and a main electrode. For example, the ohmic contact layer may be a p-layer. In this case, the holes may be used as carriers by reversing the control voltage of the gate electrode.

Similarly, a capacitor only needs to have a lower electrode layer, an intermediate layer including an insulating layer, and an upper electrode layer. For example, the capacitor can also be used as an electrode portion of each element without special separation from a photoelectric conversion element or a TFT. The configuration may be as follows.

Further, the insulating substrate does not need to be entirely an insulator, and may be a conductor or a semiconductor on which an insulator is deposited.

Further, since the photoelectric conversion element itself has a function of storing electric charges, an integrated value of optical information can be obtained for a certain period without a special capacitor.

[Embodiment 16] FIG. 39 is a schematic equivalent circuit diagram of a photoelectric conversion apparatus according to Embodiment 16. Here, a case of a photoelectric conversion element array having nine one-dimensionally arranged photoelectric conversion elements will be described as an example. FIG.
0 is a timing chart showing the operation of the equivalent circuit of FIG.

As the structure of the photoelectric conversion unit, the structure shown in FIGS. 36 and 37 of Embodiment 13 can be applied.

Next, a method for driving the photoelectric conversion device of this embodiment will be described with reference to FIGS. In FIG. 39, the photoelectric conversion elements S1 to S9 and the photoelectric conversion elements S1 to S9
Refresh capacitor C1 connected to S9
To C9, the G-electrode potentials of the photoelectric conversion elements S1 to S9 are initialized (hereinafter, also referred to as G-electrode resetting).
R9 and signal charge transfer TFTs T1 to T9
Each array is composed of three blocks.

The individual electrodes having the same order in each of the blocks of the photoelectric conversion elements S1 to S9 are each provided with a transfer TFT-T.
It is connected to one of the common lines 1102 to 1104 via 1 to T9. More specifically, the first transfer TFT-T1, T4, T7 of each block is on the common line 1102, the second transfer TFT-T2, T5, T8 of each block is on the common line 1103, and Third transfer TF of
T-T3, T6, and T9 are connected to the common line 1104, respectively. The common lines 1102 to 1104 are connected to the amplifier 112 via the switching transistors T100 to T120, respectively.
6 is connected.

In FIG. 39, common lines 1102 to 11
04 are grounded via common capacitors C100 to C120, respectively, and are connected to a switching transistor CT1.
To CT3.

Here, the switching transistor CT1
To CT3 are commonly connected to a terminal 1116, the terminal 1116 is set to a high level, and the switching transistors CT1 to CT3 are turned on.
The residual charges of the common lines 1102 to 1104 are discharged to GND to initialize the charges. In FIG. 39, the counter electrodes of the G electrodes of the refresh capacitors C1 to C3 in the first block are connected in common, and the transfer T
Connected to the common gate electrode of FT-T4 to FT-T6,
Further, the refresh capacitors C4 to C in the second block are provided.
6 are connected in common to the common electrodes of the third block transfer TFTs T7 to T9 and the common gate electrodes of the first block G electrode reset TFTs R1 to R3. ing. Similarly, the opposite electrodes of the G electrodes of the refresh capacitors C7 to C9 in the third block are commonly connected, and are connected to the common gate electrodes of the G electrode reset TFTs-R4 to R6 in the second block. In this embodiment, the refreshing means includes the capacitors C1 to C9, the shift register 1106, and the power supply 1
114, the signal detection unit is a detection means in the dotted line of FIG. 39,
TFT-T1 to T9 and a shift register 1106 may be included.

Next, the operation of this embodiment will be described in chronological order.

First, when signal light enters the photoelectric conversion elements S1 to S9, electric charges are accumulated in the refresh capacitors C1 to C9 and the floating capacitors according to the intensity. A high level is output from the first parallel terminal of the shift register 1106 [FIG. 40A], and the transfer TFT-T1 is output.
To T3 are turned on, the electric charges accumulated in the refresh capacitors C1 to C3 and the stray capacitance become:
Each is transferred to the common capacitors C100 to C120.
After the transfer TFTs-T1 to T3 are turned on, the high level output from the shift register 1107 subsequently shifts to the switching transistors T100 to T1.
20 are sequentially turned on [FIGS. 40 (j) to 40].
(L)]. Thereby, the common capacitors C100 to C100
The optical signal of the first block transferred to the
26 and are sequentially read. And then the terminal 111
6 becomes high level (FIG. 40 (m)), and when the switching transistors CT1 to CT3 are turned on, the potentials of the common capacitors C100 to C120 are initialized. When the potentials of the common capacitors C100 to C120 are completely initialized, a high level is output from the second parallel terminal of the shift register 1106 [FIG. 40 (d)], and the potentials at both ends of the refresh capacitors C1 to C3. Rises. Then, holes in the photoelectric conversion elements S1 to S3 are swept out to the common power supply line 1403. At the same time, the transfer TFTs-T4 to T6 in the second block are turned on [FIG.
0 (b)], the signal charges stored in the refresh capacitors C4 to C6 and the floating capacitors in the second block are transferred to the common capacitors C100 to C120. Then, simultaneously with the case of the first block, the shift of the shift register 1107 causes the switching transistors T100 to T100 to shift.
40 (j) to FIG. 40 (l), the optical signals of the second block stored in the common capacitors C100 to C120 are sequentially read out, and then the potentials of the common capacitors C100 to C120 Are initialized by the switching transistors CT1 to CT3 [FIG. 40 (m)].

Next, after the common electrode potentials of the refresh capacitors C1 to C3 of the first block go low, a high level is output from the third parallel terminal of the shift register 1106 [FIG. 40 (g)]. Electrode reset TF
By turning on T-R1 to R3, the potentials of the G electrodes of the photoelectric conversion elements S1 to S3 are initialized to GND. At the same time, the refresh capacitor C of the second block is used.
The potentials at both ends of 4-C6 rise [FIG. 40 (e)].
Further, the transfer TFTs T7 to T9 in the third block are simultaneously turned on [FIG. 40 (c)], and the signal charges accumulated in the refresh capacitors C7 to C9 and the floating capacitance in the third block are shared by the common capacitor. C100-C120
Transferred to Similarly to the case of the first block and the second block, the shift of the shift register 1107 causes the switching transistors T100 to T120 to be sequentially turned on [FIGS. 40 (j) to 40 (l)], and the common capacitors C100 to C120. 3rd accumulated in
The optical signals of the blocks are sequentially read. Thereafter, the potentials of the common capacitors C100 to C120 are initialized by the switching transistors CT1 to CT3 [FIG.
(M)].

Similarly, the fourth register of shift register 1106
The high level is output from the parallel terminal of
The G-electrode reset TFTs-R4 to R6 of the block are turned on (FIG. 40 (h)). At the same time, the potentials at both ends of the refresh capacitors C7 to C9 in the third block are raised [FIG. 40 (f)]. After that, a high level is output from the fifth parallel terminal of the shift register 1106, so that the G-electrode reset TFT-
R7 to R9 are turned on [FIG. 40 (i)].

As described above, by a series of operations from the first block to the third block in a certain line, the reading of one line of the signal in the main scanning direction of the document is completed, and the read signal is converted to the signal of the document. It is output in an analog manner depending on the magnitude of the reflectance.

Although the operation of the photoelectric conversion device in which the nine photoelectric conversion elements are divided into three blocks to form a sensor array for one line has been described, the charge transfer operation is similarly performed when reading other lines. The reading operation of the optical signal is performed continuously.

In this embodiment, as described with reference to FIG. 37, the photoelectric conversion element, the refresh capacitor, and the T
The FT and the matrix wiring section have a configuration of a common layer of five layers including a first electrode layer, an insulating layer, a semiconductor layer, an n layer, and a second electrode layer, but all element sections are not necessarily the same. It is not necessary that the photoelectric conversion element has at least this structure (MIS structure) and the other element portions have a layer structure having a function as each element. However, using a common configuration can improve the yield and thereby further reduce the cost.

In the above description, holes and electrons may be reversed. For example, the injection blocking layer may be a P layer.
In this case, in the above-described embodiment, the operation result similar to that of the above-described embodiment can be obtained by reversing the direction in which the voltage or the electric field is applied and by configuring the other parts in the same manner.

Although the one-dimensional line sensor has been described in the present embodiment, a two-dimensional area sensor can be obtained by arranging a plurality of line sensors. Needless to say, the conversion device can be configured by using the block division driving shown in the above embodiment.

As described above, in this embodiment, since the photoelectric conversion element, the capacitor, the TFT, and the matrix wiring portion have the same film configuration, they can be formed simultaneously by the same process.
The miniaturization and high yield can be achieved, and a low-cost and high SN ratio photoelectric conversion device can be realized. Further, there is an effect that one refresh power supply conventionally used can be reduced, and a low-cost photoelectric conversion device having a high SN ratio can be manufactured. Further, a plurality of photoelectric conversion elements are divided into blocks, and two or more operations (for example, a signal transfer operation, a sensor refresh operation, and a potential reset operation) in another block can be simultaneously driven by the same drive line. , Can operate at high speed,
Further, since the device can be miniaturized, a photoelectric conversion device with higher yield and lower cost can be realized.

[Embodiment 17] FIG. 41 is a schematic equivalent circuit diagram of one bit of a photoelectric conversion device for explaining a seventeenth embodiment of the present invention.

In FIG. 41, reference numeral 100 denotes a photoelectric conversion unit. The layer configuration of the photoelectric conversion unit is the same as that described in FIG. 4A. Therefore, D indicates an electrode on the transparent electrode 6 side, and G indicates an electrode on the lower electrode 2 side. Reference numeral 1114 denotes a power supply for applying a positive potential (V _D ) to the D electrode, 1115 denotes a power supply for applying a positive potential (V _rG ) to the G electrode in the refresh operation of the photoelectric conversion element 1100, and 1700 denotes a refresh TFT. It is. At this time, the power supply 1115 is desirably set to a lower voltage than the power supply 1114. Reference numeral 1800 denotes a signal charge storage capacitor.
It has the same laminated structure as the photoelectric conversion unit 100. The G electrode of the storage capacitor is grounded to GND, and the D electrode is connected to the G electrode of the photoelectric conversion unit 100. Further, reference numeral 1300 denotes a TFT for transferring a signal charge in the detection operation.
00 is a G electrode initialization TFT for initializing the potential of the G electrode.
(Hereinafter also referred to as a G electrode reset TFT). or,
The inside of the square dotted line represents the detecting means, which is generally constituted by an IC or the like, and FIG. 41 shows one example. Here, 1124 is a read capacitor, 1
Reference numeral 125 denotes a switch element for initializing a read capacitor, and reference numeral 1126 denotes an operational amplifier. The detection means is not limited to this example, but may be any as long as it can detect current or charge directly or by an integrated value. For example, in the case where the signal charge is not stored in the read capacitor 1124 and read by an ammeter or the like, the read capacitor 1124 and the potential initialization switch element 1125 can be omitted.

Hereinafter, the operation of the photoelectric conversion device will be described with reference to FIG.

In the refresh operation of the photoelectric conversion element
Thus, the TFT 1700 has a high potential of Pc (hereinafter referred to as a high level).
The pulse changes from the off state to the on state,
A positive potential is applied to the G electrode by the power supply 1115.
You. A positive potential is applied to the D electrode by the power supply 114.
And the potential V of the D electrode with respect to the G electrode_DGHas a positive potential
It will be given. Then, the photo in the photoelectric conversion unit 100
A part of the rule is swept to the D electrode and refreshed.
Next, the TFT 1400 is driven by a high level pulse of Pd.
From the off state to the on state, the G electrode is supplied with the GND potential.
Can be At this time, V _DGBecomes a larger positive potential, and light
The photoelectric conversion unit 100 performs a photoelectric conversion operation after the inrush current flows.
Start. Next, the TFT 1400 is driven to a low potential of Pd (hereinafter referred to as a low potential).
-It is turned off by pulse)
The poles are grounded via the charge storage capacitor 1800
Be in a state. Here, when an optical signal is incident on the photoelectric conversion unit 100,
The corresponding current flows out of the G electrode and the potential of the G electrode
Rises. In other words, light incident information is stored in the capacitance of the G electrode.
It is stored as electric charge. TFT for transfer after a certain storage time
1300 is turned off by a high-level pulse of Pb
The capacitor is turned on, and the accumulated charge is
However, this charge is transferred to the photoelectric conversion unit 10 by the photoelectric conversion operation.
It is a value proportional to the integral of the current flowing out of zero.
The total amount of incident light is detected through the operational amplifier 1126.
It is detected by the output means. Before this transfer operation,
Indicates that the potential of the capacitor 1124 is
Initialized to the GND potential by the high level pulse of a
It is desirable to have. Then, the transfer TFT 1300 is turned off.
In this state, the refreshing TFT 1700 again becomes P
It is turned on by the high level pulse of c.
Is repeated.

As a result, the SN ratio is high, and photoelectric conversion can be performed with excellent characteristics.

[Embodiment 18] FIG. 42 shows an eighteenth embodiment of the present invention.
FIG. 3 is a schematic equivalent circuit diagram of one bit of the photoelectric conversion device according to the example of FIG. FIG. 43 is a timing chart when the photoelectric conversion device of FIG. 42 is actually driven.

Here, FIG. 42 corresponds to the configuration shown in FIG. 41 described above, and the same reference numerals are given to the corresponding parts for the same parts. The description of the same parts as those in FIG. 41 is simplified or omitted.

In this embodiment, the refresh means may include the TFT 1700, a means for applying the high-level pulse Pc, a power supply 1115, and a power supply 1114.

Further, the signal detecting section may include a detecting means indicated by a dotted line in FIG. 42, a TFT 1300, a means for applying a high-level pulse Pb, and a storage capacitor 1800.

The difference between FIG. 42 and FIG. 41 is that the storage capacitor 18 connected to the G electrode of the photoelectric conversion unit 100
The terminal of 00 is not the D electrode but the G electrode.

Next, the operation will be described with reference to FIG. FIG.
In 3, the current I _S of the photoelectric conversion unit 100 and the behavior of the potential V _O of the G electrode due to the current I _S are noted.

In FIG. 43, when a refresh pulse of Pc rises and a voltage is applied to the G electrode of the photoelectric conversion unit 100, a part of the holes remaining in the i-layer of the photoelectric conversion unit 100 is swept out to the D electrode. It is.

Next, when the Pd G electrode reset pulse rises and the G electrode of the photoelectric conversion unit 100 is grounded to GND, all the electrons remaining in the i layer flow out to the D electrode. Then, the Pd G electrode reset pulse falls. The signal charge starts to be accumulated from the fall of the pulse of Pd. At this time, the charge storage electrode of the storage capacitor 1800 is a G electrode, and the ground electrode is a D electrode. Is a substantially flat state, that is, a so-called flat band state.
Generally, the voltage applied to the insulating layer side for bringing the MIS capacitor into the flat band state, that is, the so-called flat band voltage is zero or slightly positive voltage. Therefore, when the flat band voltage is zero, as described above, the capacitor 18
00 does not enter the depletion state from the start of charge storage to the end of charge storage. When the flat band voltage is a slightly positive voltage, a power supply having a voltage equal to or higher than the positive flat band is inserted between the G electrode reset TFT 1400 and GND in FIG. Can be used in the accumulation state instead of the depletion state from the start of charge storage to the end of charge storage. That is, no leak current flows through the storage capacitor 1800 in the photoelectric conversion device described with reference to FIG. Therefore, almost all charges accumulated in the storage capacitor and other floating capacitors are charges due to the signal light incident on the photoelectric conversion unit 100, and by reading out the signal voltage, information with a high SN ratio can be obtained. Become. Here, the elements for signal detection within the square dotted line shown in FIG. 42 are not particularly limited, as long as currents or charges can be detected directly or by an integrated value.
In the case where reading is performed by an ammeter or the like without being stored in the memory 124, the reading capacitor 1124 and the switch element 1125 for resetting the potential can be omitted, but this is the same as described in the description of the photoelectric conversion device in FIG. It is.

As described above, in this embodiment, the signal charges are stored in the G electrode on the insulating layer 70 side of the signal storage capacitor, and the signal storage capacitor can always be used in the accumulation state. Since there is almost no leak current caused by signal charges leaking through the storage capacitor, it is possible to provide a photoelectric conversion device with a higher SN ratio as a result.

[Embodiment 19] A nineteenth embodiment of the present invention will be described with reference to FIGS.

FIG. 44 is a schematic equivalent circuit diagram of the photoelectric conversion device of this embodiment. However, here, a case of a photoelectric conversion element array having nine one-dimensionally arranged photoelectric conversion elements is taken as an example. FIG. 45 shows a photoelectric conversion element section having a plurality of pixels in a longitudinal direction, a storage capacitor section, a refresh TFT section, a transfer TFT section, and a reset TF.
FIG. 4 is a plan view illustrating one pixel of a set of a T portion and a wiring portion. FIG. 46 is a cross-sectional view of one pixel. Note that FIG. 46 is schematically illustrated for easy understanding, and the position of the wiring portion does not always match FIG. In FIG. 46, the reset TFT portion 1400 is not shown. 44 to 46, the same parts as those in FIG. 42 are denoted by the same reference numerals.

In FIG. 45, the photoelectric conversion unit 100 has a lower electrode 2 which also serves as a light shielding film for light from the substrate side. Light emitted from the substrate side is reflected by an original surface (not shown) positioned vertically above the drawing through the lighting window 17, and the reflected light enters the photoelectric conversion unit 100. The photocurrent generated by the carriers generated here is stored in the storage capacitor 18.
00 and the equivalent capacitance component of the photoelectric conversion unit 100 and other stray capacitance. The accumulated charge is the transfer T
FT1300 to matrix wiring section 1500 for signal lines
And read as a voltage by a signal processing unit (not shown).

Referring to FIG. 46, the layer structure of each part will be briefly described.

In the figure, 100 is a photoelectric conversion unit, 1800 is a storage capacitor, 1700 is a refresh TFT, 130
0 denotes a transfer TFT, 1500 denotes a wiring portion, and these are the first electrode layers 2-1, 2-2, 2-3, the insulating layers 70, i
Layer 4, n-layer 5, second electrode layers 6-1, 6-2, 6-3
The common layer is composed of a total of five layers 6-4 and 6-5. Here, the second electrode layer is not particularly a transparent electrode.

Next, a method for driving the photoelectric conversion device according to the nineteenth embodiment will be described with reference to a circuit diagram.

Referring to FIG. 44, photoelectric conversion elements S1 to S9
, Three blocks constitute one block, and three blocks constitute a photoelectric conversion element array. The storage capacitors D1 to D9 respectively connected to the photoelectric conversion elements S1 to S9, the refreshing TFTs F1 to F9, and the photoelectric conversion elements S1 to S9.
The same applies to the TFTs-R1 to R9 for initializing the G electrode potential in S9 and the signal charge transfer TFTs-T1 to T9.

The individual electrodes having the same order in each block of the photoelectric conversion elements S1 to S9 are respectively provided with the transfer TFT-T.
It is connected to one of the common lines 1102 to 1104 via 1 to T9. More specifically, the first transfer TFT-T1, T4, T7 of each block is on the common line 1102, the second transfer TFT-T2, T5, T8 of each block is on the common line 1103, and Third transfer TF of
T-T3, T6, and T9 are connected to the common line 1104, respectively. The common lines 1102 to 1104 are connected to the amplifier 112 via the switching transistors T100 to T120, respectively.
6 is connected.

In FIG. 44, common lines 1102-1
104 are grounded via common capacitors C100 to C120, respectively, and the switching transistor CT
1 to CT3. Here, the gate electrodes of the switching transistors CT1 to CT3 are commonly connected, and turned on at the same timing as the pulse of Pa shown in FIG.
The residual charge of 1104 is discharged to GND, and the charge is initialized.

In this embodiment, the photoelectric conversion means is T
FT-R1 to R9, shift register 1109, power supply 11
4 Refresh means are TFT-F1 to TFT-F
9, shift register 1108, power supply 1115, power supply 11
14 Further, the signal detection unit includes detection means within the dotted line in FIG. 44, TFT-T1 to T9, shift register 1106,
Refers to storage capacitors D1 to D9.

Next, the operation of the nineteenth embodiment will be described in time series.

First, when signal light enters the photoelectric conversion elements S1 to S9, each of the storage capacitors D1 to D
9 and the equivalent capacitance component of each photoelectric conversion unit 100 and the stray capacitance. At this time, as described in the eighteenth embodiment, in the storage capacitors D1 to D9, since the G electrode on the insulating layer side is a charge storage electrode, electrons and holes in each i layer of the storage capacitors D1 to D9 are: There is no flow on the G electrode, and no apparent leak current occurs. A high level is output from the first parallel terminal of the shift register 1106, and the transfer TFT-T1 to T-T
3 is turned on, the charges stored in the storage capacitors D1 to D3, the respective capacitance components, and the respective floating capacitances become:
Each is transferred to the common capacitors C100 to C120.
Subsequently, the high level output from the shift register 1107 shifts, and the switching transistors T100 to
T120 is sequentially turned on. Thus, the optical signals of the first block transferred to the common capacitors C100 to C120 are sequentially read out through the amplifier 1126.

After the transfer TFTs-T1 to T3 are turned off, a high level is output from the first parallel terminal of the shift register 1108, and the refresh TFTs-F1 to T3 are output.
F3 is turned on, and the potential of the G electrodes of the photoelectric conversion elements S1 to S3 increases. Then, the photoelectric conversion elements S1 to S3
Some of the holes inside are swept out to the common power supply line 1403.

Next, a high level is output from the first parallel terminal of the shift register 1109, and the reset TFT-R1 is output.
To R3 are turned on, whereby the photoelectric conversion elements S1 to S3 are turned on.
The potential of the G electrode in S3 is initialized to GND. Then, the common capacitors C100 to C12 are supplied by the pulse of Pa.
The potential of 0 is initialized. Common capacitors C100 to C
When the potential of 120 is completely initialized, the shift register 1106 shifts, and a high level is output from the second parallel terminal. Thereby, the transfer TFT-T4 to T6
Is turned on, and the storage capacitor D4 of the second block is turned on.
D6 and the equivalent capacitance components of the photoelectric conversion elements S4 to S6 and the signal charges accumulated in the stray capacitance are transferred to the common capacitors C100 to C120. Then, simultaneously with the case of the first block, the switching of the shift transistors 1100 to T120 is sequentially turned on by the shift of the shift register 1107, and the common capacitors C100 to C120 are turned on.
Are sequentially read out from the second block.

Similarly, in the case of the third block, a charge transfer operation and an optical signal read operation are performed.

As described above, a series of operations from the first block to the third block perform one operation in the main scanning direction of the original.
The reading of the signal for the line is completed, and the read signal is output in an analog manner according to the magnitude of the reflectance of the document.

As described with reference to FIG. 46 in this embodiment, the photoelectric conversion element, the storage capacitor, and the refresh T
The FT, the transfer TFT, the reset TFT, and the matrix signal wiring portion are composed of a first electrode layer, an insulating layer, an i-layer, an n-layer, a second
Although all the element portions do not necessarily have the same layer configuration, at least the photoelectric conversion element and the storage capacitor have this structure (MIS structure). It is sufficient for the other element portions to have a layer configuration having a function as each element. However, the fact that all the elements have the same layer configuration leads to further improvement in yield and cost reduction.

In the description of the eighteenth or nineteenth embodiment, holes and electrons may be reversed. For example, the injection blocking layer may be a P layer. In this case, if the direction in which the voltage or electric field is applied is reversed in the embodiment 18 or 19, and the other portions are configured in the same manner, the same operation result as in the above embodiment can be obtained.

Although the one-dimensional line sensor has been described in the nineteenth embodiment, a two-dimensional area sensor can be obtained by arranging a plurality of line sensors. Needless to say, the configuration can be realized by using the block division driving described in the above embodiment.

[0311] As described above, the nineteenth embodiment is different from the first embodiment.
8, the photoelectric conversion element, storage capacitor, TF
Since the T and matrix signal wiring portions have the same film configuration, they can be formed simultaneously in the same process, so that miniaturization and high yield can be achieved, and a low cost and high SN ratio photoelectric conversion device can be realized.

[Embodiment 20] Embodiment 20 will be described with reference to FIGS.

FIG. 47 is a schematic equivalent circuit diagram of a photoelectric conversion apparatus according to Embodiment 20 of the present invention. However, here, Example 19
As an example, a case of a photoelectric conversion element array having nine one-dimensionally arranged photoelectric conversion elements will be described as an example.

FIG. 48 shows one pixel of a set of a photoelectric conversion element portion having a plurality of pixels in the longitudinal direction, a storage capacitor / refresh capacitor portion, a transfer TFT portion, a reset TFT portion, and a wiring portion. FIG.

FIG. 49 is a sectional view of one pixel. FIG. 4
Reference numeral 9 is schematically drawn for easy understanding, and the position of the wiring portion does not always match FIG. FIG. 4
In FIG. 9, the reset TFT portion 1400 is not shown. Note that in FIGS. 47 to 49, FIGS.
46 are given the same reference numerals.

In FIG. 48, the photoelectric conversion unit 100 has a lower electrode 2 which also serves as a light shielding film for light from the substrate side. Light emitted from the substrate side is reflected by an original surface (not shown) positioned vertically above the drawing through the lighting window 17, and the reflected light enters the photoelectric conversion unit 100. The photocurrent generated by the carriers generated here is stored in the storage / refresh capacitor 1200 and the equivalent capacitance component of the photoelectric conversion unit 100 and other floating capacitance. The accumulated charges are transferred to the signal line matrix wiring section 1500 by the transfer TFT 1300 and read as a voltage by a signal processing section (not shown).

Referring to FIG. 49, the layer structure of each part will be briefly described.

In the figure, 100 is a photoelectric conversion unit, 1200 is a storage / refresh capacitor, and 1300 is a transfer TF.
T, 1500 are wiring portions, which are the first electrode layer 2
-1, 2-2, 2-3, insulating layer 70, i-layer 4, n-layer 5,
It has a configuration of a total of five common layers including the second electrode layers 6-1, 6-2, 6-3, and 6-4. Here, it is the same as Example 19 that the second electrode layer is not particularly formed as a transparent electrode.

Next, a method for driving the photoelectric conversion device of this embodiment will be described with reference to circuit diagrams.

In FIG. 47, photoelectric conversion elements S1 to S9
, Three blocks constitute one block, and three blocks constitute a photoelectric conversion element array. The storage and refresh capacitors C1 to C9 respectively connected to the photoelectric conversion elements S1 to S9, the TFTs R1 to R9 for initializing the G electrode potentials of the photoelectric conversion elements S1 to S9, and the signal charge transfer T
The same applies to FT-T1 to T9.

In each block of the photoelectric conversion elements S1 to S9, the individual electrodes having the same order are each provided with a transfer TFT-T.
It is connected to one of the common lines 1102 to 1104 via 1 to T9. More specifically, the first transfer TFT-T1, T4, T7 of each block is on the common line 1102, the second transfer TFT-T2, T5, T8 of each block is on the common line 1103, and Third transfer TF of
T-T3, T6, and T9 are connected to the common line 1104, respectively. The common lines 1102 to 1104 are connected to the amplifier 112 via the switching transistors T100 to T120, respectively.
6 is connected.

In FIG. 47, common lines 1102-1
104 are grounded via common capacitors C100 to C120, respectively, and the switching transistor CT
1 to CT3. Here, the gate electrodes of the switching transistors CT1 to CT3 are commonly connected, and turned on at the same timing as the pulse of Pa shown in FIG.
The residual charge of 1104 is discharged to GND, and the charge is initialized.

In this embodiment, the photoelectric conversion means is T
FT-R1 to R9, shift register 1109, power supply 11
4 The refresh means includes capacitors C1 to C
9, a shift register 1108, and a power supply 1114. Further, the signal detecting section is a detecting means within the dotted line in FIG.
T1 to T9, shift register 1106, capacitor C1
To C9. That is, in the present embodiment, the capacitors C1 to C9 accumulate the signal charges and constitute a part of the refresh unit.

Next, the operation of this embodiment will be described in time series.

First, when signal light is incident on the photoelectric conversion elements S1 to S9, charge is stored in each of the storage / refresh capacitors C1 to C9, the equivalent capacitance component of each photoelectric conversion unit 100, and each floating capacitance according to the intensity of the signal light. Is accumulated. At this time, as described in the eighteenth embodiment, each of the storage and refresh capacitors C1 to C9 has the G electrode on the insulating layer side serving as a charge storage electrode. The electrons and holes in the layer do not flow onto the G electrode, and no apparent leak current occurs. A high level is output from the first parallel terminal of the shift register 1106, and the transfer TFT-T
When the storage capacitors 1 to T3 are turned on, the charges stored in the storage and refresh capacitors C1 to C3, the respective capacitance components, and the respective floating capacitances are respectively transferred to the common capacitor C100.
To C120. Then, shift register 110
7 shifts to a high level, and the switching transistors T100 to T120 are sequentially turned on. Thereby, the common capacitors C100 to C120
Are sequentially read out through the amplifier 1126.

After the transfer TFTs T1 to T3 are turned off, a high level is output from the first parallel terminal of the shift register 1108, and the potentials at both ends of the storage and refresh capacitors C1 to C3 rise. That is, the potential of the G electrodes of the photoelectric conversion elements S1 to S3 increases. Then, holes in the photoelectric conversion elements S1 to S3 are swept out to the common power supply line 1403.

Next, the reset TFT-R whose high level has been output from the first parallel terminal of the shift register 1109.
By turning on 1 to R3, the photoelectric conversion element S1
Are reset to GND. Then, the common capacitors C100 to C1 are supplied by the pulse of Pa.
The potential of 20 is initialized. Common capacitor C100 ~
When the potential of C120 is completely initialized, the shift register 1106 shifts, and a high level is output from the second parallel terminal. Thereby, the transfer TFTs T4 to T4
6 is turned on, and the storage / refresh capacitors C4 to C6 and the photoelectric conversion elements S4 to S6 of the second block are turned on.
The signal charge accumulated in the equivalent capacitance component and the stray capacitance of No. 6 is transferred to the common capacitors C100 to C120. Then, as in the case of the first block, the switching of the switching transistor T
100 to T120 are sequentially turned on, and the optical signals of the second block stored in the common capacitors C100 to C120 are sequentially read.

Similarly, in the case of the third block, a charge transfer operation and an optical signal read operation are performed.

As described above, a series of operations from the first block to the third block perform one operation in the main scanning direction of the original.
The reading of the signal for the line is completed, and the read signal is output in an analog manner according to the magnitude of the reflectance of the document.

In this embodiment, the photoelectric conversion element, the storage / refresh capacitor, the transfer TFT, the reset TFT, and the matrix signal wiring portion are composed of the first electrode layer, the insulating layer, the i-layer, the n-layer, and the second Although all the element sections do not necessarily have the same layer configuration, at least the photoelectric conversion element and the storage / refresh capacitor have the same structure. (MI
S structure), and the other element portions only need to have a layer configuration having a function as each element. However, a common configuration is convenient for improving yield, reducing cost, and the like.

In this embodiment, a one-dimensional line sensor has been described. However, if a plurality of line sensors are arranged, a two-dimensional area sensor can be obtained. As in the nineteenth embodiment, the configuration can be realized by using the block division driving described in the above embodiment.

As described above, this embodiment is similar to Embodiment 1.
In addition to the effects of 8 and 19, the storage capacitor can be provided with a refresh function, so that miniaturization and high yield can be achieved, and a further low-cost photoelectric conversion device can be realized.

[Embodiment 21] FIG. 50 is a schematic circuit diagram of a photoelectric conversion device according to this embodiment.

In FIG. 50, S11 to Smn are photoelectric conversion elements arranged on a matrix, and the lower electrode side is denoted by G and the upper electrode side is denoted by D. C11 to Cmn are storage capacitors, and T11 to Tmn are transfer TFTs. Vs is a read power supply, and Vg is a refresh power supply, which are connected to the G electrodes of all the photoelectric conversion elements S11 to Smn via respective switches SWs and SWg. Switch S
Ws is connected via an inverter, and the switch SWg is directly connected to the refresh control circuit RF, and is controlled so that SWg is turned on during the refresh period and SWs is turned on during the other periods. One pixel includes one photoelectric conversion element, a capacitor connected in parallel to the photoelectric conversion element, and a TFT, and a signal output thereof is connected to the detection integrated circuit IC by a signal wiring SIG. The photoelectric conversion device of the present embodiment divides a total of m × n pixels into m blocks and simultaneously transfers outputs of n pixels per block, and outputs the signal wiring SIG.
And is sequentially converted into an output by the integrated circuit for detection IC and output (Vout). In addition, n pixels in one block are arranged in the horizontal direction, and m blocks are sequentially arranged in the vertical direction, so that each pixel is arranged two-dimensionally.

Note that the photoelectric conversion device shown in FIG.
9 operates in the same manner as the ninth embodiment except that the polarity of Vg and the magnitude of Vs are different.

The operation will be described.

First, shift registers SR1 and S1
The control lines g1 to gm and sg1 to sgn are Hi due to R2.
Is applied. Then, the transfer TFTs T11 to Tmn and the switches M1 to Mn are turned on to conduct, and all the photoelectric conversion elements S
The D electrodes 11 to Smn have the GND potential (because the input terminal of the integration detector Amp is designed to have the GND potential). At the same time, the refresh control circuit RF outputs Hi, the switch SWg turns on, and all the photoelectric conversion elements S11 to Smn
G electrode becomes negative potential having a small absolute value by the refresh power supply Vg. Then, all the photoelectric conversion elements S11 to Smn
Becomes refresh mode and is refreshed. Next, the refresh control circuit RF outputs Lo and the switch S
Ws is turned on, and the G electrodes of all the photoelectric conversion elements S11 to Smn become a negative potential having a large absolute value by the reading power supply Vs. Then, all the photoelectric conversion elements S11 to Smn enter the photoelectric conversion mode, and at the same time, the capacitors C11 to C33 are initialized.

As described above, in the refresh mode in this embodiment, the potential of the G electrode is negative with respect to the potential of the D electrode, and the potential of the G electrode does not reach the flat band voltage V _FB. . Therefore, as described in the previous embodiment, in the refresh mode, electrons do not reach the interface between the insulating layer and the photoelectric conversion semiconductor layer, and do not allow electrons to enter and exit interface defects due to the difference between the refresh mode and the photoelectric conversion mode. And a rush current can be reduced, and a photoelectric conversion device with a high SN ratio can be realized. In this embodiment, the D electrode of the photoelectric conversion element is connected to the TFT and is commonly connected to the G electrode of each photoelectric conversion element. However, the G electrode is connected to the TFT and the D electrode is commonly connected. You may. If the polarities of Vg and Vs at this time are reversed, the same operation is performed.

In this embodiment, the total number of pixels is n × m. The specific number may be optimally selected depending on the configuration system. For example, when one substrate is composed of 20 cm × 20 cm, n is 2, 000, m is 2,000, m × n
, That is, 4,000,000 photoelectric conversion elements
It can be configured with a density of 0 μm pitch.

In FIG. 50, the shift register SR1 and the integrated circuit for detection IC are each represented by one. However, actually, the shift register SR1 and the detection integrated circuit IC are constituted by appropriate numbers depending on the numbers m and n.

FIG. 51 is a schematic block diagram showing the entire system. In this figure, an a-Si sensor substrate 6001 drives a plurality of shift registers SR1 in series and a plurality of detection integrated circuit ICs. The output of the detection integrated circuit IC is input to an analog-to-digital converter 6002 in the processing circuit 6008 and digitized. This output is stored in the memory 6004 via the fixed pattern correction subtracter 6003. The information in the memory is controlled by a controller 6005 and transferred to an image processor as a signal processing means via a buffer 6006, where the image is processed.

FIG. 52 (a) and FIG. 52 (b)
It is a schematic configuration diagram and a schematic cross-sectional view when applied to a photoelectric conversion device for line detection.

A plurality of photoelectric conversion elements and TFTs are formed in the a-Si sensor substrate 6011, and the shift register SR1
And a flexible circuit board 6010 on which a detection integrated circuit IC is mounted. Flexible circuit board 6
The other side of 010 is connected to circuit boards PCB1 and PCB2. A plurality of the a-Si sensor substrates 6011 are adhered on a base 6012 to form a large-sized photoelectric conversion device.
A lead plate 6013 is mounted to protect 014 from X-rays. On the a-Si sensor substrate 6011, a phosphor 6030 such as CsI for converting X-rays into visible light is provided.
It is applied or pasted. 19 and 20 described above.
X-rays can be detected based on the same principle as the X-ray detection method described in (1). In the present embodiment, as shown in FIG.
Stored in.

FIG. 53 shows an application example of the photoelectric conversion device of the present invention to an X-ray diagnostic system.

The X-ray 60 generated by the X-ray tube 6050
Numeral 60 transmits through the chest 6062 of the patient or the subject 6061 and enters the photoelectric conversion device 6040 on which the phosphor is mounted. The incident X-ray includes information on the inside of the body of the patient 6061. The phosphor emits light in response to the incidence of X-rays, and this information is photoelectrically converted to obtain electrical information. This information is converted into digital information, image-processed by an image processor 6070, and can be observed on a display 6080 in a control room.

Further, this information can be transferred to a remote place by a transmission means such as a telephone line 6090, displayed on a display 6081 such as a doctor's room in another place, or stored in a storage means such as an optical disk. It is also possible to make a diagnosis. Also film processor 6
100 can also be recorded on the film 6110.

[0347]

As described in detail above, according to the present invention, S
A photoelectric conversion device with high N ratio and stable characteristics, a driving method thereof, and a system including the same can be provided.

According to the present invention, it is possible to provide a photoelectric conversion device having a high yield and easy production.

In addition, according to the present invention, a photoelectric conversion device which can be formed in the same process as a TFT, can be manufactured at low cost without complicating the manufacturing process, a driving method thereof, and A system having the same can be provided.

According to the present invention, the photoelectric conversion portion (photoelectric conversion element) in the photoelectric conversion device can detect the amount of incident light only at one injection blocking layer, and can easily optimize the process. The yield can be improved, the manufacturing cost can be reduced, and a low-cost photoelectric conversion device with a high SN ratio can be provided. Furthermore, since the tunnel effect and the Schottky barrier are not used in the first electrode layer / insulating layer / photoelectric conversion semiconductor layer, the electrode material can be freely selected, and the thickness of the insulating layer and other controls can be freely controlled. high. Also, it has good matching with switch elements and capacitance elements such as thin film field effect transistors (TFTs) formed simultaneously, and can be formed simultaneously as a common film because of the same film configuration, and the important film configurations of both the photoelectric conversion element and the TFT are the same. It can be formed at the same time in a vacuum, and the SN ratio and cost of the photoelectric conversion device can be reduced.

In addition, since the photoelectric conversion element itself stores optical information as a carrier and has a property of flowing a current in real time, a photoelectric conversion device having a simple configuration and a complex function can be provided. In addition, a high-performance photoelectric conversion device can be provided in which a capacitor also includes an insulating layer in an intermediate layer and has good characteristics and can output an integrated value of optical information obtained by a photoelectric conversion element with a simple configuration.

In the present invention, the refresh operation of the photoelectric conversion element can be performed through a capacitor or the like, and an inrush current can be generated at the moment when the applied voltage is reduced. As a result, compared with the case where refreshing is performed using a TFT, the accumulated inrush current is greatly reduced, and a low-cost photoelectric conversion device with a higher SN ratio can be provided.

In the refresh operation of the photoelectric conversion element, for example, when the semiconductor injection blocking layer of the photoelectric conversion element is n-type, that is, when the charge q of the carrier whose injection is prevented is positive, the potential of the D electrode is changed to the potential of the G electrode. Higher (｛ _rG
.Q) <(V _D .q-V _FB .q)} makes it possible to prevent electrons from entering or leaving interface defects between the insulating layer and the photoelectric conversion semiconductor layer. If the charge q of carriers is negative for the case of the semiconductor injection blocking layer p-type i.e. injection is prevented, the potential of the D electrode is lower than the potential of the electrode G _{{(V rG · q) <} (V D · q-V _FB · q)} makes it possible to prevent electrons from entering or leaving an interface defect between the insulating layer and the photoelectric conversion semiconductor layer, so that inrush current can be reduced, and a high SN ratio and low cost can be achieved. Can be provided.

Further, the signal charge storage capacitor is made to have the same laminated structure as that of the photoelectric conversion element, and is further stored in the electrode on the insulating layer side of the signal charge storage capacitor, whereby the signal charge storage capacitor is always accumulated. It can be used in a state, and it is possible to reduce a leak current generated by apparently leaking signal charges via the signal charge storage capacitor, and to provide a low-cost photoelectric conversion device with a high SN ratio.

In addition, since a plurality of photoelectric conversion elements can be divided into blocks, and a signal transfer operation and a refresh operation in another block can be simultaneously driven by the same drive line, the reading operation can be performed at high speed. And the size of the device can be further reduced, so that a high-yield, low-cost photoelectric conversion device can be provided.

Further, by using the photoelectric conversion device having the above-described excellent characteristics, a facsimile or an X-ray X-ray apparatus having a large area, a high function, and a high characteristic at a lower cost can be provided.

It is to be noted that the present invention is not limited to the above-described configuration and the above-described embodiments, and it is needless to say that modifications and combinations are possible within the scope of the gist of the present invention.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view (a) and a schematic circuit diagram (b) for describing a configuration example of a photoelectric conversion unit of the present invention.

FIG. 2 is a schematic cross-sectional view illustrating a configuration example of a TFT.

FIG. 3 is a diagram for explaining an example of the relationship between the thickness of a gate insulating film of a TFT and the yield.

FIG. 4 is a schematic cross-sectional view illustrating an example of a configuration of an optical sensor.

FIG. 5 is an energy band diagram for explaining an energy state of a photoelectric conversion unit.

FIG. 6 is a timing chart for explaining an example of the operation of the photoelectric conversion device of the present invention.

FIG. 7 is a schematic circuit diagram illustrating a configuration example of a detection unit.

FIG. 8 is a schematic circuit diagram for explaining the photoelectric conversion device of the present invention.

FIG. 9 is a schematic cross-sectional view for explaining an example of the photoelectric conversion unit of the present invention.

10A and 10B are a schematic cross-sectional view and a schematic circuit diagram illustrating a configuration example of a photoelectric conversion device including a photoelectric conversion unit according to the present invention.

11A and 11B are a schematic cross-sectional view and a schematic circuit diagram illustrating a configuration example of a photoelectric conversion device including a photoelectric conversion unit according to the present invention.

FIG. 12 is a schematic circuit diagram for explaining the photoelectric conversion device of the present invention.

13A and 13B are a schematic plan view and a schematic cross-sectional view illustrating an example of a photoelectric conversion device according to the present invention.

FIG. 14 is a schematic circuit diagram for explaining a photoelectric conversion device of the present invention.

15A and 15B are a schematic plan view and a schematic cross-sectional view illustrating an example of a photoelectric conversion device according to the present invention.

FIG. 16 is a schematic circuit diagram for explaining the photoelectric conversion device of the present invention.

17A and 17B are a schematic plan view and a schematic cross-sectional view illustrating an example of a photoelectric conversion device according to the present invention.

FIG. 18 is a timing chart illustrating an example of the operation of the photoelectric conversion device of the present invention.

FIG. 19 is a schematic circuit diagram for explaining a photoelectric conversion device of the present invention.

FIG. 20 is a schematic plan view (a) and a schematic cross-sectional view (b) illustrating an example of the photoelectric conversion device of the present invention.

FIG. 21 is a timing chart illustrating an example of an operation of the photoelectric conversion device of the present invention.

FIG. 22 is a schematic layout diagram for explaining a mounting example of a photoelectric conversion device.

FIG. 23 is a schematic layout diagram for explaining a mounting example of a photoelectric conversion device.

FIG. 24 is a schematic circuit diagram for explaining the photoelectric conversion device of the present invention.

FIG. 25 is a timing chart for explaining an example of the operation of the photoelectric conversion device of the present invention.

FIG. 26 is an energy band diagram for explaining an energy state of a photoelectric conversion unit.

FIG. 27 is an energy band diagram for describing an energy state of a photoelectric conversion unit.

FIG. 28 is a schematic circuit diagram for explaining the photoelectric conversion device of the present invention.

FIG. 29 is a timing chart illustrating an example of the operation of the photoelectric conversion device of the present invention.

FIG. 30 is an energy band diagram for describing an energy state of a photoelectric conversion unit.

FIG. 31 is a schematic circuit diagram for explaining a photoelectric conversion device of the present invention.

FIG. 32 is a schematic plan view illustrating an example of the photoelectric conversion device of the present invention.

FIG. 33 is a schematic circuit diagram for explaining the photoelectric conversion device of the present invention.

FIG. 34 is a timing chart illustrating an example of the operation of the photoelectric conversion device of the present invention.

FIG. 35 is a schematic circuit diagram for explaining the photoelectric conversion device of the present invention.

FIG. 36 is a schematic plan view illustrating an example of the photoelectric conversion device of the present invention.

FIG. 37 is a schematic cross-sectional view illustrating an example of the photoelectric conversion device of the present invention.

FIG. 38 is a timing chart illustrating an example of the operation of the photoelectric conversion device of the present invention.

FIG. 39 is a schematic circuit diagram for explaining the photoelectric conversion device of the present invention.

FIG. 40 is a timing chart illustrating an example of the operation of the photoelectric conversion device of the present invention.

FIG. 41 is a schematic circuit diagram for explaining a photoelectric conversion device of the present invention.

FIG. 42 is a schematic circuit diagram for explaining a photoelectric conversion device of the present invention.

FIG. 43 is a timing chart illustrating an example of the operation of the photoelectric conversion device of the present invention.

FIG. 44 is a schematic circuit diagram for explaining the photoelectric conversion device of the present invention.

FIG. 45 is a schematic plan view illustrating an example of the photoelectric conversion device of the present invention.

FIG. 46 is a schematic cross-sectional view illustrating an example of the photoelectric conversion device of the present invention.

FIG. 47 is a schematic circuit diagram for explaining the photoelectric conversion device of the present invention.

FIG. 48 is a schematic plan view illustrating an example of the photoelectric conversion device of the present invention.

FIG. 49 is a schematic cross-sectional view for explaining an example of the photoelectric conversion device of the present invention.

FIG. 50 is a schematic circuit diagram for explaining the photoelectric conversion device of the present invention.

FIG. 51 is a system configuration diagram for describing an example of a system having the photoelectric conversion device of the present invention.

FIGS. 52A and 52B are a schematic configuration diagram (a) and a schematic cross-sectional view (b) illustrating an example when applied to an X-ray detection device.

FIG. 53 is a system configuration diagram for describing an example of a system having a photoelectric conversion device of the present invention.

[Explanation of symbols]

 S11 to S33 Photoelectric conversion element C11 to C33 Storage capacitor T11 to T33 Transfer TFT 6010 Flexible circuit board 6011 a-Si sensor board 6012 Base 6013 Lead plate 6014 Memory 6018 Processing circuit 6020 Case 6030 Phosphor

 ──────────────────────────────────────────────────続 き Continued on front page (31) Priority claim number Japanese Patent Application No. 6-196642 (32) Priority date August 22, 1994 (22 August 1994) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 6-196643 (32) Priority date August 22, 1994 (August 22, 1994) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 6-196644 (32) Priority Date August 22, 1994 (August 22, 1994) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 6-196645 ( 32) Priority date August 22, 1994 (August 22, 1994) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 6-196648 (32) Priority date 1994 August 22, 1994 (22 August 1994) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 6-196670 (32) Priority date August 22, 1994 (1994. 8.22) (33) Priority claim country Japan (JP) (72) Inventor Shinichi Takeda 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Hidemasa Mizutani 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Tetsu Itabashi Inside Canon Inc. 3- 30-2 Shimomaruko, Ota-ku, Tokyo

Claims (8)

[Claims] 1. A photoelectric conversion device in which a plurality of photoelectric conversion elements are two-dimensionally arranged on a substrate, wherein the plurality of photoelectric conversion elements are arranged vertically or horizontally with respect to the two-dimensionally arranged photoelectric conversion elements. A photoelectric conversion device in which odd-numbered and even-numbered control lines or even lines among the control lines or signal lines arranged in the above are taken out on opposite sides, respectively, and each taken-out side is connected to a plurality of integrated circuit elements. 2. A photoelectric conversion device in which a plurality of photoelectric conversion elements are two-dimensionally arranged on a substrate, wherein the plurality of photoelectric conversion elements are arranged vertically or horizontally with respect to the plurality of two-dimensionally arranged photoelectric conversion elements. A plurality of integrated circuit elements connected to the control wiring or signal wiring, and connecting the control wiring or signal wiring continuous for each integrated circuit element, A photoelectric conversion device in which integrated circuit elements are divided left and right or up and down. 3. A plurality of substrates provided with a photoelectric conversion unit provided on a base and configured to two-dimensionally arrange a plurality of photoelectric conversion elements that receive X-rays and convert the signals into electric signals, and supply the plurality of substrates to the photoelectric conversion elements. A photoelectric conversion device, comprising: an integrated circuit element provided for a signal to be output or a signal output from the photoelectric conversion element; and a case accommodating the base and the integrated circuit element. 4. The photoelectric conversion device according to claim 3, wherein said case is made of carbon fiber. 5. The photoelectric conversion device according to claim 3, further comprising a lead plate provided on a side of the base opposite to a side on which the X-rays received by the photoelectric conversion elements are incident. 6. The photoelectric conversion device according to claim 5, wherein the lead plate is provided to protect the processing circuit from X-rays. 7. The photoelectric conversion device according to claim 3, wherein a phosphor is provided on a substrate having the photoelectric conversion portion. 8. The photoelectric conversion device according to claim 7, wherein the phosphor is provided to convert X-rays into visible light.