JP2000323649A - Hybrid integrated element and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a hybrid integrated element by mounting optical elements and electronic elements on the same substrate by the smaller number of reflow processes than a conventional manner. SOLUTION: This method comprises a first process for simultaneously forming a solder bump 11a for an optical element for fixing an optimal element 6 and a solder bump 11b for an electronic element for supporting an electronic element 7 in a batch on a substrate 1, a second process for fixing the optical element 6 by the solder bump 11a for the optical element, and a third process for supporting the electronic element 7 on the solder bump 11b for the electronic element, and for fixing the electronic element 7 on the solder bump 11b for the electronic element by cream soldering 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a hybrid integrated device in which an optical device and an electronic device are hybrid-mounted on the same substrate, and a method of manufacturing the same. In particular, the present invention relates to the fabrication of a hybrid integrated module that enables high-speed and high-performance signal processing by mixing an optical element and an electronic element on a substrate having an optical waveguide.

[0002]

2. Description of the Related Art In the field of optical communication in recent years, since it is necessary to handle both optical signals and electric signals, an optical element such as a laser diode (LD) or a photodiode (PD) is provided on a substrate having an optical waveguide. With IC and LS
The development of modules manufactured by hybrid integration of electronic devices such as I has been actively conducted. This is because the hybrid integration of optical and electronic elements on the same substrate not only enables high-speed and high-performance signal processing, but also allows the module to be reduced in size and cost. is there.

The configuration of such a conventional optoelectronic hybrid module will be described with reference to FIG. Note that FIG.
The parts that are embedded and should be represented by dotted lines are shown by solid lines for clarity.

As shown in the perspective view of FIG. 9, in a conventional optoelectronic hybrid module, an optical waveguide composed of a clad 2 made of quartz glass and a core 3 embedded therein is provided on a substrate 1 made of silicon. A portion 4 is formed, and on a region 5 formed by removing a part of the optical waveguide portion 4, an electric wiring 8 for driving an optical element 6 or an electronic element 7 and for inputting / outputting an electric signal is provided. Is formed. In the optical waveguide section 4, a planar lightwave circuit (Planar Lightwave) for realizing various optical signal processing is provided.
Circuit (PLC) is formed, and a substrate having a function of mounting the optical element 6 and the electronic element 7 together with the planar lightwave circuit is referred to as a PLC platform.
In recent years, it has been introduced into optical modules as a substrate that combines optical and electrical signal processing. The optical element mounting area 5a has an active layer (or light absorbing layer) 9 of the optical element 6 and a silicon terrace 10 functioning as a reference plane in the height direction of the optical axis of the core 3 of the optical waveguide section 4. The optical element 6 and the electronic element 7
Hybrid mounting is performed on the electric wiring 8 via the solder bumps 11. Further, the active layer (or light absorbing layer) 9 of the optical element 6 has a core 3 in the region 5a.
It is mounted so that it can be optically coupled with. Also, 5
b indicates an electronic element mounting area.

A method of mounting the conventional optical element 6 and electronic element 7 for producing the optoelectronic hybrid module shown in FIG. 9 will be described. For details of the method of mounting the optical element 6 using the solder bumps 11 on the PLC platform, see, for example, Japanese Patent Application Laid-Open No. 10-138046, “Optical Element Mounting Board and Hybrid Optical Integrated Circuit”, or “S. Mino, T. Ohyama, Y. Akahor
i, Y. Yamada, M, Yanagisawa,
T. Hashimoto, andY. Itaya "10
Gbit / shybrid-integrated
laser diode array module
using a planar lightwave
circuit (PLC) -platform ", Ele
ctron. Lett. , 1996, vol. 32, n
o. 24, pp. 2322-2233 ", and FIGS. 10 (a) to 10 (d) and FIGS.
This will be briefly described with reference to (i). Note that the same reference numerals as those in FIG. 9 indicate the same parts.

FIG. 10A shows a substrate 1 made of silicon.
On top of this, there is provided an optical waveguide section 4 composed of a silica glass clad 2 and a core 3 embedded therein, and an electric wiring 8 is formed on a region 5 formed by removing a part of the optical waveguide section 4. Shows a PLC platform on which is formed.

In the optical element mounting area 5a, a silicon terrace 10 functioning as a reference plane in the height direction of the optical axis between the active layer (or light absorbing layer) 9 of the optical element 6 and the core 3 of the optical waveguide section 4 is provided. It is formed. Electrical wiring 8 in optical element mounting area 5a
A laminated solder pattern 13 is formed on the optical element electrode 12a formed above. On the other hand, the electronic element mounting area 5b
Only the electrode 12b is formed on the electric wiring 8 described above.

Before the description of FIG. 10 (b), the method of forming the solder bump 11 will be described with reference to FIG. As shown in FIG. 12A, the surface of the electric wiring 8 is
It is covered with a thin glass layer 14 formed by sputtering, and a part of the glass layer 14 has a contact hole formed by RIE. An electrode 12 on the PLC platform side is formed by depositing a barrier metal 15 so as to cover the contact hole. The barrier metal 15 has a function of preventing the molten solder from diffusing toward the electric wiring 8 during the solder reflow. The electrode 12b for an electronic element and the electrode 12a for an optical element in FIG. 10A have the same structure, and the formation method is similar to the semiconductor process in the electronic element mounting area 5b and the optical element mounting area 5a. It is formed.

Further, in the optical element electrode 12 a, a solder material is laminated by vapor deposition over a wide range including the barrier metal 15 to form a laminated solder pattern 13. The composition of the laminated solder pattern 13 is controlled by vapor deposition so as to become eutectic solder after solder reflow. When the laminated solder pattern 13 is reflowed in a flux or an inert gas atmosphere, the molten solder on the glass layer 14 is repelled and gathers on the barrier metal 15 to form the solder bump 11. This state is shown in FIG.

As described above, since the optical element 6 is placed on the silicon terrace 10, there is a gap between the optical element side electrode 18a and the laminated solder pattern 13 on the PLC platform side as shown in FIG. , A gap g exists.
The solder bump 11 needs to be formed with a height h sufficient to connect the gap g. Since the height h of the solder bump 11 is determined by the surface area of the barrier metal 15 and the volume of the laminated solder pattern 13 as shown in FIG. 12B, the height h can be controlled in advance by design. Since these formation processes can be performed by photolithography and vapor deposition performed in a normal semiconductor process, the size control of the solder bumps 11 is extremely easy.

As described above, the solder bumps 11a in the optical element mounting area 5a on the PLC platform are formed (FIG. 10B).

Next, mounting of the optical element 6 is performed by a passive alignment method using an alignment mark (FIG. 10C).

After positioning the PLC platform and the optical element 6, the PLC platform is heated again to reflow the solder bumps 11a. In this state, the optical axis alignment is completed only by placing the optical element 6 on the silicon terrace 10, and the solder bump 11a on the PLC platform comes into contact with the optical element side electrode 18a in a molten state. This re-reflow step is also performed in an inert gas atmosphere in order to suppress the progress of oxidation of the solder bump surface. Thereafter, the temperature is returned to room temperature, so that the molten solder bump 1
1a is solidified to electrically connect and fix the optical element 6 (FIG. 10D).

Next, the mounting of the electronic element 7 is performed by using a transfer type micro solder bump forming technique. The details of this method are described in, for example, “Japanese Laid-Open Patent Application No. 5-166880,“ Method of Mounting Chip Wiring Board, etc. ”” or “Japanese Patent Application Laid-Open No. 10-106640.
It is better to refer to Japanese Patent Laid-Open Publication No. "Solder bump forming method and connection method using the same". This method will be briefly described with reference to FIG. 1. A solder pattern 1 formed on a carrier substrate 16 by vapor deposition or the like with an electronic element-side electrode 18b disposed thereon.
7 (FIG. 11 (e)) is transferred to the electronic element side electrode 18b (FIG. 11 (f)) to form the solder bump 11b (FIG. 11 (g)). Then, the PLC platform and the electronic element 7 are positioned (FIG. 11 (h)), and the solder bumps 11b of the electronic element 7 are brought into contact with the electronic element electrodes 12b on the PLC platform to reflow the solder bumps 11b. Thus, the electronic device 7 and the optical device 6 can be hybrid-mounted on the same PLC platform (FIG. 11 (i)).

What is important in this hybrid mounting method is the selection of a solder material for fixing the optical element 6 and the electronic element 7, respectively. That is, the solder bump 11b on the electronic element side
Is an absolute condition that the reflow temperature does not exceed the reflow temperature of the solder bump 11a on the optical element side already mounted. This is because, when the solder bump 11a on the optical element side is reflowed, the optical element 6 moves, which may cause an optical axis shift.

[0016]

In such a conventional hybrid mounting method, there is a problem that different solder materials must be selected for the solder bumps 11a and 11b of the optical element 6 and the electronic element 7, respectively. .

Further, since the solder bumps 11a and 11b used for the optical element 6 and the electronic element 7 are different, there is a problem that it is difficult to find a mounting condition that does not cause deterioration of the solder bumps.

Further, when a plurality of electronic elements 7 are mounted, the mounting steps from FIG. 11E to FIG. 11I must be repeated by the number of mounted elements, so that manufacturing time is required. There was such a problem.

Further, each time the mounting of the electronic element 7 shown in FIGS. 11 (h) to 11 (i) is repeated, reflow is repeated a plurality of times on the solder bump 11b of the electronic element 7 mounted first. There has been a problem that the connection reliability of 11b is deteriorated.

As a method for mounting the plurality of electronic elements 7, cream solder is applied to the substrate 1 by screen printing.
A method of applying the liquid on the electrodes on the side at once is also adopted. However, in this screen printing method, since cream solder is applied by a squeegee via a print mask, there is a problem that the squeegee hits the optical element 7 and cannot be applied to the substrate 1 on which the optical element 6 is already mounted.

In addition, since the thickness of the optical element 7 and the PLC platform itself have a region 5 formed by removing a part of the optical waveguide 4, the surface unevenness is severe.
The print mask could not be brought into close contact with the substrate 1 with high accuracy. For this reason, there has been a problem that the cream solder cannot be uniformly applied. This causes a problem in that the height of the solder bumps after the reflow varies, and when the electronic element 7 is mounted, electrodes that cannot be connected to the solder bumps appear.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a shape so that an optical element and an electronic element can be hybrid-integrated on the same substrate more easily than the conventional method. It is an object of the present invention to provide a hybrid integrated device having solder bumps with uniformity and a method of manufacturing the same. It is another object of the present invention to provide an element mounting method that can hybrid-integrate a plurality of optical elements and a plurality of electronic elements on the same hybrid integration substrate, and that does not deteriorate the connection reliability with each element. I do.

[0023]

In order to achieve the above object, a hybrid integrated device according to the present invention according to the first aspect is a device in which an optical device and an electronic device are hybrid-integrated on a substrate having an optical waveguide. In the method, the first solder bump for fixing the optical element and the second solder bump for supporting the electronic element are formed simultaneously at a time, and the electronic element is fixed via a conductive fixing material. Things.

According to a second aspect of the present invention, there is provided a method of manufacturing a hybrid integrated device, wherein a first solder bump for fixing the optical device and the electronic device are supported on a substrate having an optical waveguide. A first step of simultaneously forming a second solder bump for forming the optical element on the substrate;
And a third step of supporting the electronic element on the second solder bump and fixing the electronic element on the second solder bump with a conductive fixing material. It is.

According to a third aspect of the present invention, in the method of manufacturing a hybrid integrated device according to the second aspect, the conductive fixing material is applied onto the second solder bump in the third step. The electronic element is fixed on the second solder bump by the conductive fixing material.

According to a fourth aspect of the present invention, in the method for manufacturing a hybrid integrated device according to the third aspect, the conductive fixing material is applied onto an electrode of the electronic element in the third step. The electronic element is fixed on the second solder bump by the conductive fixing material.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a hybrid integrated device according to the second aspect of the present invention, wherein the conductive fixing material according to any one of the second to fourth aspects is applied to a solder bump formed collectively on the substrate. A conductive fixing material that solidifies at a temperature lower than the melting point is used.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a hybrid integrated device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the drawings. However, the present invention is not limited to these embodiments. .

[First Embodiment] FIGS. 1 and 2 show a first embodiment of a hybrid integrated device and a method of manufacturing the same according to the present invention. 9 to 12 indicate the same parts.

FIG. 1A shows an optical waveguide section 4 composed of a cladding 2 made of quartz glass and a core 3 embedded therein on a substrate 1 made of silicon. 2 shows a PLC platform in which an electric wiring 8 is formed on a region 5 formed by removing a part of the PLC platform. In the optical element mounting region 5a, a silicon terrace 10 functioning as a reference plane in the height direction of the optical axis between the active layer (or light absorbing layer) 9 of the optical element 6 and the core 3 is formed.
A laminated solder pattern 13 is formed on the electric wiring 8 (FIG. 1A).

Next, the laminated solder pattern 13 is collectively reflowed, and the solder bumps 11 are simultaneously formed in the optical element mounting area 5a and the electronic element mounting area 5b. These solder bumps 1
The method of forming 1 (only 11 is used to generically refer to 11a and 11b; the same applies to other reference numerals) is the same as the method described with reference to FIG. 12 (FIG. 1B).

The solder bump 11 in the optical element mounting area 5a
a is used to directly electrically connect and fix the optical element side electrode 18a and the electrode 12a of the PLC platform, and the solder bump 11b in the electronic element mounting area 5b is
It functions as a stud bump supporting the electronic element side electrode 18b. The present embodiment is characterized in that the solder bumps 11a and 11b having different functions are collectively formed by the same process.

Since the optical element 6 is placed on the silicon terrace 10, a gap g exists between the optical element side electrode 18a and the PLC platform side electrode 12a as shown in FIG. The height h of the solder bump has a height h sufficient to connect the gap g. Since the height h of the solder bump is determined by the surface area of the barrier metal and the volume of the laminated solder, it can be designed and formed in advance. For details of the design, refer to
No. 133046, “Optical element mounting substrate and hybrid optical integrated circuit” may be referred to. Since these formation processes can be performed by photolithography and vapor deposition performed in a normal semiconductor process, the size control of the solder bumps is extremely easy.

On the other hand, the solder bumps 11b for the studs formed in the electronic element mounting area 5b were also formed by the same process as the method described with reference to FIG. Here, the size such as the diameter and height of the solder bump 11b used for each electronic element 7 is as follows.
Each need not be the same. That is, it may be formed according to the size of the electronic element side electrode 18b. This is because, as described above, by controlling the area size of each barrier metal, a solder bump having a desired size can be arbitrarily formed by one-time solder lamination.

These solder bumps 11 can be formed collectively by heating the entire PLC platform and reflowing the laminated solder pattern 13. The solder reflow step is performed in a flux or an inert gas atmosphere in order to suppress the progress of oxidation of the solder surface (FIG. 1B).

Next, a method for mounting the optical element and the electronic element will be described in detail.

First, the optical element 6 is mounted on the PLC platform on which the solder bumps 11 are formed. Optical element 6
Was positioned by passive alignment using alignment marks (FIG. 1 (c)). Next, the PLC platform is heated again and the solder bumps 11 are heated.
(11a and 11b) are reflowed. In this state, the optical axis alignment is completed only by placing the optical element 6 on the silicon terrace 10, and the solder bump 11a on the PLC platform comes into contact with the optical element side electrode 18a in a molten state. The re-reflow step was also performed in an inert gas atmosphere in order to suppress the progress of oxidation of the solder bump surface. Thereafter, when the temperature is returned to room temperature, the molten solder bumps are solidified and the optical element 6 is removed.
Are electrically connected and fixed (FIG. 1D). During mounting of the optical element, the solder bump 11b in the electronic element mounting area 5b is also reflowed, but the bump shape does not change.

Next, the electronic element 7 is mounted. First, cream solder 19 is applied on the solder bumps 11b in the electronic element mounting area 5b. In the present embodiment, the cream solder 1
9 was applied from the needle 20 while supplying a constant amount (FIG. 2E). The application amount of the cream solder 19 may be small enough to be electrically connected to and fixed to the electronic element 7 after the cream solder reflow. (FIG. 2 (f)). After applying the cream solder, the electrode 18b on the electronic element side and the electrode 1 on the PLC platform side
After aligning with 2b and completing the alignment,
Pressing is performed until the electronic element side electrode 18b contacts the solder bump 11b. At this time, since the height of the solder bumps 11b is uniform and hard, the solder bumps 11b serve as stoppers for holding down the electronic elements. In other words, short-circuiting between adjacent electrodes due to crushing the cream solder 19 by pressing the electronic element 7 too much is prevented. in this way,
Since the solder bump 11b functions as an element support having an appropriate height, the cream solder 19 is
1b is wrapped around, and the electronic element 7 is fixed in a stable state with the solder bump 11b having a uniform shape as a base. Finally, the cream solder 19 is reflowed to fix the electronic element 7 (FIG. 2 (g)).

What is important here is the selection of the cream solder 19. It is an absolute condition that a solder having a reflow temperature of the cream solder 19 not exceeding the melting point temperature of the solder bump 11 is used. This is because, if the solder bumps 11 are reflowed, the optical element 6 may move and cause an optical axis shift.

Using the method described above, the solder bump 1
An opto-electronic hybrid module in which the optical element 6 and the electronic element 7 were hybrid-integrated on the substrate 1 was manufactured using the substrate 1 for hybrid integration on which the substrate 1 was formed. Here, a specific example in which a PD is used for the optical element 6 and a preamplifier that amplifies an electric signal output from the PD is used for the electronic element 7 and these are hybrid-integrated on a PLC platform to produce an optical receiving module State. AuSn solder, which is considered to be reliable in fixing an optical element, was used for the solder bump 11. Optical element side electrode 18a and P
The shape of the barrier metal 15 (see FIG. 12) of the optical element electrode 12a on the LC platform side has the same diameter 40.
It was a circular pattern of μm.

The gap g of the optical element mounting area 5a is 10 μm.
m. For this reason, the height h of the solder bump for fixing the optical element 6 needs to be 10 μm or more. "Japanese Patent Laid-Open No. 1
No. 0-133046, “Optical element mounting substrate and hybrid optical integrated circuit”, a circular AuS having a thickness of 4 μm and a diameter of 80 μm is applied to a circular barrier metal having a diameter of 40 μm
By forming the n-layer solder pattern 13a, a solder bump 11 having a height of about 18 μm can be formed after the solder reflow, which is sufficiently high for connection of a gap of 10 μm.

On the other hand, the electronic element side electrode 18b has a diameter of 80
The shape of the barrier metal 15 of the electrode 12b for the electronic device on the PLC platform side was also the same circular pattern of 80 μm in diameter. The circular solder pattern 13b stacked on the barrier metal had a diameter of 150 μm. Since the laminated thickness of AuSn solder is 4 μm,
The height h of the solder bump for electronic devices after reflow is about 2
0 μm.

AuSn laminated solder pattern 13 formed on PLC platform as described above (FIG. 1 (a))
Was reflowed in a flux to collectively form solder bumps 11 for the optical element and the electronic element (FIG. 1).
(B)). Since the melting point temperature of the AuSn solder is about 280 degrees, the reflow temperature was 300 degrees. After the reflow, the flux was washed away with an organic solvent. Next, the optical element 6
And PLC platform alignment (Fig. 1
(C)) The solder bump 11 was reflowed again, and in this state, the optical element 6 was brought into contact with the silicon terrace 10 to mount the optical element 6 (FIG. 1 (d)).

Next, cream solder 19 was applied to the solder bumps 11b in the electronic element mounting area 5b (FIG. 2).
(E)). The amount of cream solder 19 applied is
1b. The cream solder 19 is made of Sn
A Pb eutectic composition having a melting point of about 180
And sufficiently lower than the melting point of the AuSn solder bump. After the alignment between the preamplifier and the PLC platform (FIG. 2 (f)), the electrode 18b of the preamplifier is used.
Was pressed until it came into contact with the solder bump 11b, and the cream solder 19 was reflowed in this state (FIG. 2 (g)).
As described above, the optical device 6 and the electronic device 7 are
The optical receiving module hybrid-integrated on the C platform was manufactured.

Solder bump 11b in electronic element mounting area 5b
The conductive fixing material applied thereon is not limited to the cream solder 19 described above. For example, a conductive adhesive may be used. However, even when the conductive adhesive is used, its curing temperature must be lower than the melting point of the solder bump 11 for the above-described reason.

Further, in order to increase the fixing strength by the cream solder 19 or the conductive adhesive, as shown in FIG. 2 (h), by flowing a filler material 23 between the electronic element and the PLC platform, the connection reliability is improved. Sex can be increased.

According to the present embodiment, since the size of the solder can be controlled by the semiconductor process, a solder bump having a uniform shape can be formed. For this reason, the height h of the solder bump can be made uniform, so that the electrical connection with the mounted element can be reliably established. This further prevents the short-circuit between adjacent electrodes because it serves as a stopper when the electronic element is mounted.

Further, it is possible to eliminate the step of preparing a transfer type solder bump having a complicated step, which is required in the conventional mounting method of an electronic element, so that the manufacturing time of the optoelectronic hybrid module can be greatly reduced. Became.

[Second Embodiment] FIG. 3 is a perspective view showing a second embodiment of the present invention. In this embodiment, a method of manufacturing an optoelectronic module in which a plurality of optical elements 6 and a plurality of electronic elements 7 are hybrid-integrated on the same substrate 1 will be described with reference to FIGS. The perspective view of FIG. 3 shows a case where two optical elements 6 and two electronic elements 7 are mounted. Note that, in FIG. 3, portions that are embedded and should be represented by dotted lines are shown by solid lines for easy understanding.

The description of the parts common to the first embodiment is omitted or simplified. Here, the structure of the PLC platform different from that of the first embodiment is that a thin-film laminated solder pattern 13c is formed on the silicon terrace 10. The thin film laminated solder pattern 13c functions as a temporary fixing solder when a plurality of optical elements 6 are mounted, and functions to increase the fixing strength of the optical elements 6 after reflow soldering.

The solder lamination step on the PLC platform (FIG. 4A) is the same as that of FIG. 1A of the first embodiment. At this time, the thin-film laminated solder pattern 13c and the laminated solder patterns 13a and 13b used for the solder bumps are simultaneously formed by photolithography and vapor deposition.

After the formation of the laminated solder pattern 13, a plurality of optical elements 6 are first mounted on a PLC platform. In the present embodiment, unlike the first embodiment, the optical element 6
No solder bump 11 is formed before mounting. The mounting of the plurality of optical elements 6 is described in detail in Japanese Patent Application Laid-Open No. 9-54229, “Optical Element Fixing Method” or Japanese Patent Application Laid-Open No. 10-1330.
No. 46, "Optical element mounting substrate and hybrid optical integrated circuit". Briefly describing this method, the optical element 6 is aligned with the PLC platform (FIG. 4B), and then the optical element 6 is pressed onto the thin-film laminated solder pattern 13c and pressed (FIG. 4).
(C)). This series of steps (from FIG.
(C)) is repeated by the number of optical elements 6 to be mounted, and all the optical elements 6 are temporarily fixed on the PLC platform.
In FIG. 4, the illustration of the plurality of optical elements 6 is omitted. When the temporary fixing of all the optical elements 6 is completed, the laminated solder pattern 13 is reflowed in an inert gas atmosphere. Then, a thin-film laminated solder pattern 13c on the silicon terrace 10 is formed.
The optical element 6 is fixed on the silicon terrace 10 without changing its thickness, while the laminated solder pattern 13a on the optical element electrode 12a becomes a solder bump 11a and is connected to the electrode 18a on the optical element side. At this time, the laminated solder pattern 13b for the electronic element is also reflowed at the same time, and the solder bump 11b is formed.
Is formed (FIG. 4D). As described above, since the solder is reflowed only once, a plurality of optical elements are mounted without deteriorating the connection reliability of the solder bumps.

Next, a plurality of electronic elements 7 are mounted.
Similarly to FIG. 2E of the first embodiment, the solder bumps 11b
The cream solder 19 may be applied directly to each of the solder bumps 11b. However, in this embodiment, the cream solder 19 is collectively applied to the solder bumps 11b by the method shown in FIGS. 5 (e) to 6 (i). Apply on top. First, as shown in FIG. 5E, a dummy substrate 21 having a projection in an electrode arrangement in the electronic element mounting area 5b is manufactured. Next, the protrusion is immersed in the cream solder tank 22 (FIG. 5 (f)) and then pulled up, so that the cream solder 19 sticks to the tip of the protrusion due to its viscosity and surface tension (FIG. 5 (g)). At this time, the amount of the sucked cream solder 19 can be constant because the amount of the sucked solder 19 can be in the state of the tip of the projection. Then, the dummy substrate 21 is aligned with the electronic element electrode 12b on the PLC platform, and is pressed against the solder bump 11b as it is (FIG. 6 (h)). Then, the cream solder 19 is copied onto the solder bump 11b (FIG. 6 (i)). In this embodiment, if the dummy substrate 21 is processed with silicon and the tip of the protrusion is subjected to thermal oxidation, the cream solder 19 is easily transferred to the solder bump 11b due to the difference in water repellency.

As described above, since the cream solder 19 can be applied to the solder bumps 11b for each electronic element 7 at a time, the time required for the application step is significantly shorter than that of the first embodiment. Can be shortened. Furthermore, if the dummy substrate 21 having the protrusions is arranged in the arrangement of all the plurality of solder bumps, it is possible to perform only one application.

The reflow temperature of the cream solder 19 used in this embodiment is also different from that of the solder bump 11 for the reason described above.
Those having a melting point lower than the melting point were used.

Thereafter, the electronic element 7 was aligned on a PLC platform (FIG. 6 (j)), and was temporarily mounted by pressing the electrode 18b of the electronic element 7 until it came into contact with the solder bump 11b. From this step (FIG. 5E) to FIG.
(J)) was repeated by the number of mounted electronic elements 7.
4 to 6, illustration of the plurality of electronic elements 7 is omitted. After the provisional mounting of all the electronic elements 7 was completed, the cream solder 19 was reflowed at once, and the electronic elements 7 were hybrid-integrated (FIG. 6 (k)). Here, since the cream solder 19 is reflowed only once, a plurality of electronic elements can be mounted without deteriorating the connection reliability.

As described above, an optoelectronic hybrid module in which a plurality of optical elements 6 and a plurality of electronic elements 7 are mounted in a hybrid manner can be manufactured.

This embodiment is more effective as the number of mounted elements and the number of electrodes are increased. Further, this method is more effective as the pitch between the electrodes becomes smaller and the electrode size becomes smaller.

Also, instead of the steps of FIGS. 6 (h) to 6 (i), as shown in FIGS. 7 (a) to 7 (c), a dummy substrate as shown in FIG. The cream solder 19 copied to 21 may be applied on the electrode 18b on the electronic element side, and then the electronic element 7 may be mounted on a PLC platform as shown in FIGS. 7 (d) to 7 (e). Also in this case, the cream solder 19 can be reflowed at once after the provisional mounting of all the electronic elements 7 is completed.
A plurality of electronic elements can be mounted without deteriorating connection reliability.

Also in the present embodiment, the conductive fixing material for connecting the electronic element 7 on the solder bump 11b in the electronic element mounting area 5b is not limited to the cream solder 19. For example, a conductive adhesive may be used, but in this case, the curing temperature must be lower than the melting point of the solder bump 11.

Further, in order to increase the fixing strength with the cream solder 19 and the conductive adhesive, the first embodiment shown in FIG.
As in (h), the filler 23 may be poured between the electronic element 7 and the PLC platform, or the reliability of the connection can be increased by molding the entire electronic element with a sealant.

At the position of the thin film laminated solder pattern 13c,
Electrodes may be provided on the PLC platform side and the optical element 6 side. In this case, the optical element 6 is fixed and electrical conduction can be achieved via the thin film laminated solder pattern 13c.

[Third Embodiment] FIG. 8 shows a third embodiment of the electronic element mounting step according to the present invention.
Here, a method of manufacturing a hybrid integrated optoelectronic module using an anisotropic conductive paste 24 for connection to the electronic element 7 unlike the first and second embodiments described above will be described.

The anisotropic conductive paste is an adhesive containing conductive fine particles, and does not have conductivity only by applying this paste. In a general mounting method of the electronic element 7 using an anisotropic conductive paste, first, an anisotropic conductive paste is applied on a substrate-side electrode. Next, the element-side electrode and the substrate-side electrode to be mounted are pressed together. At this time, for the first time, an electrical connection is made through the conductive fine particles sandwiched between the electrodes, and finally, the adhesive is cured, whereby the electronic element 7 is fixed.

When this method is used, a stud metal is usually formed on an electrode on the substrate side or on the element side so that a sufficient pressure is locally applied between the electrodes in order to reliably obtain electrical conduction. Is common.

The present embodiment is characterized in that solder bumps 11 are used instead of the stud metal.

In this embodiment, the method of mounting the optical element 6 is the same as the method of FIGS. 1A to 1D or the method of FIGS. 4A to 4D, for example. It is. Descriptions common to the first or second embodiment will be omitted or simplified. After the mounting of the optical element 6 is completed, as shown in FIG.
An anisotropic conductive adhesive 24 is applied on the solder bumps 11b on b. After applying the anisotropic conductive adhesive 24, the electrode 18b on the electronic element 7 side and the electrode 12b on the PLC platform side
(FIG. 8B), and when the positioning is completed, the electronic element-side electrode 18b is pressed on the solder bump 11b. At this time, electrical conduction is obtained by the conductive fine particles 25 sandwiched between the electrode 18b and the solder bump 11b,
Finally, the anisotropic conductive adhesive 24 is cured, and the electronic element 7
Is fixed (FIG. 8C).

By repeating such a method as many times as the number of the electronic elements 7 mounted, a plurality of electronic elements are hybrid-integrated with the optical element 6 on the same PLC platform. Also in the present embodiment, the curing temperature of the anisotropic conductive adhesive 24 must be lower than the melting point temperature of the solder bump 11 for the reason described above.

According to the embodiment of the present invention, unlike the method of mounting the electronic element described in the first or second embodiment, the solder bumps 11b on the electronic element mounting area 5b are electrically conductive. There is no need to apply a fixing material,
In addition, since the application accuracy of the conductive fixing material does not matter, the application process can be further simplified, and the electronic element mounting process can be greatly simplified. This means that the greater the number of mounted electronic elements 7 or the greater the number of electrodes and the higher the electrode arrangement density, the greater the effectiveness of the present embodiment.

Regardless of this embodiment, the number of optical elements 6 may be plural. PLC in this case
The configuration of the platform, the method for mounting the optical element, and the method for forming the solder bumps are the same as those described in the second embodiment.

[0071]

As described above, in the hybrid integrated device according to the present invention, the first solder bump for fixing the optical element and the second solder bump for supporting the electronic element are simultaneously formed at the same time. As a result, a high quality connection is ensured without receiving a plurality of reflows as in the prior art.

Further, in the method for manufacturing a hybrid integrated device according to the present invention, the first solder bump for fixing the optical device and the second solder bump for supporting the electronic device are formed on the substrate. A first step of forming the optical element at the same time, a second step of fixing the optical element with a first solder bump, and a step of supporting the electronic element on the second solder bump and forming the optical element on the second solder bump. And the third step of fixing with a conductive fixing material, so that the solder bumps for mounting the optical element and the electronic element can be formed at a time.

Further, by using the same method as the semiconductor process for the shape of the solder bump that can be formed, a solder bump having a uniform shape can be formed. For this reason, since the height of the solder bumps can be made uniform, electrical connection with the mounted element can be reliably obtained. This also serves as a stopper when the electronic element is mounted, so that a short circuit between adjacent electrodes can be prevented.

Also, the conventional method of mounting an electronic element is as follows.
This makes it possible to eliminate the step of preparing a transfer-type solder bump having a complicated step, thereby greatly reducing the time required to manufacture an optoelectronic hybrid module.

In addition, the step of solidifying the conductive fixing material is as follows.
Since the number of times is sufficient, a plurality of electronic elements can be mounted without deteriorating the connection reliability.

Further, a plurality of optical elements and a plurality of electronic elements can be easily hybrid-mounted on the same substrate, and the more the number of mounted elements and the number of electrodes are increased, the more effective it becomes. The more effective the smaller the pitch between the electrodes and the smaller the electrode size.

Further, since the application accuracy of the conductive fixing material is not required, it is possible to further facilitate the application step and to greatly simplify the electronic element mounting step. This means that as the number of mounted electronic elements increases,
Alternatively, the usefulness increases as the number of electrodes increases and the electrode arrangement density increases.

[Brief description of the drawings]

FIG. 1 is a process chart showing a first embodiment of a hybrid integrated device and a method of manufacturing the same according to the present invention.

FIG. 2 is a process chart showing a first embodiment of a hybrid integrated device and a method of manufacturing the same according to the present invention.

FIG. 3 is a perspective view showing a second embodiment of the hybrid integrated device according to the present invention.

FIG. 4 is a process chart showing a second embodiment of a hybrid integrated device and a method of manufacturing the same according to the present invention.

FIG. 5 is a process chart showing a second embodiment of the hybrid integrated device and the method for manufacturing the same according to the present invention.

FIG. 6 is a process chart showing a second embodiment of a hybrid integrated device and a method for manufacturing the same according to the present invention.

FIG. 7 is a process chart showing a second embodiment of a hybrid integrated device and a method of manufacturing the same according to the present invention.

FIG. 8 is a process chart showing a third embodiment of the hybrid integrated device and the method of manufacturing the same according to the present invention.

FIG. 9 is a perspective view showing a hybrid integrated device according to the related art.

FIG. 10 is a process diagram showing a method for manufacturing a hybrid integrated device according to a conventional technique.

FIG. 11 is a process diagram showing a method for manufacturing a hybrid integrated device according to a conventional technique.

FIG. 12 is a cross-sectional view of a main part of a conventional hybrid integrated device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Cladding 3 Core 4 Optical waveguide part 5 area 5a Optical element mounting area 5b Electronic element mounting area 6 Optical element 7 Electronic element 8 Electrical wiring 9 Active layer (or light absorption layer) 10 Silicon terrace 11a Solder bump for optical element ( 11b Solder bump for electronic element (second solder bump) 12a Electrode for substrate side optical element 12b Electrode for substrate side electronic element 13 Laminated solder pattern 13a Laminated solder pattern for optical element 13b For electronic element Laminated solder pattern 13c Thin-film laminated solder pattern 14 Glass layer 15 Barrier metal 16 Carrier substrate 19 Cream solder (or conductive adhesive) 20 Needle 21 Dummy substrate 22 Cream solder tank 23 Filler 24 Anisotropic conductive adhesive

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[Procedure amendment]

[Submission date] July 11, 2000 (2007.1.
1)

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 9

[Correction method] Change

[Correction contents]

FIG. 9

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Takashi Yamada 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo F-term in Nippon Telegraph and Telephone Corporation (reference) 2H047 MA07 QA04 5E319 AA03 AB05 BB04 BB05 BB16 CC33 GG11 5F044 KK05 KK19 KK23 LL01 LL07 LL09 QQ01 RR01

Claims (5)

[Claims] In a device in which an optical element and an electronic element are hybrid-integrated on a substrate having an optical waveguide, a first solder bump for fixing the optical element and a second solder bump for supporting the electronic element are: A hybrid integrated device formed simultaneously at a time and fixing the electronic device via a conductive fixing material. 2. A method of manufacturing a hybrid integrated device in which an optical element and an electronic element are hybrid-integrated on a substrate having an optical waveguide, wherein the first solder bump for fixing the optical element and the electronic element are supported. A second step of simultaneously forming a second solder bump on the substrate at a time, a second step of fixing the optical element with the first solder bump, and a second step of fixing the electronic element to a second solder bump. A third step of supporting on the solder bumps and fixing on the second solder bumps with a conductive fixing material, the method comprising the steps of: 3. In a third step, after applying the conductive fixing material on a second solder bump, fixing the electronic element on the second solder bump with the conductive fixing material. The method for manufacturing a hybrid integrated device according to claim 2, wherein: 4. The method according to claim 3, wherein in the third step, the conductive fixing material is applied on an electrode of the electronic element, and then the electronic element is fixed on the second solder bump with the conductive fixing material. The method for manufacturing a hybrid integrated device according to claim 2, wherein: 5. The conductive fixing material according to claim 2, wherein the conductive fixing material is solidified at a temperature lower than the melting point of the solder bumps collectively formed on the substrate. A manufacturing method of the hybrid integrated device according to the above.