JP3405402B2 - Parallel transmission type optical module and method of manufacturing the same - Google Patents
Parallel transmission type optical module and method of manufacturing the sameInfo
- Publication number
- JP3405402B2 JP3405402B2 JP17709599A JP17709599A JP3405402B2 JP 3405402 B2 JP3405402 B2 JP 3405402B2 JP 17709599 A JP17709599 A JP 17709599A JP 17709599 A JP17709599 A JP 17709599A JP 3405402 B2 JP3405402 B2 JP 3405402B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- transmission type
- parallel transmission
- optical module
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000003287 optical effect Effects 0.000 title claims description 91
- 230000005540 biological transmission Effects 0.000 title claims description 45
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000000758 substrate Substances 0.000 claims description 144
- 239000000919 ceramic Substances 0.000 claims description 56
- 239000002184 metal Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000013307 optical fiber Substances 0.000 claims description 20
- 230000017525 heat dissipation Effects 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims 1
- 239000011295 pitch Substances 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 229920000642 polymer Polymers 0.000 description 5
- 230000005855 radiation Effects 0.000 description 5
- 238000000347 anisotropic wet etching Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000004014 plasticizer Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Optical Couplings Of Light Guides (AREA)
- Led Device Packages (AREA)
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は、光通信用並列伝送
型光モジュールに関する。また本発明は、その製造方法
にも関する。TECHNICAL FIELD The present invention relates to a parallel transmission type optical module for optical communication. The present invention also relates to the manufacturing method thereof.
【0002】[0002]
【従来の技術】光通信は光ファイバ、半導体レーザ(L
D)、発光ダイオード(LED)、フォトダイオード
(PD)を始めとして、光スイッチ、光変調器、アイソ
レータ、光導波路等の受動、能動素子の高性能、高機能
化により応用範囲が拡大されつつある。近年、より多く
の情報を伝達する要求が高まる中で、コンピュータ端末
間、交換器や大型コンピュータ間のデータ伝送を実時間
で並列に行う並列伝送が注目されつつある。この機能を
満足するものとして、複数の発光あるいは受光素子と複
数の光ファイバを一体化した並列伝送型モジュールがあ
る。通常、発光(受光)素子は同一半導体基板上にモノ
リシックに複数個配列したLD、PDアレイ、そして光
ファイバは、一方向に複数本配列した光ファイバアレイ
が用いられている。2. Description of the Related Art Optical communication uses optical fibers and semiconductor lasers (L
D), light emitting diodes (LEDs), photodiodes (PDs), optical switches, optical modulators, isolators, optical waveguides, and other passive and active devices have been expanding their application range due to high performance and high functionality. . In recent years, with the increasing demand for transmitting more information, parallel transmission, which performs data transmission between computer terminals, switches and large computers in parallel in real time, is drawing attention. There is a parallel transmission type module that integrates a plurality of light emitting or light receiving elements and a plurality of optical fibers to satisfy this function. Usually, a plurality of light emitting (light receiving) elements are monolithically arranged on the same semiconductor substrate, such as LD and PD arrays, and a plurality of optical fibers are arranged in one direction.
【0003】図7は1チャネル当たり数百Mヘルツレベ
ルの並列伝送光モジュールの一例で、図7(a)は断面
図、図7(b)は平面図である。放熱性の良い共通基板
20上に光実装基板24とセラミック電気実装基板28
が配置されている。光実装基板24は放熱性、及び光フ
ァイバ実装用の溝の加工性からシリコン(Si)が通常
用いられる。光実装基板24上に、SiO2などの絶縁
膜を介して12チャネルのアレイ状のLDあるいはPD
21(以下、LD21で代表する)が配置される。LD
21から出射された光は、近接して配置されたポリマ系
光導波路22に結合する。この光導波路22でアレイピ
ッチ間隔が250μm一定に変換され、その出射端にア
レイ光ファイバ23が配置される。アレイ光ファイバ2
3は、通常リボン状に構成され、異方性ウェットエッチ
ングで精密に形成されたV溝25に高精度に固定され
る。FIG. 7 shows an example of a parallel transmission optical module having a level of several hundreds of megahertz per channel. FIG. 7 (a) is a sectional view and FIG. 7 (b) is a plan view. The optical mounting board 24 and the ceramic electrical mounting board 28 are mounted on the common board 20 having good heat dissipation.
Are arranged. The optical mounting substrate 24 is usually made of silicon (Si) because of its heat dissipation and workability of the groove for mounting the optical fiber. An array of 12-channel LDs or PDs on the optical mounting substrate 24 with an insulating film such as SiO 2 interposed therebetween.
21 (hereinafter, represented by LD21) is arranged. LD
The light emitted from 21 is coupled to the polymer-based optical waveguide 22 arranged in close proximity. The optical waveguide 22 converts the array pitch interval to a constant 250 μm, and the array optical fiber 23 is arranged at the emitting end. Array optical fiber 2
3 is usually formed in a ribbon shape, and is highly accurately fixed to the V groove 25 precisely formed by anisotropic wet etching.
【0004】電気実装基板28は、多層配線設計の容易
さ、及び製造コストから、通常アルミナ基板が用いられ
る。電気実装基板28上にはLD21のアナログドライ
バIC26とロジックIC27などの電気素子が配置さ
れる。高速駆動の場合、電気実装基板28は多層に構成
される。光実装基板24と電気実装基板28はワイヤボ
ンド29で電気的に接続される。As the electrical mounting substrate 28, an alumina substrate is usually used because of the ease of designing the multilayer wiring and the manufacturing cost. On the electric mounting substrate 28, electric elements such as the analog driver IC 26 of the LD 21 and the logic IC 27 are arranged. In the case of high speed driving, the electrical mounting substrate 28 is constructed in multiple layers. The optical mounting substrate 24 and the electrical mounting substrate 28 are electrically connected by wire bonds 29.
【0005】[0005]
【発明が解決しようとする課題】ギガヘルツ以上の高速
信号を扱う並列伝送型モジュールでは全てのチャネルが
高速に、しかも独立に動作する必要があるために、素子
間の配線長を短くして、かつワイヤボンド排除する必要
がある。従って、図7のモジュール構成では、チャネル
間のクロストークという不具合が発生する問題がある。In a parallel transmission type module that handles high-speed signals of gigahertz or higher, all channels must operate at high speed and independently, so that the wiring length between elements must be shortened, and Wire bonds need to be eliminated. Therefore, the module configuration of FIG. 7 has a problem that a problem of crosstalk between channels occurs.
【0006】これに対して、IC26などの電気素子と
LD21などの光素子を同一基板にフリップチップ実装
することで、素子間距離を小さくしてワイヤボンドをな
くすことができる。しかし、以下に示す問題がある。共
通基板が光実装基板であるSiの場合、Siは絶縁体で
はなく半導体であるので、高速動作時にチャネル間の電
気クロストークが発生する。また、基板を容易に多層構
成にできないので、高速動作に不都合が生じる。一方、
高速動作に有利なアルミナなどのセラミック多層基板を
共通基板にした場合、アルミナ基板は熱伝導がSiに比
べて1桁以上悪いので、LDの放熱に不具合が生じLD
の動作が不安定になる。また、セラミック基板は高精度
の機械加工が困難であるので、光ファイバ整列用の精密
溝の形成が容易でない難点がある。On the other hand, by flip-chip mounting the electric element such as the IC 26 and the optical element such as the LD 21 on the same substrate, the distance between the elements can be reduced and the wire bond can be eliminated. However, there are the following problems. When the common substrate is Si, which is an optical mounting substrate, since Si is a semiconductor rather than an insulator, electrical crosstalk between channels occurs during high-speed operation. Further, since the substrate cannot be easily formed into a multi-layer structure, high speed operation is inconvenient. on the other hand,
When a ceramic multi-layer substrate such as alumina, which is advantageous for high-speed operation, is used as a common substrate, the alumina substrate has a heat conduction that is one digit or more worse than that of Si.
Becomes unstable. Further, since it is difficult to machine the ceramic substrate with high precision, it is difficult to form precision grooves for aligning optical fibers.
【0007】本発明の目的は上記の問題点を解決し、光
素子、電気素子双方が混載された並列伝送型光モジュー
ルを提供することにある。An object of the present invention is to solve the above problems and provide a parallel transmission type optical module in which both optical elements and electric elements are mounted together.
【0008】[0008]
【問題を解決するための手段】本発明の並列伝送型光モ
ジュールは、セラミック基板に、光素子を搭載したSi
基板が貼り合わされており、少なくとも光素子とセラミ
ック基板との電気接続が、該光素子がSi基板表面に絶
縁層を介して形成された金属電極と電気的に接続され、
該金属電極がSi基板底面まで延在してセラミック基板
上に形成された電極と直接接続されて成されることを特
徴とする構成である。A parallel transmission type optical module of the present invention is a Si substrate having an optical element mounted on a ceramic substrate.
The substrate is bonded, at least the electrical connection between the optical element and the ceramic substrate, the optical element is electrically connected to the metal electrode formed on the surface of the Si substrate through the insulating layer,
The metal electrode extends to the bottom surface of the Si substrate and is directly connected to the electrode formed on the ceramic substrate.
【0009】前記Si基板には光素子に加えて、さらに
光導波路、光ファイバが配置されており、前記セラミッ
ク基板が多層構造に形成され、電気素子はセラミック基
板上に形成された樹脂製ビルドアップ基板上に配置され
ることを特徴とする並列伝送型光モジュールである。
又、Si基板とセラミック基板との電気接続は、Si基
板に形成された貫通穴を通して行われ、Si基板に形成
された貫通穴において、貫通後に酸化膜などで絶縁され
た後に金属電極が形成され、セラミック基板上に形成さ
れた電極に接続される。前記貫通穴は、Si基板上面か
らの異方性エッチングの後、Si基板裏面を研磨するこ
とで形成されたものである。さらにセラミック基板のS
i基板接合部に放熱ビアを設けたことを特徴とする並列
伝送型光モジュールである。In addition to an optical element, an optical waveguide and an optical fiber are arranged on the Si substrate, the ceramic substrate is formed in a multilayer structure, and the electric element is a resin build-up formed on the ceramic substrate. The parallel transmission type optical module is arranged on a substrate.
Further, the electrical connection between the Si substrate and the ceramic substrate is performed through a through hole formed in the Si substrate, and in the through hole formed in the Si substrate, a metal electrode is formed after being insulated by an oxide film or the like after the penetration. , Connected to the electrodes formed on the ceramic substrate. The through hole is formed by polishing the rear surface of the Si substrate after anisotropic etching from the upper surface of the Si substrate. Furthermore, S of the ceramic substrate
The parallel transmission type optical module is characterized in that a heat dissipation via is provided in the i substrate joint portion.
【0010】また本発明は、セラミック基板に、光素子
を搭載したSi基板を貼り合わせてなる並列伝送型光モ
ジュールの製造方法であって、Si基板表面に絶縁層を
介して該Si基板底面まで延在する金属電極を形成する
工程、該Si基板をセラミック基板上に、前記金属電極
とセラミック基板上に形成した電極とが直接接続される
ように貼り合わせる工程、前記金属電極に光素子を電気
的に接続する工程、とを有してなる並列伝送型光モジュ
ールの製造方法に関するものである。Further, the present invention is a method of manufacturing a parallel transmission type optical module comprising a ceramic substrate and an Si substrate on which an optical element is mounted, which is bonded to the Si substrate surface through an insulating layer to the Si substrate bottom surface. A step of forming an extending metal electrode; a step of adhering the Si substrate on a ceramic substrate so that the metal electrode and an electrode formed on the ceramic substrate are directly connected; and an optical element electrically connected to the metal electrode. The present invention relates to a method for manufacturing a parallel transmission type optical module including a step of electrically connecting.
【0011】[0011]
【発明の実施の形態】セラミック基板上に貼り合わされ
たSi基板にはLD、光導波路、光ファイバが配置され
ている。セラミック基板は多層構造に形成され、Si基
板の近傍にドライバICなど制御電気素子が配置されて
いる。高密度の配線が必要な場合は、電気素子はセラミ
ック基板上に形成された樹脂製ビルドアップ基板上に配
置される。Si基板とセラミックとの電気接続はSi基
板に形成された貫通穴を通して行われる。貫通穴では、
貫通後に酸化膜などで絶縁された後に金属電極が形成さ
れ、下基板のセラミックに形成された電極に接続され
る。ここで、貫通穴は、異方性エッチングや機械的な加
工で形成されるが、穴形状の縮小、加工時間の低減のた
めにSi基板は研磨などで厚みが小さくされている。光
素子と電気素子の配線長を極力短くする場合には、貫通
穴の電極に電気素子の電極が直接接合される。BEST MODE FOR CARRYING OUT THE INVENTION An LD, an optical waveguide, and an optical fiber are arranged on a Si substrate bonded on a ceramic substrate. The ceramic substrate is formed in a multilayer structure, and a control electric element such as a driver IC is arranged near the Si substrate. When high-density wiring is required, the electric element is arranged on a resin build-up board formed on a ceramic board. The electrical connection between the Si substrate and the ceramic is made through a through hole formed in the Si substrate. In the through hole,
A metal electrode is formed after being penetrated and insulated by an oxide film or the like, and connected to an electrode formed on the ceramic of the lower substrate. Here, the through hole is formed by anisotropic etching or mechanical processing, but the thickness of the Si substrate is reduced by polishing or the like in order to reduce the hole shape and the processing time. When the wiring length between the optical element and the electric element is made as short as possible, the electrode of the electric element is directly bonded to the electrode of the through hole.
【0012】光素子、及び電気素子は、それぞれの基板
に独立に実装できるので、基板を共通化することにより
生じた配線、基板加工、放熱などの従来の不具合は解消
できる。またセラミック基板のSi基板接合部に放熱ビ
アを設けることにより、LDの放熱性をさらに向上でき
る。Since the optical element and the electric element can be independently mounted on the respective substrates, the conventional problems such as wiring, substrate processing, and heat radiation caused by sharing the substrates can be solved. Further, the heat radiation of the LD can be further improved by providing the heat radiation via in the Si substrate bonding portion of the ceramic substrate.
【0013】以下、本発明について図面を参照して詳細
に説明する。The present invention will be described in detail below with reference to the drawings.
【0014】図1は本発明を示す並列伝送型光モジュー
ルの一例で、図1(a)は断面図、図1(b)は平面図
である。実装基板、例えばアルミナなどのセラミック基
板1上に、光素子が搭載されたSi基板5が配置されて
いる。Si基板5は接着剤、半田、あるいは金属の拡散
でセラミック基板1に接合される。また、Si基板5は
通常の並列伝送型光モジュールの光基板と同等の構成で
あり、250μmピッチのLDアレイ2、ポリマ系アレ
イ光導波路3、光ファイバアレイ4が配置されている。
ポリマ系アレイ光導波路3では、一様でないLDアレイ
2のピッチを等間隔に変換している。光ファイバアレイ
4は異方性ウェットエッチングなどで形成したV溝6に
正確に位置決めされている。LDアレイ2のドライバI
C7とロジックIC8はSi基板5に近接してセラミッ
ク基板1上にフリップチップ実装される。LDアレイ2
とIC7との電気接続は、Si基板5にLDアレイ2と
同一ピッチで設けられた貫通穴10を通して行われる。
セラミック基板1の貫通穴10の部分には、予め表面が
例えば金(Au)のスルーホール電極が形成されてお
り、貫通穴10に形成した電極9に接続している。貫通
穴10は例えば光ファイバ用V溝6と同様に異方性ウェ
ットエッチングで形成される。貫通穴10を形成後、穴
部のSi表面に熱酸化膜などの絶縁膜を積層し、さらに
その上にLDアレイ2の引き出しAu電極9を形成す
る。引き出し電極9とセラミック基板1側のスルーホー
ル電極との接続は、例えばスルーホール電極上に金錫
(AuSn)半田を溶融して行われる。より高速の動作
を必要とする場合は、セラミック基板1を多層構造とし
たり、図2に示すように電気素子の接合電極が貫通穴1
0のスルーホール電極に半田バンプ11を介して直接接
続する構成となる。また、図3のように、セラミック基
板1のLDアレイ2実装部に放熱ビア12を形成するこ
とにより、LDアレイ2の放熱性をさらに向上すること
ができる。FIG. 1 is an example of a parallel transmission type optical module showing the present invention. FIG. 1 (a) is a sectional view and FIG. 1 (b) is a plan view. A Si substrate 5 on which an optical element is mounted is arranged on a mounting substrate, for example, a ceramic substrate 1 such as alumina. The Si substrate 5 is bonded to the ceramic substrate 1 with an adhesive, solder, or metal diffusion. The Si substrate 5 has the same structure as the optical substrate of a normal parallel transmission type optical module, and the LD array 2, the polymer array optical waveguide 3, and the optical fiber array 4 having a pitch of 250 μm are arranged.
In the polymer array optical waveguide 3, the pitch of the LD array 2 which is not uniform is converted into equal intervals. The optical fiber array 4 is accurately positioned in the V groove 6 formed by anisotropic wet etching or the like. Driver I of LD array 2
The C7 and the logic IC 8 are flip-chip mounted on the ceramic substrate 1 close to the Si substrate 5. LD array 2
And IC 7 are electrically connected to each other through through holes 10 formed in Si substrate 5 at the same pitch as LD array 2.
A through-hole electrode whose surface is, for example, gold (Au) is formed in advance in the through-hole 10 portion of the ceramic substrate 1 and is connected to the electrode 9 formed in the through-hole 10. The through hole 10 is formed by anisotropic wet etching similarly to the optical fiber V groove 6, for example. After the through hole 10 is formed, an insulating film such as a thermal oxide film is laminated on the Si surface of the hole portion, and the lead Au electrode 9 of the LD array 2 is further formed thereon. The lead electrode 9 and the through-hole electrode on the ceramic substrate 1 side are connected by, for example, melting gold-tin (AuSn) solder on the through-hole electrode. When a higher speed operation is required, the ceramic substrate 1 may have a multi-layer structure, or as shown in FIG.
The configuration is such that it is directly connected to the 0 through-hole electrode via the solder bump 11. Further, as shown in FIG. 3, by forming the heat dissipation vias 12 in the LD array 2 mounting portion of the ceramic substrate 1, the heat dissipation of the LD array 2 can be further improved.
【0015】さらに、信号配線を高速かつ高密度にする
場合には、図4のようにセラミック基板28上に多層の
ビルドアップ12が形成される。Further, when the signal wiring is made high speed and high density, a multilayer buildup 12 is formed on the ceramic substrate 28 as shown in FIG.
【0016】以上、Si基板をセラミック基板に貼り合
わせて重ねる構造を採用することにより、光素子に対す
る放熱性、高精度の位置決めの要求と電気素子に対する
高速電気配線の要求を同時に満たす実装基板が可能にな
り、従来困難であったギガヘルツレベルの高速の並列伝
送型光モジュールを実現できる。As described above, by adopting the structure in which the Si substrate is laminated on the ceramic substrate and laminated, a mounting substrate which simultaneously satisfies the requirements for heat dissipation to optical elements, high-precision positioning, and high-speed electrical wiring for electrical elements is possible. Thus, it is possible to realize a high-speed parallel transmission type optical module at a gigahertz level, which has been difficult in the past.
【0017】本発明では、アレイ素子としてアレイピッ
チ250μmの12チャネルのLDを示したがそれ以外
のピッチ、チャネルでも同様な効果が得られる。また、
LDアレイと光ファイバの間にポリマ系光導波路を配置
したが、他の材料の導波路、あるいは導波路がなくても
かまわない。In the present invention, a 12-channel LD having an array pitch of 250 μm is shown as an array element, but similar effects can be obtained with other pitches and channels. Also,
Although the polymer optical waveguide is arranged between the LD array and the optical fiber, the waveguide of another material or the waveguide may be omitted.
【0018】[0018]
【実施例】実施例1
図1に示す並列伝送型光モジュールの製造方法を図5に
示す工程断面図及び図6に示すフローシートを用いて説
明する。まず、アルミナ粉末、フラックス、有機バイン
ダ、溶剤、可塑剤をボールミル中で良く混合した後、ブ
レードによりキャリアテープ上へ伸展し、乾燥させグリ
ーンシートを作製する。グリーンシートに金型で穴開け
を行い、この中へ金属粉末で作製した導体ペーストを充
填し、導体パターンを印刷したものを複数枚積層して、
焼成し、セラミック多層配線基板1を作製する(工程
(a)、図5(a))。EXAMPLE 1 A method of manufacturing the parallel transmission type optical module shown in FIG. 1 will be described with reference to process sectional views shown in FIG. 5 and a flow sheet shown in FIG. First, alumina powder, flux, organic binder, solvent and plasticizer are thoroughly mixed in a ball mill, and then spread on a carrier tape with a blade and dried to produce a green sheet. The green sheet is punched with a mold, filled with a conductive paste made of metal powder, and a plurality of printed conductor patterns are laminated,
Firing is performed to produce the ceramic multilayer wiring board 1 (step (a), FIG. 5 (a)).
【0019】次に、光素子を搭載するSi基板5に異方
性ウェットエッチングにてV溝6及び貫通穴10を形成
する。Si基板5上に200μm角のエッチング窓を設
け、Siのエッチングを行うと、深さ約140μmの四
角錐状の穴10が形成される。穴部を含むSi基板表面
に熱酸化膜を形成後、LDアレイ2の引き出しAu電極
9をスパッタ法により形成する(工程(b)、図5
(b))。次に光導波路3を所定位置に形成する。光導
波路としては、従来公知のポリメチルメタアクリレート
(PMMA)、フッ素化ポリイミド、シロキサン系ポリ
マなどを用いて、これらの樹脂溶液あるいは前駆体溶液
をスピンコート法により塗布し、所定の硬化法に従って
硬化させ、フォトリソグラフィを用いて所定の形状に成
形する(工程(c)、図5(c))。次にSi基板5を
100μmの厚さになるまで裏面から研磨すると底部に
約60μm角の貫通穴が形成される。研磨後のSi基板
5の厚みは貫通穴10のピッチに依存し、貫通穴10を
千鳥状に配置してピッチを2倍に拡大すると、Si基板
5の厚さも2倍に拡大が可能となる。Next, the V groove 6 and the through hole 10 are formed in the Si substrate 5 on which the optical element is mounted by anisotropic wet etching. When a 200 μm square etching window is provided on the Si substrate 5 and Si is etched, a quadrangular pyramid-shaped hole 10 having a depth of about 140 μm is formed. After forming a thermal oxide film on the surface of the Si substrate including the holes, the extraction Au electrode 9 of the LD array 2 is formed by the sputtering method (step (b), FIG. 5).
(B)). Next, the optical waveguide 3 is formed at a predetermined position. As the optical waveguide, conventionally known polymethylmethacrylate (PMMA), fluorinated polyimide, siloxane-based polymer or the like is used, and these resin solutions or precursor solutions are applied by spin coating and cured according to a predetermined curing method. Then, it is formed into a predetermined shape using photolithography (step (c), FIG. 5C). Next, the Si substrate 5 is polished from the back surface to a thickness of 100 μm, so that a through hole of about 60 μm square is formed at the bottom. The thickness of the Si substrate 5 after polishing depends on the pitch of the through holes 10, and if the through holes 10 are arranged in a staggered manner and the pitch is doubled, the thickness of the Si substrate 5 can also be doubled. .
【0020】このように形成した光素子搭載用のSi基
板5の貫通穴がセラミック多層配線基板1のスルーホー
ル電極と接合できるように位置合わせして、エポシキ系
接着剤、半田、あるいは金属の拡散にて貼り合わせた
後、スルーホール電極上に金錫(AuSn)半田を溶融
して、引き出し電極9との接合を行う(工程(e)、図
5(e))。The through hole of the Si substrate 5 for mounting the optical element thus formed is aligned so that it can be joined to the through hole electrode of the ceramic multilayer wiring substrate 1, and epoxy adhesive, solder, or metal diffusion. After bonding by, the gold-tin (AuSn) solder is melted on the through-hole electrode and joined to the extraction electrode 9 (step (e), FIG. 5 (e)).
【0021】最後に、基板1上にドライバIC7及びロ
ジックIC8をフリップチップ接合し、Si基板5には
アレイピッチ250μmの12チャネルLD2と光ファ
イバ4とを接合して、図5(f)に示す並列伝送型光モ
ジュールが完成する(工程(f))。Finally, the driver IC 7 and the logic IC 8 are flip-chip bonded onto the substrate 1, the 12-channel LD 2 having an array pitch of 250 μm and the optical fiber 4 are bonded onto the Si substrate 5, as shown in FIG. The parallel transmission type optical module is completed (step (f)).
【0022】尚、上記実施例では、貫通穴を形成して、
電気接続を行っているが、例えば、貫通穴の代わりに、
基板端部を斜めに成形して、金属電極を基板上面から底
面へ続く様に形成しても良く、光素子への電気接続を行
う金属電極がSi基板上で固定される構成であり、Si
基板底面でセラミック基板との直接接続が可能であれ
ば、どのような構成であっても良い。In the above embodiment, a through hole is formed,
I have an electrical connection, but instead of, for example, a through hole,
The end portion of the substrate may be formed obliquely, and the metal electrode may be formed so as to continue from the top surface to the bottom surface of the substrate, and the metal electrode for electrical connection to the optical element is fixed on the Si substrate.
Any structure may be used as long as it can be directly connected to the ceramic substrate on the bottom surface of the substrate.
【0023】実施例2
図2に示す並列伝送型光モジュールを製造した。この例
では、Si基板5のサイズはセラミック基板1の主面を
ほぼ覆う大きさのものを使用し、実施例1で示した光素
子用の貫通穴の他に、電気素子を搭載するための貫通穴
を形成し、各貫通穴内部に熱酸化膜を形成後、実施例1
と同様に光導波路3を形成し、セラミック基板と貼り合
わせ、その後、光素子をSi基板上の金属電極9に、光
ファイバ4をV溝6に、電気素子7、8を半田バンプに
よりセラミック基板のスルーホール電極と接続して形成
した。Example 2 A parallel transmission type optical module shown in FIG. 2 was manufactured. In this example, the size of the Si substrate 5 is such that it substantially covers the main surface of the ceramic substrate 1, and in addition to the through holes for optical elements shown in Example 1, electrical elements are mounted. After forming through-holes and forming a thermal oxide film inside each through-hole, Example 1
Similarly, the optical waveguide 3 is formed and bonded to a ceramic substrate. After that, the optical element is formed on the metal electrode 9 on the Si substrate, the optical fiber 4 is formed on the V groove 6, and the electric elements 7 and 8 are formed on the ceramic substrate by solder bumps. It was formed by connecting to the through-hole electrode.
【0024】実施例3
実施例1と同様にアルミナ製のグリーンシートを必要枚
貼り合わせた後、金型を用いて穴を開けることにより放
熱ビア12を形成する。その後、実施例1と同様にSi
基板5を貼り合わせ、光素子、電気素子を実装すること
で、図3に示す並列伝送型光モジュールが完成する。こ
こで形成した放熱ビアの大きさはφ500μm程度とす
ることで、高い放熱性が得られる。また放熱ビアを介し
て放熱フィンなどの取り付けも可能である。Example 3 Similar to Example 1, after a required number of alumina green sheets were bonded together, a heat radiating via 12 was formed by making a hole using a mold. Then, as in Example 1, Si
The parallel transmission type optical module shown in FIG. 3 is completed by bonding the substrate 5 and mounting the optical element and the electric element. High heat dissipation can be obtained by setting the size of the heat dissipation via formed here to about φ500 μm. It is also possible to attach a radiation fin or the like via a radiation via.
【0025】実施例4
実施例1と同様に、Si基板5の貼り合わせを行った
後、電気素子実装部に樹脂製ビルドアップ13を形成す
る。樹脂製ビルドアップ13は次に示す手順で形成され
る。
1.感光性絶縁樹脂を基板に塗布し、露光、現像によ
り、絶縁パターンにエッチングする。
2.フォトレジストで、導体パターンを形成する。
3.無電界メッキ等により、導体をつける。
4.フォトレジストを取り除く。
以上の工程を必要回繰り返すことで、所望の層構造のビ
ルドアップが形成できる。Example 4 As in Example 1, after the Si substrate 5 is bonded, the resin buildup 13 is formed on the electric element mounting portion. The resin buildup 13 is formed by the following procedure. 1. A photosensitive insulating resin is applied to the substrate, and the insulating pattern is etched by exposure and development. 2. A conductive pattern is formed with photoresist. 3. Attach the conductor by electroless plating. 4. Remove photoresist. By repeating the above steps as many times as necessary, a buildup having a desired layer structure can be formed.
【0026】このビルドアップ13上に電気素子7、8
をフリップチップ接続して図4に示す並列伝送型光モジ
ュールが完成する。The electric elements 7 and 8 are mounted on the build-up 13.
Are flip-chip connected to complete the parallel transmission type optical module shown in FIG.
【0027】[0027]
【発明の効果】以上説明したように本発明によれば、高
速信号の送受信が可能な並列伝送型光モジュールを実現
できる。その理由は、Si基板上に光素子への電気的接
続を行う金属電極を形成し、該金属電極をSi基板底面
まで延在させてその部分でセラミック基板と直接接続し
ているため、従来のワイヤボンディングによる手法と比
較して、信頼性の高いセラミック基板内部の配線との接
続が可能となるからである。又、ワイヤボンディングが
不要となるため、クロストークが解消され、従来より、
光素子と電気素子とを近接させることが可能となり、ギ
ガヘルツ以上の高速信号への対応も可能となる。As described above, according to the present invention, a parallel transmission type optical module capable of transmitting and receiving high speed signals can be realized. The reason is that a metal electrode for electrically connecting to an optical element is formed on a Si substrate, the metal electrode is extended to the bottom surface of the Si substrate, and the portion is directly connected to the ceramic substrate. This is because, as compared with the method using wire bonding, it is possible to connect the wiring inside the ceramic substrate with high reliability. Also, since wire bonding is unnecessary, crosstalk is eliminated, and
It is possible to bring the optical element and the electric element close to each other, and it is possible to cope with high-speed signals of gigahertz or higher.
【図1】本発明の並列伝送型光モジュール構成の断面図
(a)と上面図(b)である。FIG. 1 is a cross-sectional view (a) and a top view (b) of a parallel transmission type optical module configuration of the present invention.
【図2】本発明の他の実施形態になる並列伝送型光モジ
ュールの断面図である。FIG. 2 is a cross-sectional view of a parallel transmission type optical module according to another embodiment of the present invention.
【図3】本発明の他の実施形態になる並列伝送型光モジ
ュールの断面図である。FIG. 3 is a sectional view of a parallel transmission type optical module according to another embodiment of the present invention.
【図4】本発明の他の実施形態になる並列伝送型光モジ
ュール構成の断面図(a)と上面図(b)である。FIG. 4 is a sectional view (a) and a top view (b) of a parallel transmission type optical module configuration according to another embodiment of the present invention.
【図5】図1に示す並列伝送型光モジュールの製造方法
を説明する工程断面図である。5A to 5C are process cross-sectional views illustrating a method of manufacturing the parallel transmission type optical module shown in FIG.
【図6】図5の製造方法のフローシートである。6 is a flow sheet of the manufacturing method of FIG.
【図7】従来の並列伝送型光モジュールの構成断面図
(a)と上面図(b)である。FIG. 7 is a cross-sectional view (a) and a top view (b) of a conventional parallel transmission type optical module.
1・・・セラミック基板 2・・・LDアレイ 3・・・光導波路アレイ 4・・・光ファイバアレイ 5・・・Si基板 6・・・V溝 7・・・ドライバIC 8・・・ロジックIC 9・・・電極 10・・・貫通穴 11・・・半田バンプ 12・・・放熱ビア 13・・・ビルドアップ 1 ... Ceramic substrate 2 ... LD array 3 ... Optical waveguide array 4 ... Optical fiber array 5: Si substrate 6 ... V groove 7 ... Driver IC 8 ... Logic IC 9 ... Electrode 10 ... through hole 11 ... Solder bump 12 ... Heat dissipation via 13 ... Build up
フロントページの続き (56)参考文献 特開 平11−97797(JP,A) 特開 平8−78657(JP,A) 特開 平10−275957(JP,A) 特開 平7−273401(JP,A) 特開 平2−220491(JP,A) 特開 平5−304306(JP,A) 特開 平10−311936(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01S 5/00 - 5/50 G02B 6/42 H01L 33/00 H04B 10/00 JICSTファイル(JOIS)Continuation of front page (56) Reference JP-A-11-97797 (JP, A) JP-A-8-78657 (JP, A) JP-A-10-275957 (JP, A) JP-A-7-273401 (JP , A) JP-A-2-220491 (JP, A) JP-A-5-304306 (JP, A) JP-A-10-311936 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB) Name) H01S 5/00-5/50 G02B 6/42 H01L 33/00 H04B 10/00 JISST file (JOIS)
Claims (16)
i基板が貼り合わされており、少なくとも光素子とセラ
ミック基板との電気接続が、該光素子がSi基板表面に
絶縁層を介して形成された金属電極と電気的に接続さ
れ、該金属電極がSi基板底面まで延在してセラミック
基板上に形成された電極と直接接続されて成されること
を特徴とする並列伝送型光モジュール。1. An S in which an optical element is mounted on a ceramic substrate.
The i substrate is bonded, and at least the electrical connection between the optical element and the ceramic substrate is electrically connected to the metal electrode formed on the surface of the Si substrate via the insulating layer, and the metal electrode is connected to the Si electrode. A parallel transmission type optical module, which is formed by directly connecting to an electrode formed on a ceramic substrate and extending to the bottom surface of the substrate.
ファイバが配置されていることを特徴とする請求項1に
記載の並列伝送型光モジュール。2. The parallel transmission type optical module according to claim 1, wherein an optical waveguide and an optical fiber are further arranged on the Si substrate.
れていることを特徴とする請求項1又は2に記載の並列
伝送型光モジュール。3. The parallel transmission type optical module according to claim 1, wherein the ceramic substrate is formed in a multilayer structure.
た樹脂製ビルドアップ上に配置されることを特徴とする
請求項1〜3のいずれか1項に記載の並列伝送型光モジ
ュール。4. The parallel transmission type optical module according to claim 1, wherein the electric element is arranged on a resin buildup formed on a ceramic substrate.
続のための金属電極は、Si基板に形成された貫通穴を
通してSi基板底面まで延在していることを特徴とする
請求項1〜4のいずれか1項に記載の並列伝送型光モジ
ュール。5. The metal electrode for electrical connection between the optical element and the ceramic substrate extends to the bottom surface of the Si substrate through a through hole formed in the Si substrate. The parallel transmission type optical module according to any one of 1.
性エッチングの後、Si基板裏面を研磨することで形成
されたものであることを特徴とする請求項5に記載の並
列伝送型光モジュール。6. The parallel transmission type according to claim 5, wherein the through hole is formed by polishing the rear surface of the Si substrate after anisotropic etching from the upper surface of the Si substrate. Optical module.
ビアを設けたことを特徴とする請求項1〜6のいずれか
1項に記載の並列伝送型光モジュール。7. The parallel transmission type optical module according to claim 1, wherein a heat dissipation via is provided in the Si substrate joint portion of the ceramic substrate.
り合わされており、電気素子は、Si基板に形成した貫
通穴を通してセラミック基板に接続されていることを特
徴とする請求項5、6又は7に記載の並列伝送型光モジ
ュール。8. The Si substrate is bonded to substantially the entire surface of the ceramic substrate, and the electric element is connected to the ceramic substrate through a through hole formed in the Si substrate. The parallel transmission type optical module described in.
i基板を貼り合わせてなる並列伝送型光モジュールの製
造方法であって、Si基板表面に絶縁層を介して該Si
基板底面まで延在する金属電極を形成する工程、該Si
基板をセラミック基板上に、前記金属電極とセラミック
基板上に形成した電極とが直接接続されるように貼り合
わせる工程、前記金属電極に光素子を電気的に接続する
工程、とを有してなる並列伝送型光モジュールの製造方
法。9. A ceramic substrate on which an optical element is mounted, S
A method of manufacturing a parallel transmission type optical module, which comprises bonding i substrates together, the method comprising:
Forming a metal electrode extending to the bottom surface of the substrate;
A step of laminating a substrate on a ceramic substrate so that the metal electrode and an electrode formed on the ceramic substrate are directly connected; and a step of electrically connecting an optical element to the metal electrode. Method for manufacturing parallel transmission type optical module.
光ファイバが配置されており、光ファイバを配置するた
めの溝形成工程を有することを特徴とする請求項9に記
載の並列伝送型光モジュールの製造方法。10. The Si substrate further includes an optical waveguide,
The method for manufacturing a parallel transmission type optical module according to claim 9, wherein an optical fiber is arranged, and a groove forming step for arranging the optical fiber is included.
工程を有する請求項9又は10に記載の並列伝送型光モ
ジュールの製造方法。11. The method of manufacturing a parallel transmission type optical module according to claim 9, further comprising the step of forming a ceramic substrate in a multilayer structure.
プを形成する工程、及び該ビルドアップ上に電気素子を
配置する工程を有する請求項9乃至11に記載の並列伝
送型光モジュールの製造方法。12. The method of manufacturing a parallel transmission type optical module according to claim 9, further comprising a step of forming a resin build-up on the ceramic substrate and a step of disposing an electric element on the build-up.
溝形成と同時に、前記光素子とセラミック基板との電気
接続のための金属電極をSi基板底面まで延在させるた
めの貫通穴を形成する工程を有する請求項9又は10に
記載の並列伝送型光モジュールの製造方法。13. A through hole for extending a metal electrode for electrical connection between the optical element and the ceramic substrate to the bottom surface of the Si substrate is formed at the same time as forming a groove for arranging an optical fiber in the Si substrate. The method for manufacturing a parallel transmission type optical module according to claim 9 or 10, further comprising steps.
方性エッチングの後、Si基板裏面を研磨して形成する
ことを特徴とする請求項13に記載の並列伝送型光モジ
ュールの製造方法。14. The method of manufacturing a parallel transmission type optical module according to claim 13, wherein the through hole is formed by anisotropically etching the upper surface of the Si substrate and then polishing the back surface of the Si substrate. .
熱ビアを形成する工程を有することを特徴とする請求項
9乃至14のいずれか1項に記載の並列伝送型光モジュ
ールの製造方法。15. The method of manufacturing a parallel transmission type optical module according to claim 9, further comprising the step of forming a heat dissipation via in a Si substrate bonding portion of the ceramic substrate.
板を貼り合わされており、電気素子を、Si基板に形成
した貫通穴を介してセラミック基板に接続することを特
徴とする請求項13、14又は15に記載の並列伝送型
光モジュールの製造方法。16. A Si substrate covering substantially the entire surface of the ceramic substrate is bonded, and the electric element is connected to the ceramic substrate through a through hole formed in the Si substrate. 15. The method for manufacturing a parallel transmission type optical module according to item 15.
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JP17709599A JP3405402B2 (en) | 1999-06-23 | 1999-06-23 | Parallel transmission type optical module and method of manufacturing the same |
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JP3405402B2 true JP3405402B2 (en) | 2003-05-12 |
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